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vphy: Added API for resetting the MMCM.

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This commit is contained in:
Gilbert Magnaye 2015-11-11 19:19:55 -08:00 • committed by Nava kishore Manne
parent f93d8928e0
commit 5f495caaab
3 changed files with 60 additions and 1 deletions
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58
XilinxProcessorIPLib/drivers/vphy/src/xvphy.c
View file

@ -45,7 +45,8 @@
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.0 als 10/19/15 Initial release.
* 1.0 als, 10/19/15 Initial release.
* gm
* </pre>
*
*******************************************************************************/
@ -1422,6 +1423,12 @@ void XVphy_MmcmStart(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)
u32 Status;
u8 Retry;
if ((InstancePtr->Config.TxProtocol == XVPHY_PROTOCOL_HDMI) ||
(InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_HDMI)) {
/* Enable MMCM Locked Masking */
XVphy_MmcmLockedMaskEnable(InstancePtr, QuadId, Dir, TRUE);
}
/* Enable MMCM. */
XVphy_MmcmPowerDown(InstancePtr, QuadId, Dir, FALSE);
@ -1444,6 +1451,55 @@ void XVphy_MmcmStart(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)
/* Toggle MMCM reset. */
XVphy_MmcmReset(InstancePtr, QuadId, Dir, FALSE);
if ((InstancePtr->Config.TxProtocol == XVPHY_PROTOCOL_HDMI) ||
(InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_HDMI)) {
/* Disable MMC Locked Masking */
XVphy_MmcmLockedMaskEnable(InstancePtr, QuadId, Dir, FALSE);
}
}
/*****************************************************************************/
/**
* This function will reset the mixed-mode clock manager (MMCM) core.
*
* @param InstancePtr is a pointer to the XVphy core instance.
* @param QuadId is the GT quad ID to operate on.
* @param Dir is an indicator for TX or RX.
* @param Enable is an indicator whether to "Enable" the locked mask
* if set to 1. If set to 0: reset, then disable.
*
* @return None.
*
* @note None.
*
******************************************************************************/
void XVphy_MmcmLockedMaskEnable(XVphy *InstancePtr, u8 QuadId,
XVphy_DirectionType Dir, u8 Enable)
{
u32 RegOffsetCtrl;
u32 RegVal;
XVphy_SelQuad(InstancePtr, QuadId);
if (Dir == XVPHY_DIR_TX) {
RegOffsetCtrl = XVPHY_MMCM_TXUSRCLK_CTRL_REG;
}
else {
RegOffsetCtrl = XVPHY_MMCM_RXUSRCLK_CTRL_REG;
}
/* Assert reset. */
RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl);
RegVal |= XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK;
XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl, RegVal);
if (!Enable) {
/* De-assert reset. */
RegVal &= ~XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK;
XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl,
RegVal);
}
}
/*****************************************************************************/

2
XilinxProcessorIPLib/drivers/vphy/src/xvphy.h
View file

@ -707,6 +707,8 @@ void XVphy_MmcmReset(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir,
void XVphy_MmcmPowerDown(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir,
u8 Hold);
void XVphy_MmcmStart(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir);
void XVphy_MmcmLockedMaskEnable(XVphy *InstancePtr, u8 QuadId,
XVphy_DirectionType Dir, u8 Enable);
void XVphy_BufgGtReset(XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Reset);
void XVphy_SetBufgGtDiv(XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Div);
void XVphy_IBufDsEnable(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir,

1
XilinxProcessorIPLib/drivers/vphy/src/xvphy_hw.h
View file

@ -457,6 +457,7 @@
#define XVPHY_MMCM_USRCLK_CTRL_CFG_SUCCESS_MASK 0x10
#define XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK 0x20
#define XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK 0x400
#define XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK 0x800
/* 0x124, 0x144: MMCM_TXUSRCLK_REG1, MMCM_RXUSRCLK_REG1 */
#define XVPHY_MMCM_USRCLK_REG1_DIVCLK_MASK \
0x00000FF