vphy: Added API for resetting the MMCM.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> Acked-by: Srikanth Vemula <svemula@xilinx.com>
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3 changed files with 60 additions and 1 deletions
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@ -45,7 +45,8 @@
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.0 als 10/19/15 Initial release.
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* 1.0 als, 10/19/15 Initial release.
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* gm
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* </pre>
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*
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*******************************************************************************/
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@ -1422,6 +1423,12 @@ void XVphy_MmcmStart(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)
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u32 Status;
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u8 Retry;
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if ((InstancePtr->Config.TxProtocol == XVPHY_PROTOCOL_HDMI) ||
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(InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_HDMI)) {
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/* Enable MMCM Locked Masking */
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XVphy_MmcmLockedMaskEnable(InstancePtr, QuadId, Dir, TRUE);
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}
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/* Enable MMCM. */
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XVphy_MmcmPowerDown(InstancePtr, QuadId, Dir, FALSE);
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@ -1444,6 +1451,55 @@ void XVphy_MmcmStart(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir)
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/* Toggle MMCM reset. */
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XVphy_MmcmReset(InstancePtr, QuadId, Dir, FALSE);
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if ((InstancePtr->Config.TxProtocol == XVPHY_PROTOCOL_HDMI) ||
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(InstancePtr->Config.RxProtocol == XVPHY_PROTOCOL_HDMI)) {
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/* Disable MMC Locked Masking */
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XVphy_MmcmLockedMaskEnable(InstancePtr, QuadId, Dir, FALSE);
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}
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}
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/*****************************************************************************/
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/**
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* This function will reset the mixed-mode clock manager (MMCM) core.
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*
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* @param InstancePtr is a pointer to the XVphy core instance.
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* @param QuadId is the GT quad ID to operate on.
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* @param Dir is an indicator for TX or RX.
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* @param Enable is an indicator whether to "Enable" the locked mask
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* if set to 1. If set to 0: reset, then disable.
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*
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* @return None.
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*
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* @note None.
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*
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******************************************************************************/
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void XVphy_MmcmLockedMaskEnable(XVphy *InstancePtr, u8 QuadId,
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XVphy_DirectionType Dir, u8 Enable)
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{
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u32 RegOffsetCtrl;
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u32 RegVal;
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XVphy_SelQuad(InstancePtr, QuadId);
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if (Dir == XVPHY_DIR_TX) {
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RegOffsetCtrl = XVPHY_MMCM_TXUSRCLK_CTRL_REG;
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}
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else {
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RegOffsetCtrl = XVPHY_MMCM_RXUSRCLK_CTRL_REG;
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}
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/* Assert reset. */
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RegVal = XVphy_ReadReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl);
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RegVal |= XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK;
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XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl, RegVal);
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if (!Enable) {
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/* De-assert reset. */
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RegVal &= ~XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK;
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XVphy_WriteReg(InstancePtr->Config.BaseAddr, RegOffsetCtrl,
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RegVal);
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}
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}
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/*****************************************************************************/
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@ -707,6 +707,8 @@ void XVphy_MmcmReset(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir,
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void XVphy_MmcmPowerDown(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir,
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u8 Hold);
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void XVphy_MmcmStart(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir);
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void XVphy_MmcmLockedMaskEnable(XVphy *InstancePtr, u8 QuadId,
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XVphy_DirectionType Dir, u8 Enable);
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void XVphy_BufgGtReset(XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Reset);
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void XVphy_SetBufgGtDiv(XVphy *InstancePtr, XVphy_DirectionType Dir, u8 Div);
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void XVphy_IBufDsEnable(XVphy *InstancePtr, u8 QuadId, XVphy_DirectionType Dir,
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@ -457,6 +457,7 @@
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#define XVPHY_MMCM_USRCLK_CTRL_CFG_SUCCESS_MASK 0x10
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#define XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK 0x20
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#define XVPHY_MMCM_USRCLK_CTRL_PWRDWN_MASK 0x400
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#define XVPHY_MMCM_USRCLK_CTRL_LOCKED_MASK_MASK 0x800
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/* 0x124, 0x144: MMCM_TXUSRCLK_REG1, MMCM_RXUSRCLK_REG1 */
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#define XVPHY_MMCM_USRCLK_REG1_DIVCLK_MASK \
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0x00000FF
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