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xilskey: Added DFT control bits programming

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DFT JTAG disable and DFT mode disable control bits
programming and reading from status register are added
to efuse example and also input macros in xilskey_input.h
file.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
VNSL Durga 2015-10-09 22:44:49 +05:30 • committed by Nava kishore Manne
parent 1553beac28
commit 601ba781fb
2 changed files with 37 additions and 0 deletions
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21
lib/sw_services/xilskey/examples/xilskey_efuse_example.c
View file

@ -157,6 +157,8 @@
* done based on the platform and Modified example
* to support both Zynq PL's eFuse and also Ultrascale's
* eFuse.
* 4.00 vns 09/10/15 Added DFT JTAG disable and DFT MODE disable
* programming and reading options for Zynq eFuse PS.
*
****************************************************************************/
/***************************** Include Files *********************************/
@ -229,6 +231,8 @@
#define XSK_EFUSEPS_STATUS_WP_BIT_HIGH 0x2000
#define XSK_EFUSEPS_STATUS_RSA_EN 0x400
#define XSK_EFUSEPS_STATUS_ROM_128_CRC 0x800
#define XSK_EFUSEPS_STATUS_DFT_JTAG_DISABLE 0x200
#define XSK_EFUSEPS_STATUS_DFT_MODE_DISABLE 0x100
/*
* PL efuse status bit definitions of Zynq
@ -321,6 +325,21 @@ int main()
xil_printf("EfusePS status bits : 128k CRC check on ROM disabled\n\r");
}
if (PsStatusBits & XSK_EFUSEPS_STATUS_DFT_JTAG_DISABLE) {
xil_printf("EfusePS status bits : DFT JTAG is disabled\n\r");
}
else {
xil_printf("EfusePS status bits : DFT JTAG is enabled\n\r");
}
if (PsStatusBits & XSK_EFUSEPS_STATUS_DFT_MODE_DISABLE) {
xil_printf("EfusePS status bits : DFT mode is disabled\n\r");
}
else {
xil_printf("EfusePS status bits : DFT mode is enabled\n\r");
}
/**
* Write the PS eFUSE as defined in xilskeyinput.h
*/
@ -656,6 +675,8 @@ u32 XilSKey_EfusePs_InitData(XilSKey_EPs *PsInstancePtr)
PsInstancePtr->EnableRsaAuth = XSK_EFUSEPS_ENABLE_RSA_AUTH;
PsInstancePtr->EnableRom128Crc = XSK_EFUSEPS_ENABLE_ROM_128K_CRC;
PsInstancePtr->EnableRsaKeyHash = XSK_EFUSEPS_ENABLE_RSA_KEY_HASH;
PsInstancePtr->DisableDftJtag = XSK_EFUSEPS_DISABLE_DFT_JTAG;
PsInstancePtr->DisableDftMode = XSK_EFUSEPS_DISABLE_DFT_MODE;
if (PsInstancePtr->EnableRsaKeyHash == TRUE) {
/**

16
lib/sw_services/xilskey/examples/xilskey_input.h
View file

@ -67,6 +67,14 @@
* TRUE will burn the ROM 128k crc bit. Every successive boot after this,
* BootROM will calculate 128k crc. FALSE will not modify the ROM CRC128K bit.
*
* #define XSK_EFUSEPS_DISABLE_DFT_JTAG FALSE
* TRUE will disable DFT JTAG permanently.
* FALSE will not modify the eFuse PS DFT JTAG disable bit
*
* #define XSK_EFUSEPS_DISABLE_DFT_MODE FALSE
* TRUE will disable DFT mode permanently.
* FALSE will not modify the eFuse PS DFT mode disable bit
*
* #define XSK_EFUSEPS_ENABLE_RSA_KEY_HASH FALSE
* TRUE will burn the eFUSE hash, that is given in XSK_EFUSEPS_RSA_KEY_HASH_VALUE
* when write API is used. TRUE will read the eFUSE hash when read API is used
@ -378,6 +386,8 @@
* to access Master Jtag primitive and also added
* extra control bits and secure bits for Ultrascale's
* eFuse.
* 4.00 vns 09/10/15 Added DFT JTAG disable and DFT MODE disable programming
* options for Zynq eFuse PS.
*
* </pre>
*
@ -649,6 +659,12 @@ extern "C" {
#define XSK_EFUSEPS_ENABLE_ROM_128K_CRC FALSE /**< Enable the ROM
* code 128K crc eFUSE Bit
*/
#define XSK_EFUSEPS_DISABLE_DFT_JTAG FALSE /**< DFT jtag
* Disable
*/
#define XSK_EFUSEPS_DISABLE_DFT_MODE FALSE /**< DFT mode
* Disable
*/
#define XSK_EFUSEPS_ENABLE_RSA_KEY_HASH FALSE /**< Enabling this
* RsaKeyHashValue[64] is
* written to eFUSE array