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bsp: a9: change in xil_cache APIs

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This patch modifies Xil_DCacheInvalidateRange and Xil_DCacheFlushRange
to remove unnecessary dsb in the APIs. It also adds necessary
Xil_L2CacheSync in Xil_L2CacheInvalidateRange API.

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-05-13 12:42:04 +05:30 • committed by Nava kishore Manne
parent ed26a3d6f0
commit 6565a67b0e
2 changed files with 20 additions and 5 deletions
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6
lib/bsp/standalone/src/changelog.txt
View file

@ -223,4 +223,10 @@
* and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
* caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
* of L2Cache is done later.
* 5.1 pkp 12/05/15 Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
* Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
* taking long time to fix CR#853097. L2CacheSync is added into
* Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
* Xil_L2CacheInvalidate APIs are modified to flush the complete stack
* instead of just System Stack
*****************************************************************************************/

19
lib/bsp/standalone/src/cortexa9/xil_cache.c
View file

@ -82,6 +82,14 @@
* 5.00 kvn 12/15/14 Xil_L2CacheInvalidate was modified to fix CR# 838835. L2 Cache
* has stack memory which has return address. Before invalidating
* cache, stack memory was flushed first and L2 Cache is invalidated.
* 5.01 pkp 05/12/15 Xil_DCacheInvalidateRange and Xil_DCacheFlushRange is modified
* to remove unnecessary dsb in the APIs. Instead of using dsb
* for L2 Cache, L2CacheSync has been used for each L2 cache line
* and single dsb has been used for L1 cache. Also L2CacheSync is
* added into Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate
* and Xil_L2CacheInvalidate APIs are modified to flush the complete
* stack instead of just System Stack
*
* </pre>
*
******************************************************************************/
@ -106,7 +114,7 @@
#ifdef __GNUC__
extern s32 _stack_end;
extern s32 _stack;
extern s32 __undef_stack;
#endif
/****************************************************************************
@ -350,7 +358,7 @@ void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
while (tempadr < tempend) {
/* Invalidate L2 cache line */
*L2CCOffset = tempadr;
dsb();
Xil_L2CacheSync();
#ifdef __GNUC__
/* Invalidate L1 Data cache line */
__asm__ __volatile__("mcr " \
@ -477,7 +485,7 @@ void Xil_DCacheFlushRange(INTPTR adr, u32 len)
#endif
/* Flush L2 cache line */
*L2CCOffset = LocalAddr;
dsb();
Xil_L2CacheSync();
LocalAddr += cacheline;
}
}
@ -756,7 +764,7 @@ void Xil_L1DCacheInvalidate(void)
#ifdef __GNUC__
stack_end = (u32)&_stack_end;
stack_start = (u32)&_stack;
stack_start = (u32)&__undef_stack;
stack_size=stack_start-stack_end;
/*Flush stack memory to save return address*/
@ -1359,7 +1367,7 @@ void Xil_L2CacheInvalidate(void)
#ifdef __GNUC__
u32 stack_start,stack_end,stack_size;
stack_end = (u32)&_stack_end;
stack_start = (u32)&_stack;
stack_start = (u32)&__undef_stack;
stack_size=stack_start-stack_end;
/*Flush stack memory to save return address*/
@ -1446,6 +1454,7 @@ void Xil_L2CacheInvalidateRange(u32 adr, u32 len)
while (LocalAddr < end) {
*L2CCOffset = LocalAddr;
Xil_L2CacheSync();
LocalAddr += cacheline;
}