tpg: Added html files.
Modified tpg.mdd and tpg.tcl files. Signed-off-by: Durga challa <vnsldurg@xilinx.com>
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3 changed files with 5 additions and 89 deletions
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@ -29,7 +29,6 @@
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# this Software without prior written authorization from Xilinx.
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#
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##############################################################################
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OPTION psf_version = 2.1;
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BEGIN driver tpg
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@ -37,6 +37,9 @@
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###############################################################
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proc generate {drv_handle} {
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xdefine_include_file $drv_handle "xparameters.h" "tpg" "C_BASEADDR" "C_HIGHADDR"
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xdefine_canonical_xpars $drv_handle "xparameters.h" "tpg" "C_BASEADDR" "C_HIGHADDR"
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xdefine_include_file $drv_handle "xparameters.h" "TPG" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_S_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_FORMAT" "C_S_AXI_CLK_FREQ_HZ" "C_ACTIVE_ROWS" "C_ACTIVE_COLS" "C_PATTERN_CONTROL" "C_MOTION_SPEED" "C_CROSS_HAIRS" "C_ZPLATE_HOR_CONTROL" "C_ZPLATE_VER_CONTROL" "C_BOX_SIZE" "C_BOX_COLOR" "C_STUCK_PIXEL_THRESH" "C_NOISE_GAIN" "C_BAYER_PHASE" "C_HAS_INTC_IF" "C_ENABLE_MOTION"
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xdefine_config_file $drv_handle "xtpg_g.c" "XTpg" "DEVICE_ID" "C_BASEADDR" "C_S_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_FORMAT" "C_S_AXI_CLK_FREQ_HZ" "C_ACTIVE_ROWS" "C_ACTIVE_COLS" "C_PATTERN_CONTROL" "C_MOTION_SPEED" "C_CROSS_HAIRS" "C_ZPLATE_HOR_CONTROL" "C_ZPLATE_VER_CONTROL" "C_BOX_SIZE" "C_BOX_COLOR" "C_STUCK_PIXEL_THRESH" "C_NOISE_GAIN" "C_BAYER_PHASE" "C_HAS_INTC_IF" "C_ENABLE_MOTION"
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xdefine_canonical_xpars $drv_handle "xparameters.h" "TPG" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_S_AXIS_VIDEO_FORMAT" "C_M_AXIS_VIDEO_FORMAT" "C_S_AXI_CLK_FREQ_HZ" "C_ACTIVE_ROWS" "C_ACTIVE_COLS" "C_PATTERN_CONTROL" "C_MOTION_SPEED" "C_CROSS_HAIRS" "C_ZPLATE_HOR_CONTROL" "C_ZPLATE_VER_CONTROL" "C_BOX_SIZE" "C_BOX_COLOR" "C_STUCK_PIXEL_THRESH" "C_NOISE_GAIN" "C_BAYER_PHASE" "C_HAS_INTC_IF" "C_ENABLE_MOTION"
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}
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@ -1,86 +0,0 @@
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/*****************************************************************************
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*
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* Copyright (C) 2001 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"),to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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*****************************************************************************/
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/**
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*
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* @file example.c
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*
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* This file demonstrates how to use Xilinx Test Pattern Generator (TPG)
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* ore pcore driver functions.
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*
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*
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* ***************************************************************************
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*/
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#include "tpg.h"
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#include "xparameters.h"
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/***************************************************************************/
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// Test Pattern Generator Register Reading Example
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// This function provides an example of how to read the current configuration
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// settings of the TPG core.
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/***************************************************************************/
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void report_tpg_settings(u32 BaseAddress) {
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u32 status, reg_val;
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unsigned char inchar=0;
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xil_printf("Test Pattern Generator Core Configuration:\r\n");
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xil_printf(" Enable Bit: %1d\r\n", TPG_ReadReg(BaseAddress, TPG_CONTROL) & TPG_CTL_EN_MASK);
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xil_printf(" Register Update Bit: %1d\r\n", (TPG_ReadReg(BaseAddress, TPG_CONTROL) & TPG_CTL_RUE_MASK) >> 1);
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xil_printf(" Reset Bit: %1d\r\n", TPG_ReadReg(BaseAddress, TPG_CONTROL) & TPG_RST_RESET);
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status = TPG_ReadReg(BaseAddress, TPG_STATUS);
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xil_printf(" TPG Status: %08x \r\n", status);
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xil_printf(" Core Version: %1d.%1d\r\n", TPG_ReadReg(BaseAddress, TPG_VERSION));
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reg_val = TPG_ReadReg(BaseAddress, TPG_CONTROL );
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xil_printf("TPG_CONTROL : %8x\r\n", reg_val);
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reg_val = TPG_ReadReg(BaseAddress, TPG_IRQ_EN );
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xil_printf("TPG_IRQ_EN : %8x\r\n", reg_val);
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reg_val = (TPG_ReadReg(BaseAddress, TPG_ACTIVE_SIZE ) && 0x1FFF);
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xil_printf("Active Rows : %8d\r\n", reg_val);
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reg_val = (TPG_ReadReg(BaseAddress, TPG_ACTIVE_SIZE) >> 16);
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xil_printf("Active Columns : %8d\r\n", reg_val);
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xil_printf("Press Space to continue!\r\n", reg_val);
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while (inchar != ' ') inchar = inbyte();
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}
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/*****************************************************************************/
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//
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// This is the main function for the TPG example.
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//
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/*****************************************************************************/
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int main(void)
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{
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// Print the current settings for the TPG core
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report_tpg_settings(XPAR_TPG_0_BASEADDR);
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return 0;
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}
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