bsp: r5: removed xmpu, slcr, xppu header files from cortexr5 folder
This patch removes xmpu, slcr, xppu header files from cortexr5 folder and standalone tcl has been modified to copy the header files from cortexa53/includes_ps. Makefile has been modified to include the header files in include folder while compilation Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel
Nava kishore Manne
parent
9b5cb9a6de
commit
6b6e985817
19 changed files with 3 additions and 22123 deletions
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@ -119,6 +119,7 @@ proc generate {os_handle} {
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}
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"psu_cortexr5" {
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set procdrv [hsi::get_sw_processor]
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set includedir "./src/cortexa53/includes_ps"
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set ccdir "./src/cortexr5/gcc"
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foreach entry [glob -nocomplain [file join $cortexr5srcdir *]] {
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file copy -force $entry "./src/"
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@ -126,7 +127,7 @@ proc generate {os_handle} {
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foreach entry [glob -nocomplain [file join $ccdir *]] {
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file copy -force $entry "./src/"
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}
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file copy -force $includedir "./src/"
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file delete -force "./src/gcc"
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file delete -force "./src/profile"
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if { $enable_sw_profile == "true" } {
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@ -59,6 +59,7 @@ INCLUDES=-I./. -I${INCLUDEDIR}
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OUTS = *.o
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INCLUDEFILES=*.h
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INCLUDEFILES+=includes_ps/*.h
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libs: $(LIBS)
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@ -1,382 +0,0 @@
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/* ### HEADER ### */
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#ifndef __XFPD_SLCR_H__
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#define __XFPD_SLCR_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* XfpdSlcr Base Address
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*/
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#define XFPD_SLCR_BASEADDR 0xFD610000UL
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/**
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* Register: XfpdSlcrWprot0
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*/
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#define XFPD_SLCR_WPROT0 ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
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#define XFPD_SLCR_WPROT0_RSTVAL 0x00000001UL
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#define XFPD_SLCR_WPROT0_ACT_SHIFT 0UL
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#define XFPD_SLCR_WPROT0_ACT_WIDTH 1UL
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#define XFPD_SLCR_WPROT0_ACT_MASK 0x00000001UL
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#define XFPD_SLCR_WPROT0_ACT_DEFVAL 0x1UL
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/**
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* Register: XfpdSlcrCtrl
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*/
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#define XFPD_SLCR_CTRL ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
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#define XFPD_SLCR_CTRL_RSTVAL 0x00000000UL
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#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
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#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
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#define XFPD_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
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#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrIsr
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*/
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#define XFPD_SLCR_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
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#define XFPD_SLCR_ISR_RSTVAL 0x00000000UL
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#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
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#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
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#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
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#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrImr
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*/
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#define XFPD_SLCR_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
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#define XFPD_SLCR_IMR_RSTVAL 0x00000001UL
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#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
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#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
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#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
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#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
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/**
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* Register: XfpdSlcrIer
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*/
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#define XFPD_SLCR_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
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#define XFPD_SLCR_IER_RSTVAL 0x00000000UL
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#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
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#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
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#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
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#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrIdr
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*/
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#define XFPD_SLCR_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
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#define XFPD_SLCR_IDR_RSTVAL 0x00000000UL
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#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
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#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
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#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
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#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrItr
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*/
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#define XFPD_SLCR_ITR ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
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#define XFPD_SLCR_ITR_RSTVAL 0x00000000UL
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#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
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#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
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#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
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#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrWdtClkSel
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*/
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#define XFPD_SLCR_WDT_CLK_SEL ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
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#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL 0x00000000UL
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#define XFPD_SLCR_WDT_CLK_SEL_SHIFT 0UL
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#define XFPD_SLCR_WDT_CLK_SEL_WIDTH 1UL
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#define XFPD_SLCR_WDT_CLK_SEL_MASK 0x00000001UL
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#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrIntFpd
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*/
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#define XFPD_SLCR_INT_FPD ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
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#define XFPD_SLCR_INT_FPD_RSTVAL 0x00000000UL
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#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT 0UL
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#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH 1UL
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#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK 0x00000001UL
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#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrGpu
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*/
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#define XFPD_SLCR_GPU ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
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#define XFPD_SLCR_GPU_RSTVAL 0x00000007UL
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#define XFPD_SLCR_GPU_ARCACHE_SHIFT 7UL
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#define XFPD_SLCR_GPU_ARCACHE_WIDTH 4UL
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#define XFPD_SLCR_GPU_ARCACHE_MASK 0x00000780UL
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#define XFPD_SLCR_GPU_ARCACHE_DEFVAL 0x0UL
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#define XFPD_SLCR_GPU_AWCACHE_SHIFT 3UL
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#define XFPD_SLCR_GPU_AWCACHE_WIDTH 4UL
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#define XFPD_SLCR_GPU_AWCACHE_MASK 0x00000078UL
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#define XFPD_SLCR_GPU_AWCACHE_DEFVAL 0x0UL
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#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT 2UL
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#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH 1UL
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#define XFPD_SLCR_GPU_PP1_IDLE_MASK 0x00000004UL
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#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL 0x1UL
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#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT 1UL
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#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH 1UL
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#define XFPD_SLCR_GPU_PP0_IDLE_MASK 0x00000002UL
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#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL 0x1UL
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#define XFPD_SLCR_GPU_IDLE_SHIFT 0UL
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#define XFPD_SLCR_GPU_IDLE_WIDTH 1UL
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#define XFPD_SLCR_GPU_IDLE_MASK 0x00000001UL
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#define XFPD_SLCR_GPU_IDLE_DEFVAL 0x1UL
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/**
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* Register: XfpdSlcrGdmaCfg
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*/
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#define XFPD_SLCR_GDMA_CFG ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
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#define XFPD_SLCR_GDMA_CFG_RSTVAL 0x00000048UL
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#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT 5UL
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#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH 2UL
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#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK 0x00000060UL
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#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL 0x2UL
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#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT 0UL
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#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH 5UL
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#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK 0x0000001fUL
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#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL 0x8UL
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/**
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* Register: XfpdSlcrGdma
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*/
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#define XFPD_SLCR_GDMA ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
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#define XFPD_SLCR_GDMA_RSTVAL 0x00003b3bUL
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#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT 12UL
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#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH 3UL
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#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK 0x00007000UL
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#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL 0x3UL
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#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT 11UL
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#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH 1UL
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#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK 0x00000800UL
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#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL 0x1UL
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#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT 8UL
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#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH 3UL
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#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK 0x00000700UL
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#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL 0x3UL
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#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT 4UL
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#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH 3UL
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#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK 0x00000070UL
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#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL 0x3UL
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#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT 3UL
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#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH 1UL
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#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK 0x00000008UL
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#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL 0x1UL
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#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT 0UL
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#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH 3UL
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#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK 0x00000007UL
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#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL 0x3UL
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/**
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* Register: XfpdSlcrAfiFs
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*/
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#define XFPD_SLCR_AFI_FS ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
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#define XFPD_SLCR_AFI_FS_RSTVAL 0x00000a00UL
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#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT 10UL
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#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH 2UL
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#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK 0x00000c00UL
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#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL 0x2UL
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#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT 8UL
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#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH 2UL
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#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK 0x00000300UL
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#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL 0x2UL
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/**
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* Register: XfpdSlcrErrAtbIsr
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*/
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#define XFPD_SLCR_ERR_ATB_ISR ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
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#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL 0x00000000UL
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#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT 2UL
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#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK 0x00000004UL
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#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL 0x0UL
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#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT 1UL
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#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK 0x00000002UL
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#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL 0x0UL
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#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT 0UL
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#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK 0x00000001UL
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#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrErrAtbImr
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*/
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#define XFPD_SLCR_ERR_ATB_IMR ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
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#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL 0x00000007UL
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#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT 2UL
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#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK 0x00000004UL
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#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL 0x1UL
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#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT 1UL
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#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK 0x00000002UL
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#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL 0x1UL
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#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT 0UL
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#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK 0x00000001UL
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#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL 0x1UL
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/**
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* Register: XfpdSlcrErrAtbIer
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*/
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#define XFPD_SLCR_ERR_ATB_IER ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
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#define XFPD_SLCR_ERR_ATB_IER_RSTVAL 0x00000000UL
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#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT 2UL
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#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK 0x00000004UL
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#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL 0x0UL
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#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT 1UL
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#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK 0x00000002UL
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#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL 0x0UL
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#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT 0UL
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#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK 0x00000001UL
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#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrErrAtbIdr
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*/
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#define XFPD_SLCR_ERR_ATB_IDR ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
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#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL 0x00000000UL
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#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT 2UL
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#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK 0x00000004UL
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#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL 0x0UL
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#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT 1UL
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#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK 0x00000002UL
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#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL 0x0UL
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#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT 0UL
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#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH 1UL
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#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK 0x00000001UL
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#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL 0x0UL
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/**
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* Register: XfpdSlcrAtbCmdstore
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*/
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#define XFPD_SLCR_ATB_CMDSTORE ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
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#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL 0x00000007UL
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#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT 2UL
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#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH 1UL
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#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK 0x00000004UL
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#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL 0x1UL
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||||
|
||||
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT 1UL
|
||||
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK 0x00000002UL
|
||||
#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT 0UL
|
||||
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrAtbRespEn
|
||||
*/
|
||||
#define XFPD_SLCR_ATB_RESP_EN ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
|
||||
#define XFPD_SLCR_ATB_RESP_EN_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT 2UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK 0x00000004UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL 0x0UL
|
||||
|
||||
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT 1UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK 0x00000002UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL 0x0UL
|
||||
|
||||
#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT 0UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrAtbResptype
|
||||
*/
|
||||
#define XFPD_SLCR_ATB_RESPTYPE ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL 0x00000007UL
|
||||
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT 2UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK 0x00000004UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT 1UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK 0x00000002UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT 0UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrAtbPrescale
|
||||
*/
|
||||
#define XFPD_SLCR_ATB_PRESCALE ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
|
||||
#define XFPD_SLCR_ATB_PRESCALE_RSTVAL 0x0000ffffUL
|
||||
|
||||
#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT 16UL
|
||||
#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH 1UL
|
||||
#define XFPD_SLCR_ATB_PRESCALE_EN_MASK 0x00010000UL
|
||||
#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL 0x0UL
|
||||
|
||||
#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT 0UL
|
||||
#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH 16UL
|
||||
#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK 0x0000ffffUL
|
||||
#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL 0xffffUL
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XFPD_SLCR_H__ */
|
||||
|
|
@ -1,277 +0,0 @@
|
|||
/* ### HEADER ### */
|
||||
|
||||
#ifndef __XFPD_SLCR_SECURE_H__
|
||||
#define __XFPD_SLCR_SECURE_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* XfpdSlcrSecure Base Address
|
||||
*/
|
||||
#define XFPD_SLCR_SECURE_BASEADDR 0xFD690000UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecCtrl
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_CTRL ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
|
||||
#define XFPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecIsr
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_ISR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
|
||||
#define XFPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecImr
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_IMR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
|
||||
#define XFPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
|
||||
|
||||
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecIer
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_IER ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
|
||||
#define XFPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecIdr
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_IDR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
|
||||
#define XFPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecItr
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_ITR ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
|
||||
#define XFPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecSata
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_SATA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
|
||||
#define XFPD_SLCR_SEC_SATA_RSTVAL 0x0000000eUL
|
||||
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT 3UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK 0x00000008UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT 2UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK 0x00000004UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT 1UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK 0x00000002UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecPcie
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_PCIE ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
|
||||
#define XFPD_SLCR_SEC_PCIE_RSTVAL 0x01ffffffUL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT 24UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK 0x01000000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT 23UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK 0x00800000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT 22UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK 0x00400000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT 21UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK 0x00200000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT 20UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK 0x00100000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT 19UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK 0x00080000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT 18UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK 0x00040000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT 17UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK 0x00020000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT 16UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK 0x00010000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT 15UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK 0x00008000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT 14UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK 0x00004000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT 13UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK 0x00002000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT 12UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK 0x00001000UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT 11UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK 0x00000800UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT 10UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK 0x00000400UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT 9UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK 0x00000200UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT 8UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK 0x00000100UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT 7UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK 0x00000080UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT 6UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK 0x00000040UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT 5UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK 0x00000020UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT 4UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK 0x00000010UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT 3UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK 0x00000008UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT 2UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK 0x00000004UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK 0x00000002UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL 0x1UL
|
||||
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecDpdma
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_DPDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
|
||||
#define XFPD_SLCR_SEC_DPDMA_RSTVAL 0x00000001UL
|
||||
|
||||
#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_DPDMA_TZ_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecGdma
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_GDMA ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
|
||||
#define XFPD_SLCR_SEC_GDMA_RSTVAL 0x000000ffUL
|
||||
|
||||
#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH 8UL
|
||||
#define XFPD_SLCR_SEC_GDMA_TZ_MASK 0x000000ffUL
|
||||
#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL 0xffUL
|
||||
|
||||
/**
|
||||
* Register: XfpdSlcrSecGic
|
||||
*/
|
||||
#define XFPD_SLCR_SEC_GIC ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
|
||||
#define XFPD_SLCR_SEC_GIC_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT 0UL
|
||||
#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH 1UL
|
||||
#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK 0x00000001UL
|
||||
#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL 0x0UL
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XFPD_SLCR_SECURE_H__ */
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -1,81 +0,0 @@
|
|||
/* ### HEADER ### */
|
||||
|
||||
#ifndef __XFPD_XMPU_SINK_H__
|
||||
#define __XFPD_XMPU_SINK_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* XfpdXmpuSink Base Address
|
||||
*/
|
||||
#define XFPD_XMPU_SINK_BASEADDR 0xFD4F0000UL
|
||||
|
||||
/**
|
||||
* Register: XfpdXmpuSinkErrSts
|
||||
*/
|
||||
#define XFPD_XMPU_SINK_ERR_STS ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
|
||||
#define XFPD_XMPU_SINK_ERR_STS_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT 31UL
|
||||
#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH 1UL
|
||||
#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
|
||||
#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
|
||||
|
||||
#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT 0UL
|
||||
#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH 12UL
|
||||
#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
|
||||
#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdXmpuSinkIsr
|
||||
*/
|
||||
#define XFPD_XMPU_SINK_ISR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
|
||||
#define XFPD_XMPU_SINK_ISR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT 0UL
|
||||
#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH 1UL
|
||||
#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
|
||||
#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdXmpuSinkImr
|
||||
*/
|
||||
#define XFPD_XMPU_SINK_IMR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
|
||||
#define XFPD_XMPU_SINK_IMR_RSTVAL 0x00000001UL
|
||||
|
||||
#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT 0UL
|
||||
#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH 1UL
|
||||
#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
|
||||
#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XfpdXmpuSinkIer
|
||||
*/
|
||||
#define XFPD_XMPU_SINK_IER ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
|
||||
#define XFPD_XMPU_SINK_IER_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT 0UL
|
||||
#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH 1UL
|
||||
#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
|
||||
#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XfpdXmpuSinkIdr
|
||||
*/
|
||||
#define XFPD_XMPU_SINK_IDR ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
|
||||
#define XFPD_XMPU_SINK_IDR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT 0UL
|
||||
#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH 1UL
|
||||
#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
|
||||
#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XFPD_XMPU_SINK_H__ */
|
||||
|
|
@ -1,174 +0,0 @@
|
|||
/* ### HEADER ### */
|
||||
|
||||
#ifndef __XIOU_SECURE_SLCR_H__
|
||||
#define __XIOU_SECURE_SLCR_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* XiouSecureSlcr Base Address
|
||||
*/
|
||||
#define XIOU_SECURE_SLCR_BASEADDR 0xFF240000UL
|
||||
|
||||
/**
|
||||
* Register: XiouSecSlcrAxiWprtcn
|
||||
*/
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL 0x00000000UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT 25UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK 0x0e000000UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT 22UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK 0x01c00000UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 19UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00380000UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT 16UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK 0x00070000UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 9UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000e00UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 6UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x000001c0UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000038UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT 0UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK 0x00000007UL
|
||||
#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XiouSecSlcrAxiRprtcn
|
||||
*/
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL 0x00000000UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT 22UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK 0x01c00000UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 19UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00380000UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT 16UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK 0x00070000UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 9UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000e00UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 6UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x000001c0UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000038UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
|
||||
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT 0UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH 3UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK 0x00000007UL
|
||||
#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XiouSecSlcrCtrl
|
||||
*/
|
||||
#define XIOU_SEC_SLCR_CTRL ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
|
||||
#define XIOU_SEC_SLCR_CTRL_RSTVAL 0x00000000UL
|
||||
|
||||
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT 0UL
|
||||
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH 1UL
|
||||
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK 0x00000001UL
|
||||
#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XiouSecSlcrIsr
|
||||
*/
|
||||
#define XIOU_SEC_SLCR_ISR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
|
||||
#define XIOU_SEC_SLCR_ISR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XiouSecSlcrImr
|
||||
*/
|
||||
#define XIOU_SEC_SLCR_IMR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
|
||||
#define XIOU_SEC_SLCR_IMR_RSTVAL 0x00000001UL
|
||||
|
||||
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XiouSecSlcrIer
|
||||
*/
|
||||
#define XIOU_SEC_SLCR_IER ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
|
||||
#define XIOU_SEC_SLCR_IER_RSTVAL 0x00000000UL
|
||||
|
||||
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XiouSecSlcrIdr
|
||||
*/
|
||||
#define XIOU_SEC_SLCR_IDR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
|
||||
#define XIOU_SEC_SLCR_IDR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XiouSecSlcrItr
|
||||
*/
|
||||
#define XIOU_SEC_SLCR_ITR ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
|
||||
#define XIOU_SEC_SLCR_ITR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XIOU_SECURE_SLCR_H__ */
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -1,141 +0,0 @@
|
|||
/* ### HEADER ### */
|
||||
|
||||
#ifndef __XLPD_SLCR_SECURE_H__
|
||||
#define __XLPD_SLCR_SECURE_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* XlpdSlcrSecure Base Address
|
||||
*/
|
||||
#define XLPD_SLCR_SECURE_BASEADDR 0xFF4B0000UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecCtrl
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_CTRL ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
|
||||
#define XLPD_SLCR_SEC_CTRL_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK 0x00000001UL
|
||||
#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecIsr
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_ISR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
|
||||
#define XLPD_SLCR_SEC_ISR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecImr
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_IMR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
|
||||
#define XLPD_SLCR_SEC_IMR_RSTVAL 0x00000001UL
|
||||
|
||||
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecIer
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_IER ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
|
||||
#define XLPD_SLCR_SEC_IER_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecIdr
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_IDR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
|
||||
#define XLPD_SLCR_SEC_IDR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecItr
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_ITR ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
|
||||
#define XLPD_SLCR_SEC_ITR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK 0x00000001UL
|
||||
#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecRpu
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_RPU ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
|
||||
#define XLPD_SLCR_SEC_RPU_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT 1UL
|
||||
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK 0x00000002UL
|
||||
#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK 0x00000001UL
|
||||
#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecAdma
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_ADMA ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
|
||||
#define XLPD_SLCR_SEC_ADMA_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH 8UL
|
||||
#define XLPD_SLCR_SEC_ADMA_TZ_MASK 0x000000ffUL
|
||||
#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecSafetyChk
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_SAFETY_CHK ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
|
||||
#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH 32UL
|
||||
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK 0xffffffffUL
|
||||
#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdSlcrSecUsb
|
||||
*/
|
||||
#define XLPD_SLCR_SEC_USB ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
|
||||
#define XLPD_SLCR_SEC_USB_RSTVAL 0x00000003UL
|
||||
|
||||
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT 1UL
|
||||
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK 0x00000002UL
|
||||
#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT 0UL
|
||||
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH 1UL
|
||||
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK 0x00000001UL
|
||||
#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL 0x1UL
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XLPD_SLCR_SECURE_H__ */
|
||||
|
|
@ -1,858 +0,0 @@
|
|||
/* ### HEADER ### */
|
||||
|
||||
#ifndef __XLPD_XPPU_H__
|
||||
#define __XLPD_XPPU_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* XlpdXppu Base Address
|
||||
*/
|
||||
#define XLPD_XPPU_BASEADDR 0xFF980000UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuCtrl
|
||||
*/
|
||||
#define XLPD_XPPU_CTRL ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
|
||||
#define XLPD_XPPU_CTRL_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT 2UL
|
||||
#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH 1UL
|
||||
#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK 0x00000004UL
|
||||
#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT 1UL
|
||||
#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH 1UL
|
||||
#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK 0x00000002UL
|
||||
#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_CTRL_EN_SHIFT 0UL
|
||||
#define XLPD_XPPU_CTRL_EN_WIDTH 1UL
|
||||
#define XLPD_XPPU_CTRL_EN_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_CTRL_EN_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuErrSts1
|
||||
*/
|
||||
#define XLPD_XPPU_ERR_STS1 ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
|
||||
#define XLPD_XPPU_ERR_STS1_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT 0UL
|
||||
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH 32UL
|
||||
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuErrSts2
|
||||
*/
|
||||
#define XLPD_XPPU_ERR_STS2 ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
|
||||
#define XLPD_XPPU_ERR_STS2_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT 0UL
|
||||
#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH 16UL
|
||||
#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK 0x0000ffffUL
|
||||
#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuPoison
|
||||
*/
|
||||
#define XLPD_XPPU_POISON ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
|
||||
#define XLPD_XPPU_POISON_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_POISON_BASE_SHIFT 0UL
|
||||
#define XLPD_XPPU_POISON_BASE_WIDTH 20UL
|
||||
#define XLPD_XPPU_POISON_BASE_MASK 0x000fffffUL
|
||||
#define XLPD_XPPU_POISON_BASE_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuIsr
|
||||
*/
|
||||
#define XLPD_XPPU_ISR ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
|
||||
#define XLPD_XPPU_ISR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_ISR_APER_PARITY_SHIFT 7UL
|
||||
#define XLPD_XPPU_ISR_APER_PARITY_WIDTH 1UL
|
||||
#define XLPD_XPPU_ISR_APER_PARITY_MASK 0x00000080UL
|
||||
#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_ISR_APER_TZ_SHIFT 6UL
|
||||
#define XLPD_XPPU_ISR_APER_TZ_WIDTH 1UL
|
||||
#define XLPD_XPPU_ISR_APER_TZ_MASK 0x00000040UL
|
||||
#define XLPD_XPPU_ISR_APER_TZ_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_ISR_APER_PERM_SHIFT 5UL
|
||||
#define XLPD_XPPU_ISR_APER_PERM_WIDTH 1UL
|
||||
#define XLPD_XPPU_ISR_APER_PERM_MASK 0x00000020UL
|
||||
#define XLPD_XPPU_ISR_APER_PERM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_ISR_MID_PARITY_SHIFT 3UL
|
||||
#define XLPD_XPPU_ISR_MID_PARITY_WIDTH 1UL
|
||||
#define XLPD_XPPU_ISR_MID_PARITY_MASK 0x00000008UL
|
||||
#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_ISR_MID_RO_SHIFT 2UL
|
||||
#define XLPD_XPPU_ISR_MID_RO_WIDTH 1UL
|
||||
#define XLPD_XPPU_ISR_MID_RO_MASK 0x00000004UL
|
||||
#define XLPD_XPPU_ISR_MID_RO_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_ISR_MID_MISS_SHIFT 1UL
|
||||
#define XLPD_XPPU_ISR_MID_MISS_WIDTH 1UL
|
||||
#define XLPD_XPPU_ISR_MID_MISS_MASK 0x00000002UL
|
||||
#define XLPD_XPPU_ISR_MID_MISS_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_ISR_INV_APB_SHIFT 0UL
|
||||
#define XLPD_XPPU_ISR_INV_APB_WIDTH 1UL
|
||||
#define XLPD_XPPU_ISR_INV_APB_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_ISR_INV_APB_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuImr
|
||||
*/
|
||||
#define XLPD_XPPU_IMR ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
|
||||
#define XLPD_XPPU_IMR_RSTVAL 0x000000efUL
|
||||
|
||||
#define XLPD_XPPU_IMR_APER_PARITY_SHIFT 7UL
|
||||
#define XLPD_XPPU_IMR_APER_PARITY_WIDTH 1UL
|
||||
#define XLPD_XPPU_IMR_APER_PARITY_MASK 0x00000080UL
|
||||
#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_IMR_APER_TZ_SHIFT 6UL
|
||||
#define XLPD_XPPU_IMR_APER_TZ_WIDTH 1UL
|
||||
#define XLPD_XPPU_IMR_APER_TZ_MASK 0x00000040UL
|
||||
#define XLPD_XPPU_IMR_APER_TZ_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_IMR_APER_PERM_SHIFT 5UL
|
||||
#define XLPD_XPPU_IMR_APER_PERM_WIDTH 1UL
|
||||
#define XLPD_XPPU_IMR_APER_PERM_MASK 0x00000020UL
|
||||
#define XLPD_XPPU_IMR_APER_PERM_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_IMR_MID_PARITY_SHIFT 3UL
|
||||
#define XLPD_XPPU_IMR_MID_PARITY_WIDTH 1UL
|
||||
#define XLPD_XPPU_IMR_MID_PARITY_MASK 0x00000008UL
|
||||
#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_IMR_MID_RO_SHIFT 2UL
|
||||
#define XLPD_XPPU_IMR_MID_RO_WIDTH 1UL
|
||||
#define XLPD_XPPU_IMR_MID_RO_MASK 0x00000004UL
|
||||
#define XLPD_XPPU_IMR_MID_RO_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_IMR_MID_MISS_SHIFT 1UL
|
||||
#define XLPD_XPPU_IMR_MID_MISS_WIDTH 1UL
|
||||
#define XLPD_XPPU_IMR_MID_MISS_MASK 0x00000002UL
|
||||
#define XLPD_XPPU_IMR_MID_MISS_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_IMR_INV_APB_SHIFT 0UL
|
||||
#define XLPD_XPPU_IMR_INV_APB_WIDTH 1UL
|
||||
#define XLPD_XPPU_IMR_INV_APB_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_IMR_INV_APB_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuIen
|
||||
*/
|
||||
#define XLPD_XPPU_IEN ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
|
||||
#define XLPD_XPPU_IEN_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_IEN_APER_PARITY_SHIFT 7UL
|
||||
#define XLPD_XPPU_IEN_APER_PARITY_WIDTH 1UL
|
||||
#define XLPD_XPPU_IEN_APER_PARITY_MASK 0x00000080UL
|
||||
#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IEN_APER_TZ_SHIFT 6UL
|
||||
#define XLPD_XPPU_IEN_APER_TZ_WIDTH 1UL
|
||||
#define XLPD_XPPU_IEN_APER_TZ_MASK 0x00000040UL
|
||||
#define XLPD_XPPU_IEN_APER_TZ_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IEN_APER_PERM_SHIFT 5UL
|
||||
#define XLPD_XPPU_IEN_APER_PERM_WIDTH 1UL
|
||||
#define XLPD_XPPU_IEN_APER_PERM_MASK 0x00000020UL
|
||||
#define XLPD_XPPU_IEN_APER_PERM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IEN_MID_PARITY_SHIFT 3UL
|
||||
#define XLPD_XPPU_IEN_MID_PARITY_WIDTH 1UL
|
||||
#define XLPD_XPPU_IEN_MID_PARITY_MASK 0x00000008UL
|
||||
#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IEN_MID_RO_SHIFT 2UL
|
||||
#define XLPD_XPPU_IEN_MID_RO_WIDTH 1UL
|
||||
#define XLPD_XPPU_IEN_MID_RO_MASK 0x00000004UL
|
||||
#define XLPD_XPPU_IEN_MID_RO_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IEN_MID_MISS_SHIFT 1UL
|
||||
#define XLPD_XPPU_IEN_MID_MISS_WIDTH 1UL
|
||||
#define XLPD_XPPU_IEN_MID_MISS_MASK 0x00000002UL
|
||||
#define XLPD_XPPU_IEN_MID_MISS_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IEN_INV_APB_SHIFT 0UL
|
||||
#define XLPD_XPPU_IEN_INV_APB_WIDTH 1UL
|
||||
#define XLPD_XPPU_IEN_INV_APB_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_IEN_INV_APB_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuIds
|
||||
*/
|
||||
#define XLPD_XPPU_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
|
||||
#define XLPD_XPPU_IDS_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_IDS_APER_PARITY_SHIFT 7UL
|
||||
#define XLPD_XPPU_IDS_APER_PARITY_WIDTH 1UL
|
||||
#define XLPD_XPPU_IDS_APER_PARITY_MASK 0x00000080UL
|
||||
#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IDS_APER_TZ_SHIFT 6UL
|
||||
#define XLPD_XPPU_IDS_APER_TZ_WIDTH 1UL
|
||||
#define XLPD_XPPU_IDS_APER_TZ_MASK 0x00000040UL
|
||||
#define XLPD_XPPU_IDS_APER_TZ_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IDS_APER_PERM_SHIFT 5UL
|
||||
#define XLPD_XPPU_IDS_APER_PERM_WIDTH 1UL
|
||||
#define XLPD_XPPU_IDS_APER_PERM_MASK 0x00000020UL
|
||||
#define XLPD_XPPU_IDS_APER_PERM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IDS_MID_PARITY_SHIFT 3UL
|
||||
#define XLPD_XPPU_IDS_MID_PARITY_WIDTH 1UL
|
||||
#define XLPD_XPPU_IDS_MID_PARITY_MASK 0x00000008UL
|
||||
#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IDS_MID_RO_SHIFT 2UL
|
||||
#define XLPD_XPPU_IDS_MID_RO_WIDTH 1UL
|
||||
#define XLPD_XPPU_IDS_MID_RO_MASK 0x00000004UL
|
||||
#define XLPD_XPPU_IDS_MID_RO_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IDS_MID_MISS_SHIFT 1UL
|
||||
#define XLPD_XPPU_IDS_MID_MISS_WIDTH 1UL
|
||||
#define XLPD_XPPU_IDS_MID_MISS_MASK 0x00000002UL
|
||||
#define XLPD_XPPU_IDS_MID_MISS_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_IDS_INV_APB_SHIFT 0UL
|
||||
#define XLPD_XPPU_IDS_INV_APB_WIDTH 1UL
|
||||
#define XLPD_XPPU_IDS_INV_APB_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_IDS_INV_APB_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMMstrIds
|
||||
*/
|
||||
#define XLPD_XPPU_M_MSTR_IDS ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
|
||||
#define XLPD_XPPU_M_MSTR_IDS_RSTVAL 0x00000014UL
|
||||
|
||||
#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT 0UL
|
||||
#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH 32UL
|
||||
#define XLPD_XPPU_M_MSTR_IDS_NO_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL 0x14UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMAperture32b
|
||||
*/
|
||||
#define XLPD_XPPU_M_APERTURE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
|
||||
#define XLPD_XPPU_M_APERTURE_32B_RSTVAL 0x00000080UL
|
||||
|
||||
#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT 0UL
|
||||
#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH 32UL
|
||||
#define XLPD_XPPU_M_APERTURE_32B_NO_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL 0x80UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMAperture64kb
|
||||
*/
|
||||
#define XLPD_XPPU_M_APERTURE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
|
||||
#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL 0x00000100UL
|
||||
|
||||
#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT 0UL
|
||||
#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH 32UL
|
||||
#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL 0x100UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMAperture1mb
|
||||
*/
|
||||
#define XLPD_XPPU_M_APERTURE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
|
||||
#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL 0x00000010UL
|
||||
|
||||
#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT 0UL
|
||||
#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH 32UL
|
||||
#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL 0x10UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMAperture512mb
|
||||
*/
|
||||
#define XLPD_XPPU_M_APERTURE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
|
||||
#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL 0x00000001UL
|
||||
|
||||
#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT 0UL
|
||||
#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH 32UL
|
||||
#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuBase32b
|
||||
*/
|
||||
#define XLPD_XPPU_BASE_32B ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
|
||||
#define XLPD_XPPU_BASE_32B_RSTVAL 0xff990000UL
|
||||
|
||||
#define XLPD_XPPU_BASE_32B_ADDR_SHIFT 0UL
|
||||
#define XLPD_XPPU_BASE_32B_ADDR_WIDTH 32UL
|
||||
#define XLPD_XPPU_BASE_32B_ADDR_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL 0xff990000UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuBase64kb
|
||||
*/
|
||||
#define XLPD_XPPU_BASE_64KB ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
|
||||
#define XLPD_XPPU_BASE_64KB_RSTVAL 0xff000000UL
|
||||
|
||||
#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT 0UL
|
||||
#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH 32UL
|
||||
#define XLPD_XPPU_BASE_64KB_ADDR_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL 0xff000000UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuBase1mb
|
||||
*/
|
||||
#define XLPD_XPPU_BASE_1MB ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
|
||||
#define XLPD_XPPU_BASE_1MB_RSTVAL 0xfe000000UL
|
||||
|
||||
#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT 0UL
|
||||
#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH 32UL
|
||||
#define XLPD_XPPU_BASE_1MB_ADDR_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL 0xfe000000UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuBase512mb
|
||||
*/
|
||||
#define XLPD_XPPU_BASE_512MB ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
|
||||
#define XLPD_XPPU_BASE_512MB_RSTVAL 0xc0000000UL
|
||||
|
||||
#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT 0UL
|
||||
#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH 32UL
|
||||
#define XLPD_XPPU_BASE_512MB_ADDR_MASK 0xffffffffUL
|
||||
#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL 0xc0000000UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId00
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID00 ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
|
||||
#define XLPD_XPPU_MSTR_ID00_RSTVAL 0x83ff0040UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL 0x3ffUL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID00_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID00_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL 0x40UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId01
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID01 ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
|
||||
#define XLPD_XPPU_MSTR_ID01_RSTVAL 0x03f00000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL 0x3f0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID01_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID01_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId02
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID02 ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
|
||||
#define XLPD_XPPU_MSTR_ID02_RSTVAL 0x83f00010UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL 0x3f0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID02_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID02_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL 0x10UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId03
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID03 ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
|
||||
#define XLPD_XPPU_MSTR_ID03_RSTVAL 0x83c00080UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL 0x3c0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID03_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID03_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL 0x80UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId04
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID04 ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
|
||||
#define XLPD_XPPU_MSTR_ID04_RSTVAL 0x83c30080UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL 0x3c3UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID04_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID04_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL 0x80UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId05
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID05 ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
|
||||
#define XLPD_XPPU_MSTR_ID05_RSTVAL 0x03c30081UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL 0x3c3UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID05_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID05_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL 0x81UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId06
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID06 ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
|
||||
#define XLPD_XPPU_MSTR_ID06_RSTVAL 0x03c30082UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL 0x3c3UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID06_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID06_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL 0x82UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId07
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID07 ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
|
||||
#define XLPD_XPPU_MSTR_ID07_RSTVAL 0x83c30083UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL 0x1UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL 0x3c3UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID07_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID07_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL 0x83UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId08
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID08 ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
|
||||
#define XLPD_XPPU_MSTR_ID08_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID08_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID08_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId09
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID09 ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
|
||||
#define XLPD_XPPU_MSTR_ID09_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID09_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID09_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId10
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID10 ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
|
||||
#define XLPD_XPPU_MSTR_ID10_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID10_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID10_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId11
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID11 ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
|
||||
#define XLPD_XPPU_MSTR_ID11_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID11_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID11_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId12
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID12 ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
|
||||
#define XLPD_XPPU_MSTR_ID12_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID12_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID12_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId13
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID13 ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
|
||||
#define XLPD_XPPU_MSTR_ID13_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID13_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID13_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId14
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID14 ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
|
||||
#define XLPD_XPPU_MSTR_ID14_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID14_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID14_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId15
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID15 ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
|
||||
#define XLPD_XPPU_MSTR_ID15_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID15_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID15_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId16
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID16 ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
|
||||
#define XLPD_XPPU_MSTR_ID16_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID16_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID16_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId17
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID17 ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
|
||||
#define XLPD_XPPU_MSTR_ID17_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID17_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID17_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId18
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID18 ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
|
||||
#define XLPD_XPPU_MSTR_ID18_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID18_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID18_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuMstrId19
|
||||
*/
|
||||
#define XLPD_XPPU_MSTR_ID19 ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
|
||||
#define XLPD_XPPU_MSTR_ID19_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT 31UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDP_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT 30UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH 1UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDR_MASK 0x40000000UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT 16UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDM_MASK 0x03ff0000UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_MSTR_ID19_MID_SHIFT 0UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MID_WIDTH 10UL
|
||||
#define XLPD_XPPU_MSTR_ID19_MID_MASK 0x000003ffUL
|
||||
#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL 0x0UL
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XLPD_XPPU_H__ */
|
||||
|
|
@ -1,81 +0,0 @@
|
|||
/* ### HEADER ### */
|
||||
|
||||
#ifndef __XLPD_XPPU_SINK_H__
|
||||
#define __XLPD_XPPU_SINK_H__
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* XlpdXppuSink Base Address
|
||||
*/
|
||||
#define XLPD_XPPU_SINK_BASEADDR 0xFF9C0000UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuSinkErrSts
|
||||
*/
|
||||
#define XLPD_XPPU_SINK_ERR_STS ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
|
||||
#define XLPD_XPPU_SINK_ERR_STS_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT 31UL
|
||||
#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH 1UL
|
||||
#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK 0x80000000UL
|
||||
#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL 0x0UL
|
||||
|
||||
#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT 0UL
|
||||
#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH 12UL
|
||||
#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK 0x00000fffUL
|
||||
#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuSinkIsr
|
||||
*/
|
||||
#define XLPD_XPPU_SINK_ISR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
|
||||
#define XLPD_XPPU_SINK_ISR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT 0UL
|
||||
#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH 1UL
|
||||
#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuSinkImr
|
||||
*/
|
||||
#define XLPD_XPPU_SINK_IMR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
|
||||
#define XLPD_XPPU_SINK_IMR_RSTVAL 0x00000001UL
|
||||
|
||||
#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT 0UL
|
||||
#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH 1UL
|
||||
#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL 0x1UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuSinkIer
|
||||
*/
|
||||
#define XLPD_XPPU_SINK_IER ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
|
||||
#define XLPD_XPPU_SINK_IER_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT 0UL
|
||||
#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH 1UL
|
||||
#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL 0x0UL
|
||||
|
||||
/**
|
||||
* Register: XlpdXppuSinkIdr
|
||||
*/
|
||||
#define XLPD_XPPU_SINK_IDR ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
|
||||
#define XLPD_XPPU_SINK_IDR_RSTVAL 0x00000000UL
|
||||
|
||||
#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT 0UL
|
||||
#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH 1UL
|
||||
#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK 0x00000001UL
|
||||
#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL 0x0UL
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __XLPD_XPPU_SINK_H__ */
|
||||
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