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dp: rx: Enable enhanced framing mode and training pattern 3 if DP v1.2.

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As per specification.
- Always enable enhanced framing mode.
- Declare training pattern 3 support if core is DP v1.2.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-08-04 01:38:22 -07:00 • committed by Nava kishore Manne
parent d972cf8c18
commit 754a82e98b
2 changed files with 10 additions and 0 deletions
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2
XilinxProcessorIPLib/drivers/dp/examples/xdp_rx_sst_dp159_example.c
View file

@ -533,6 +533,8 @@ static void Dprx_Dp159Config(XDp *InstancePtr, XIic *IicInstancePtr,
LaneCount = XDp_ReadReg(InstancePtr->Config.BaseAddr,
XDP_RX_OVER_LANE_COUNT_SET);
LaneCount &= XDP_RX_OVER_LANE_COUNT_SET_MASK;
LinkRate = XDp_ReadReg(InstancePtr->Config.BaseAddr,
XDP_RX_OVER_LINK_BW_SET);

8
XilinxProcessorIPLib/drivers/dp/src/xdp.c
View file

@ -1569,6 +1569,14 @@ void XDp_RxSetLaneCount(XDp *InstancePtr, u8 LaneCount)
InstancePtr->RxInstance.LinkConfig.LaneCount = LaneCount;
/* Use enhanced framing mode to meet the DisplayPort specification. */
LaneCount |= XDP_RX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK;
/* If the core is a DisplayPort v1.2 or newer core, always support
* training pattern 3 to meet the specification. */
if (InstancePtr->Config.DpProtocol) {
LaneCount |= XDP_RX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK;
}
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_CTRL_DPCD, 0x1);
XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_OVER_LANE_COUNT_SET,
LaneCount);