lwip: Add support for Zynq Ultrascale MPSoC
Add support to be used with newer version of GEM in Zynq Ultrascale MPSoC. Use TX Q1 and RX Q0; segregate Zynq specific TLB attributes and SLCR settings. Signed-off-by: Harini Katakam <harinik@xilinx.com> Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Harini Katakam
Nava kishore Manne
parent
baa1675449
commit
7f8e620772
4 changed files with 131 additions and 58 deletions
2
ThirdParty/sw_services/lwip141/src/ChangeLog
vendored
2
ThirdParty/sw_services/lwip141/src/ChangeLog
vendored
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@ -1,5 +1,7 @@
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Change Log for lwip
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=================================
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2015-07-19
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* Add support for Zynq Ultrascale MPSoC emacps
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2015-06-15
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* Update the lwip tcl for Hier IP(To support User parameters).
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2015-05-15
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@ -21,7 +21,7 @@ AXI_ETHERNET_SRCS = $(PORT)/netif/xaxiemacif_hw.c \
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AXI_ETHERNET_FIFO_SRCS = $(PORT)/netif/xaxiemacif_fifo.c
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AXI_ETHERNET_DMA_SRCS = $(PORT)/netif/xaxiemacif_dma.c
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PS7_ETHERNET_SRCS = $(PORT)/netif/xemacpsif_hw.c \
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PS_ETHERNET_SRCS = $(PORT)/netif/xemacpsif_hw.c \
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$(PORT)/netif/xemacpsif_physpeed.c \
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$(PORT)/netif/xemacpsif.c \
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$(PORT)/netif/xemacpsif_dma.c
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@ -52,8 +52,8 @@ ifeq ($(CONFIG_AXI_ETHERNET_DMA), y)
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ADAPTER_SRCS += $(AXI_ETHERNET_DMA_SRCS)
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endif
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ifeq ($(CONFIG_PS7_ETHERNET), y)
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ADAPTER_SRCS += $(PS7_ETHERNET_SRCS)
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ifeq ($(CONFIG_PS_ETHERNET), y)
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ADAPTER_SRCS += $(PS_ETHERNET_SRCS)
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endif
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ADAPTER_OBJS = $(ADAPTER_SRCS:%.c=%.o)
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@ -1,6 +1,6 @@
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/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -44,6 +44,9 @@
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#include "xparameters_ps.h"
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#include "xil_exception.h"
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#include "xil_mmu.h"
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#if defined (ARMR5)
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#include "xreg_cortexr5.h"
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#endif
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#ifdef CONFIG_XTRACE
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#include "xtrace.h"
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#endif
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@ -54,8 +57,8 @@
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#endif
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#define INTC_BASE_ADDR XPAR_SCUGIC_CPU_BASEADDR
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#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_DIST_BASEADDR
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#define INTC_BASE_ADDR XPAR_SCUGIC_0_CPU_BASEADDR
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#define INTC_DIST_BASE_ADDR XPAR_SCUGIC_0_DIST_BASEADDR
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/* Byte alignment of BDs */
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#define BD_ALIGNMENT (XEMACPS_DMABD_MINIMUM_ALIGNMENT*2)
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@ -173,7 +176,10 @@ void process_sent_bds(xemacpsif_s *xemacpsif, XEmacPs_BdRing *txring)
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tx_pbufs_storage[index + bdindex] = 0;
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curbdpntr = XEmacPs_BdRingNext(txring, curbdpntr);
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n_pbufs_freed--;
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#if defined (ARMR5)
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#else
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dsb();
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#endif
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}
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status = XEmacPs_BdRingFree(txring, n_bds, txbdset);
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@ -367,6 +373,7 @@ void emacps_recv_handler(void *arg)
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u32_t bdindex;
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u32_t regval;
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u32_t index = 0;
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u32_t gigeversion;
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xemac = (struct xemac_s *)(arg);
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xemacpsif = (xemacpsif_s *)(xemac->state);
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@ -375,6 +382,8 @@ void emacps_recv_handler(void *arg)
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#ifdef OS_IS_FREERTOS
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xInsideISR++;
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#endif
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gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
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if (xemacpsif->emacps.Config.BaseAddress != XPAR_XEMACPS_0_BASEADDR) {
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index = sizeof(s32_t) * XLWIP_CONFIG_N_RX_DESC;
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}
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@ -384,8 +393,9 @@ void emacps_recv_handler(void *arg)
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*/
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regval = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET);
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XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXSR_OFFSET, regval);
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resetrx_on_no_rxdata(xemacpsif);
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if (gigeversion <= 2) {
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resetrx_on_no_rxdata(xemacpsif);
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}
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while(1) {
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@ -462,6 +472,10 @@ XStatus init_dma(struct xemac_s *xemac)
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u32_t bdindex;
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volatile u32_t tempaddress;
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u32_t index = 0;
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u32_t gigeversion;
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XEmacPs_Bd *bdtxterminate;
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XEmacPs_Bd *bdrxterminate;
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u32_t *temp;
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xemacpsif_s *xemacpsif = (xemacpsif_s *)(xemac->state);
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struct xtopology_t *xtopologyp = &xtopology[xemac->topology_index];
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@ -469,6 +483,7 @@ XStatus init_dma(struct xemac_s *xemac)
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if (xemacpsif->emacps.Config.BaseAddress != XPAR_XEMACPS_0_BASEADDR) {
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index = sizeof(s32_t) * XLWIP_CONFIG_N_RX_DESC;
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}
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gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
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/*
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* The BDs need to be allocated in uncached memory. Hence the 1 MB
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* address range allocated for Bd_Space is made uncached
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@ -477,7 +492,11 @@ XStatus init_dma(struct xemac_s *xemac)
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* a reserved uncached area used only for BDs.
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*/
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if (bd_space_attr_set == 0) {
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Xil_SetTlbAttributes((s32_t)bd_space, 0xc02); // addr, attr
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#if defined (ARMR5)
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Xil_SetTlbAttributes((s32_t)bd_space, STRONG_ORDERD_SHARED | PRIV_RW_USER_RW); // addr, attr
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#else
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Xil_SetTlbAttributes((s32_t)bd_space, 0xc02); // addr, attr
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#endif
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bd_space_attr_set = 1;
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}
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@ -493,6 +512,14 @@ XStatus init_dma(struct xemac_s *xemac)
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tempaddress = (u32_t)&(bd_space[bd_space_index]);
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xemacpsif->tx_bdspace = (void *)tempaddress;
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bd_space_index += 0x10000;
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if (gigeversion > 2) {
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tempaddress = (u32_t)&(bd_space[bd_space_index]);
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bdrxterminate = (XEmacPs_Bd *)tempaddress;
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bd_space_index += 0x10000;
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tempaddress = (u32_t)&(bd_space[bd_space_index]);
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bdtxterminate = (XEmacPs_Bd *)tempaddress;
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bd_space_index += 0x10000;
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}
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LWIP_DEBUGF(NETIF_DEBUG, ("rx_bdspace: 0x%08x\r\n", xemacpsif->rx_bdspace));
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LWIP_DEBUGF(NETIF_DEBUG, ("tx_bdspace: 0x%08x\r\n", xemacpsif->tx_bdspace));
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@ -577,12 +604,47 @@ XStatus init_dma(struct xemac_s *xemac)
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return ERR_IF;
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}
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bdindex = XEMACPS_BD_TO_INDEX(rxringptr, rxbd);
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temp = (u32_t *)rxbd;
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*temp = 0;
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if (bdindex == (XLWIP_CONFIG_N_RX_DESC - 1)) {
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*temp = 0x00000002;
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}
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temp++;
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*temp = 0;
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Xil_DCacheInvalidateRange((u32_t)p->payload, (u32_t)XEMACPS_MAX_FRAME_SIZE);
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XEmacPs_BdSetAddressRx(rxbd, (u32_t)p->payload);
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bdindex = XEMACPS_BD_TO_INDEX(rxringptr, rxbd);
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rx_pbufs_storage[index + bdindex] = (s32_t)p;
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}
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XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);
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if (gigeversion > 2) {
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XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, 1, XEMACPS_SEND);
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}else {
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XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.TxBdRing.BaseBdAddr, 0, XEMACPS_SEND);
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}
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if (gigeversion > 2)
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{
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/*
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* This version of GEM supports priority queuing and the current
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* dirver is using tx priority queue 1 and normal rx queue for
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* packet transmit and receive. The below code ensure that the
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* other queue pointers are parked to known state for avoiding
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* the controller to malfunction by fetching the descriptors
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* from these queues.
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*/
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XEmacPs_BdClear(bdrxterminate);
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XEmacPs_BdSetAddressRx(bdrxterminate, (XEMACPS_RXBUF_NEW_MASK |
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XEMACPS_RXBUF_WRAP_MASK));
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XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_RXQ1BASE_OFFSET),
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(UINTPTR)bdrxterminate);
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XEmacPs_BdClear(bdtxterminate);
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XEmacPs_BdSetStatus(bdrxterminate, (XEMACPS_TXBUF_USED_MASK |
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XEMACPS_TXBUF_WRAP_MASK));
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XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_TXQBASE_OFFSET),
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(UINTPTR)bdrxterminate);
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}
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/*
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* Connect the device driver handler that will be called when an
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@ -618,19 +680,23 @@ void resetrx_on_no_rxdata(xemacpsif_s *xemacpsif)
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{
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u32_t regctrl;
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u32_t tempcntr;
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u32_t gigeversion;
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tempcntr = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET);
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if ((!tempcntr) && (!(xemacpsif->last_rx_frms_cntr))) {
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regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
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XEMACPS_NWCTRL_OFFSET);
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regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK);
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XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
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XEMACPS_NWCTRL_OFFSET, regctrl);
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regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET);
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regctrl |= (XEMACPS_NWCTRL_RXEN_MASK);
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XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl);
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gigeversion = ((Xil_In32(xemacpsif->emacps.Config.BaseAddress + 0xFC)) >> 16) & 0xFFF;
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if (gigeversion == 2) {
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tempcntr = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_RXCNT_OFFSET);
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if ((!tempcntr) && (!(xemacpsif->last_rx_frms_cntr))) {
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regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress,
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XEMACPS_NWCTRL_OFFSET);
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regctrl &= (~XEMACPS_NWCTRL_RXEN_MASK);
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XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress,
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XEMACPS_NWCTRL_OFFSET, regctrl);
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regctrl = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET);
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regctrl |= (XEMACPS_NWCTRL_RXEN_MASK);
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XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, regctrl);
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}
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xemacpsif->last_rx_frms_cntr = tempcntr;
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}
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xemacpsif->last_rx_frms_cntr = tempcntr;
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}
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void free_txrx_pbufs(xemacpsif_s *xemacpsif)
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@ -1,6 +1,6 @@
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/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@ -527,56 +527,61 @@ static void SetUpSLCRDivisors(s32_t mac_baseaddr, s32_t speed)
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u32_t SlcrDiv0;
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u32_t SlcrDiv1;
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u32_t SlcrTxClkCntrl;
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u32_t gigeversion;
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*(volatile u32_t *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
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gigeversion = ((Xil_In32(mac_baseaddr + 0xFC)) >> 16) & 0xFFF;
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if (gigeversion == 2) {
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*(volatile u32_t *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE;
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if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
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slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
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} else {
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slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
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}
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if (speed == 1000) {
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if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
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slcrBaseAddress = SLCR_GEM0_CLK_CTRL_ADDR;
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} else {
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slcrBaseAddress = SLCR_GEM1_CLK_CTRL_ADDR;
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}
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if (speed == 1000) {
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if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
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#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0
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SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
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SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1;
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#endif
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} else {
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} else {
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#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0
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SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
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SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1;
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#endif
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}
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} else if (speed == 100) {
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if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
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}
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} else if (speed == 100) {
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if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
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#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0
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SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
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SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1;
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#endif
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} else {
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} else {
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#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0
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SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
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#endif
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}
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} else {
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if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
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#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
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SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
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SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_100MBPS_DIV1;
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#endif
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}
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} else {
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#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
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SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
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if (mac_baseaddr == XPAR_XEMACPS_0_BASEADDR) {
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#ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0
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SlcrDiv0 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1;
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#endif
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} else {
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#ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0
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SlcrDiv0 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV0;
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SlcrDiv1 = XPAR_PS7_ETHERNET_1_ENET_SLCR_10MBPS_DIV1;
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#endif
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}
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}
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SlcrTxClkCntrl = *(volatile u32_t *)(slcrBaseAddress);
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SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
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SlcrTxClkCntrl |= (SlcrDiv1 << 20);
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SlcrTxClkCntrl |= (SlcrDiv0 << 8);
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*(volatile u32_t *)(slcrBaseAddress) = SlcrTxClkCntrl;
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*(volatile u32_t *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
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}
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SlcrTxClkCntrl = *(volatile u32_t *)(slcrBaseAddress);
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SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
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SlcrTxClkCntrl |= (SlcrDiv1 << 20);
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SlcrTxClkCntrl |= (SlcrDiv0 << 8);
|
||||
*(volatile u32_t *)(slcrBaseAddress) = SlcrTxClkCntrl;
|
||||
*(volatile u32_t *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE;
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue