dptx: More documentation for Doxygen.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
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5 changed files with 94 additions and 44 deletions
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@ -57,6 +57,7 @@
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*******************************************************************************/
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#ifndef XDPTX_EXAMPLE_COMMON_H_
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/* Prevent circular inclusions by using protection macros. */
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#define XDPTX_EXAMPLE_COMMON_H_
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/******************************* Include Files ********************************/
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@ -63,16 +63,14 @@
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/**************************** Constant Definitions ****************************/
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/**
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* The maximum voltage swing and pre-emphasis level is 3.
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*/
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/* The maximum voltage swing level is 3. */
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#define XDPTX_MAXIMUM_VS_LEVEL 3
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/* The maximum pre-emphasis level is 3. */
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#define XDPTX_MAXIMUM_PE_LEVEL 3
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/**
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* Error out if an AUX transactions exceeds these defer or timeout values.
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*/
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/* Error out if an AUX request yields a defer reply more than 50 times. */
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#define XDPTX_AUX_MAX_DEFER_COUNT 50
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/* Error out if an AUX request times out more than 50 times awaiting a reply. */
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#define XDPTX_AUX_MAX_TIMEOUT_COUNT 50
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/****************************** Type Definitions ******************************/
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@ -94,10 +92,17 @@ typedef enum {
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* This typedef describes an AUX transaction.
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*/
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typedef struct {
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u16 CmdCode;
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u8 NumBytes;
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u32 Address;
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u8 *Data;
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u16 CmdCode; /**< The AUX command code that specifies what
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type of AUX transaction is taking
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place. */
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u8 NumBytes; /**< The number of bytes that the AUX
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transaction will perform work on. */
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u32 Address; /**< The AUX or I2C start address that the AUX
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transaction will perform work on. */
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u8 *Data; /**< The data buffer that will store the data
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read from AUX read transactions or the
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data to write for AUX write
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transactions. */
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} XDptx_AuxTransaction;
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/**************************** Function Prototypes *****************************/
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@ -35,7 +35,8 @@
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* @file xdptx.h
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*
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* The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the
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* Xilinx DisplayPort soft IP core in source (TX) mode.
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* Xilinx DisplayPort soft IP core in source (TX) mode. This driver follows the
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* DisplayPort 1.2a specification.
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*
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* The Xilinx DisplayPort soft IP supports the following features:
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* - 1, 2, or 4 lanes.
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@ -171,8 +172,9 @@
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*
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*******************************************************************************/
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#ifndef XDPTX_H_ /* Prevent circular inclusions */
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#define XDPTX_H_ /* by using protection macros. */
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#ifndef XDPTX_H_
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/* Prevent circular inclusions by using protection macros. */
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#define XDPTX_H_
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/******************************* Include Files ********************************/
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@ -306,13 +308,16 @@ typedef enum {
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*/
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typedef struct {
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XDptx_VideoMode VideoMode; /**< Enumerated key. */
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u8 DmtId; /**< Standard DMT ID number. */
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u8 DmtId; /**< Standard Display Monitor Timing
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(DMT) ID number. */
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u16 HResolution; /**< Horizontal resolution. */
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u16 VResolution; /**< Vertical resolution. */
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u32 PixelClkKhz; /**< Pixel frequency (in KHz). */
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u8 Scan; /**< Interlaced/non-interlaced. */
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u8 HSyncPolarity; /**< Horizontal polarity. */
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u8 VSyncPolarity; /**< Vertical polarity. */
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u8 HSyncPolarity; /**< Horizontal synchronization
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polarity. */
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u8 VSyncPolarity; /**< Vertical synchronization
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polarity. */
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u32 HFrontPorch; /**< Horizontal front porch. */
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u32 HSyncPulseWidth; /**< Horizontal synchronization pulse
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width. */
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* video will be displayed.
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*/
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typedef struct {
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u32 HClkTotal;
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u32 VClkTotal;
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u32 HSyncPulseWidth;
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u32 VSyncPulseWidth;
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u32 HResolution;
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u32 VResolution;
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u32 HSyncPolarity;
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u32 VSyncPolarity;
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u32 HStart;
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u32 VStart;
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u32 VBackPorch;
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u32 VFrontPorch;
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u32 HBackPorch;
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u32 HFrontPorch;
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u32 Misc0;
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u32 Misc1;
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u32 MVid;
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u32 NVid;
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u32 TransferUnitSize;
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u32 UserPixelWidth;
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u32 DataPerLane;
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u32 AvgBytesPerTU;
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u32 InitWait;
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u32 Interlaced;
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u32 BitsPerColor;
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u32 HClkTotal; /**< Horizontal total time (in
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pixels). */
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u32 VClkTotal; /**< Vertical total time (in pixels). */
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u32 HSyncPulseWidth; /**< Horizontal synchronization time (in
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pixels). */
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u32 VSyncPulseWidth; /**< Vertical synchronization time (in
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lines */
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u32 HResolution; /**< Horizontal resolution (in
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pixels). */
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u32 VResolution; /**< Vertical resolution (in lines). */
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u32 HSyncPolarity; /**< Horizontal synchronization polarity
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(0=positive/1=negative). */
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u32 VSyncPolarity; /**< Vertical synchronization polarity
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(0=positive/1=negative). */
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u32 HStart; /**< Horizontal blank start (in
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pixels). */
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u32 VStart; /**< Vertical blank start (in lines). */
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u32 VBackPorch; /**< Vertical back porch (in lines). */
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u32 VFrontPorch; /**< Vertical front porch (in lines). */
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u32 HBackPorch; /**< Horizontal back porch (in
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pixels). */
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u32 HFrontPorch; /**< Horizontal front porch (in
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pixels). */
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u32 Misc0; /**< Miscellaneous stream attributes 0
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as specified by the DisplayPort
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1.2 specification. */
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u32 Misc1; /**< Miscellaneous stream attributes 1
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as specified by the DisplayPort
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1.2 specification. */
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u32 MVid; /**< M value for the video stream. This
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value is equal to the pixel
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clock in KHz. */
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u32 NVid; /**< N value for the video stream. */
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u32 TransferUnitSize; /**< Size of the transfer unit in the
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framing logic. */
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u32 UserPixelWidth; /**< The width of the user data input
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port. */
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u32 DataPerLane; /**< Used to translate the number of
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pixels per line to the native
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internal 16-bit datapath. */
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u32 AvgBytesPerTU; /**< Average number of bytes per
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transfer unit, scaled up by a
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factor of 1000. */
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u32 InitWait; /**< Number of initial wait cycles at
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the start of a new line by
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the framing logic. */
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u32 Interlaced; /**< Input stream is interlaced. */
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u32 BitsPerColor; /**< Number of bits per color
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component. */
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} XDptx_MainStreamAttributes;
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/******************************************************************************/
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*
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*******************************************************************************/
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#ifndef XDPTX_HW_H_ /* Prevent circular inclusions */
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#define XDPTX_HW_H_ /* by using protection macros. */
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#ifndef XDPTX_HW_H_
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/* Prevent circular inclusions by using protection macros. */
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#define XDPTX_HW_H_
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/***************************** Include Files **********************************/
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/**
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* This table contains the main stream attributes for various standard
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* resolutions.
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* resolutions. Each entry is of the format:
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* 1) XDPTX_VM_<HRES>x<VRES>_<REFRESH (HZ)>_P(_RB = Reduced Blanking)
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* 2) Display Monitor Timing (DMT) ID
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* 3) Horizontal resolution (pixels)
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* 4) Vertical resolution (lines)
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* 5) Pixel clock (KHz)
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* 6) Scan (0=non-interlaced|1=interlaced)
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* 7) Horizontal sync polarity (0=positive|1=negative)
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* 8) Vertical sync polarity (0=positive|1=negative)
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* 9) Horizontal front porch (pixels)
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* 10) Horizontal sync time (pixels)
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* 11) Horizontal back porch (pixels)
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* 12) Vertical front porch (lines)
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* 13) Vertical sync time (lines)
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* 14) Vertical back porch (lines)
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*/
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XDptx_DmtMode XDptx_DmtModes[] =
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{
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