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dptx: Using tabs instead of 8 spaces.

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2014-07-29 23:08:06 -07:00 • committed by Jagannadha Sutradharudu Teki
parent e3f77d9867
commit 8a5fe55ba2
15 changed files with 3999 additions and 3991 deletions
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238
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_audio_example.c
View file

@ -38,27 +38,27 @@
* to display video. In this example application, the sequence to enable audio
* is illustrated.
*
* @note This example requires an audio source such as an S/PDIF instance
* to be part of the hardware system. See XAPP1178 for reference.
* @note This example requires that the audio enable configuration
* parameter for DisplayPort be turned on when creating the
* hardware design.
* @note For this example to output audio, the user will need to
* implement initialization of the system (Dptx_PlatformInit),
* configuration of the audio source (Dptx_ConfigureAudioSrc) and,
* depending on the hardware system, will need to implement sending
* of an info frame (Dptx_AudioSendInfoFrame). See XAPP1178 and the
* IP documentation for reference.
* @note For this example to display output, after training is complete,
* the user will need to implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement. The functions Dptx_ConfigureAudioSrc and
* Dptx_AudioSendInfoFrame are present in this file and are also
* left for the user to implement.
* @note This example requires an audio source such as an S/PDIF instance
* to be part of the hardware system. See XAPP1178 for reference.
* @note This example requires that the audio enable configuration
* parameter for DisplayPort be turned on when creating the
* hardware design.
* @note For this example to output audio, the user will need to
* implement initialization of the system (Dptx_PlatformInit),
* configuration of the audio source (Dptx_ConfigureAudioSrc) and,
* depending on the hardware system, will need to implement sending
* of an info frame (Dptx_AudioSendInfoFrame). See XAPP1178 and the
* IP documentation for reference.
* @note For this example to display output, after training is complete,
* the user will need to implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement. The functions Dptx_ConfigureAudioSrc and
* Dptx_AudioSendInfoFrame are present in this file and are also
* left for the user to implement.
*
* <pre>
* MODIFICATION HISTORY:
@ -87,26 +87,26 @@ static void Dptx_AudioSendInfoFrame(XDptx *InstancePtr);
/**
* This function is the main function of the XDptx audio example.
*
* @param None.
* @param None.
*
* @return
* - XST_SUCCESS if the audio example finished successfully.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if the audio example finished successfully.
* - XST_FAILURE otherwise.
*
* @note None.
* @note None.
*
*******************************************************************************/
int main(void)
{
int Status;
u32 Status;
/* Run the XDptx audio example. */
Status = Dptx_AudioExample(&DptxInstance, DPTX_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Run the XDptx audio example. */
Status = Dptx_AudioExample(&DptxInstance, DPTX_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
@ -115,46 +115,46 @@ int main(void)
* function will set up audio, initiate link training, and a video stream will
* start being sent over the main link.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
*
* @return
* - XST_SUCCESS if the system was set up correctly and link
* training was successful.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if the system was set up correctly and link
* training was successful.
* - XST_FAILURE otherwise.
*
* @note None.
* @note None.
*
*******************************************************************************/
u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId)
{
u32 Status;
u32 Status;
/* Do platform initialization here. This is hardware system specific -
* it is up to the user to implement this function. */
Dptx_PlatformInit();
/*******************/
/* Do platform initialization here. This is hardware system specific -
* it is up to the user to implement this function. */
Dptx_PlatformInit();
/*******************/
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Initialize DisplayPort audio. */
Dptx_AudioInit(InstancePtr);
/* Initialize DisplayPort audio. */
Dptx_AudioInit(InstancePtr);
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
/* A sink monitor must be connected at this point. See the polling or
* interrupt examples for how to wait for a connection event. */
Status = Dptx_Run(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* A sink monitor must be connected at this point. See the polling or
* interrupt examples for how to wait for a connection event. */
Status = Dptx_Run(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
@ -163,102 +163,102 @@ u32 Dptx_AudioExample(XDptx *InstancePtr, u16 DeviceId)
* to implement configuration of the audio stream and, if needed, sending of
* the info frame.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note The user needs to implement the Dptx_ConfigureAudioSrc and
* the Dptx_AudioSendInfoFrame functions to fulfill audio
* initialization.
* @note The user needs to implement the Dptx_ConfigureAudioSrc and
* the Dptx_AudioSendInfoFrame functions to fulfill audio
* initialization.
*
*******************************************************************************/
static void Dptx_AudioInit(XDptx *InstancePtr)
{
u32 Fs;
u32 MAud;
u32 NAud;
u32 NumChs;
u32 Fs;
u32 MAud;
u32 NAud;
u32 NumChs;
/* Disable audio in the DisplayPort TX. This will also flush the buffers
* in the DisplayPort TX and set MUTE bit in VB-ID. */
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
0x0);
/* Disable audio in the DisplayPort TX. This will also flush the buffers
* in the DisplayPort TX and set MUTE bit in VB-ID. */
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
0x0);
/* Configure the audio source (the S/PDIF controller). It is up to the
* user to implement this function. */
Dptx_ConfigureAudioSrc(InstancePtr);
/*******************/
/* Configure the audio source (the S/PDIF controller). It is up to the
* user to implement this function. */
Dptx_ConfigureAudioSrc(InstancePtr);
/*******************/
/* Write audio info frame as per user requirements. This may be optional
* for some systems. 8 writes are required to register
* XDPTX_TX_AUDIO_INFO_DATA. It is up to the user to implement this
* function. */
Dptx_AudioSendInfoFrame(InstancePtr);
/*******************/
/* Write audio info frame as per user requirements. This may be optional
* for some systems. 8 writes are required to register
* XDPTX_TX_AUDIO_INFO_DATA. It is up to the user to implement this
* function. */
Dptx_AudioSendInfoFrame(InstancePtr);
/*******************/
Fs = 48; /* KHz (32 | 44.1 | 48) */
if (InstancePtr->LinkConfig.LinkRate == XDPTX_LINK_BW_SET_540GBPS) {
MAud = 512 * Fs;
}
else if (InstancePtr->LinkConfig.LinkRate ==
XDPTX_LINK_BW_SET_270GBPS) {
MAud = 512 * Fs;
}
else if (InstancePtr->LinkConfig.LinkRate ==
XDPTX_LINK_BW_SET_162GBPS) {
MAud = 512 * Fs;
}
Fs = 48; /* KHz (32 | 44.1 | 48) */
if (InstancePtr->LinkConfig.LinkRate == XDPTX_LINK_BW_SET_540GBPS) {
MAud = 512 * Fs;
}
else if (InstancePtr->LinkConfig.LinkRate ==
XDPTX_LINK_BW_SET_270GBPS) {
MAud = 512 * Fs;
}
else if (InstancePtr->LinkConfig.LinkRate ==
XDPTX_LINK_BW_SET_162GBPS) {
MAud = 512 * Fs;
}
/* Write the channel count. The value is (actual count - 1). */
NumChs = 2;
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CHANNELS,
NumChs - 1);
/* Write the channel count. The value is (actual count - 1). */
NumChs = 2;
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CHANNELS,
NumChs - 1);
/* NAud = 540000 | 270000 | 162000 */
NAud = 27 * InstancePtr->LinkConfig.LinkRate * 1000;
/* NAud = 540000 | 270000 | 162000 */
NAud = 27 * InstancePtr->LinkConfig.LinkRate * 1000;
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_MAUD, MAud);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_NAUD, NAud);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_MAUD, MAud);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_NAUD, NAud);
/* Enable audio in the DisplayPort TX. */
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
0x1);
/* Enable audio in the DisplayPort TX. */
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_AUDIO_CONTROL,
0x1);
}
/******************************************************************************/
/**
* This function needs to configure the audio source.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note The user needs to implement this. See XAPP1178 and the IP
* documentation for reference.
* @note The user needs to implement this. See XAPP1178 and the IP
* documentation for reference.
*
*******************************************************************************/
static void Dptx_ConfigureAudioSrc(XDptx *InstancePtr)
{
xil_printf("Dptx_ConfigureAudioSrc: User defined function here.\n");
xil_printf("Dptx_ConfigureAudioSrc: User defined function here.\n");
}
/******************************************************************************/
/**
* This function needs to send an info frame as per user requirements.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note The user needs to implement this. See XAPP1178 and the IP
* documentation for reference.
* @note This may be optional for some systems.
* @note A sequence of 8 writes are required to register
* XDPTX_TX_AUDIO_INFO_DATA. See XAPP1178 and the IP documentation
* for reference.
* @note The user needs to implement this. See XAPP1178 and the IP
* documentation for reference.
* @note This may be optional for some systems.
* @note A sequence of 8 writes are required to register
* XDPTX_TX_AUDIO_INFO_DATA. See XAPP1178 and the IP documentation
* for reference.
*
*******************************************************************************/
static void Dptx_AudioSendInfoFrame(XDptx *InstancePtr)
{
xil_printf("Dptx_AudioSendInfoFrame: User defined function here.\n");
xil_printf("Dptx_AudioSendInfoFrame: User defined function here.\n");
}

354
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c
View file

@ -38,13 +38,13 @@
* the DisplayPort TX core by training the main link at the maximum common
* capabilities between the TX and RX and checking the lane status.
*
* @note The DisplayPort TX core does not work alone - video/audio
* sources need to be set up in the system correctly, as well as
* setting up the output path (for example, configuring the
* hardware system with the DisplayPort TX core output to an FMC
* card with DisplayPort output capabilities. Some platform
* initialization will need to happen prior to calling XDptx driver
* functions. See XAPP1178 as a reference.
* @note The DisplayPort TX core does not work alone - video/audio
* sources need to be set up in the system correctly, as well as
* setting up the output path (for example, configuring the
* hardware system with the DisplayPort TX core output to an FMC
* card with DisplayPort output capabilities. Some platform
* initialization will need to happen prior to calling XDptx driver
* functions. See XAPP1178 as a reference.
*
* <pre>
* MODIFICATION HISTORY:
@ -73,32 +73,32 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr);
* This function will configure and establish a link with the receiver device,
* afterwards, a video stream will start to be sent over the main link.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param LaneCount is the number of lanes to use over the main link.
* @param LinkRate is the link rate to use over the main link.
* @param InstancePtr is a pointer to the XDptx instance.
* @param LaneCount is the number of lanes to use over the main link.
* @param LinkRate is the link rate to use over the main link.
*
* @return
* - XST_SUCCESS if main link was successfully established.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if main link was successfully established.
* - XST_FAILURE otherwise.
*
* @note None.
* @note None.
*
*******************************************************************************/
u32 Dptx_Run(XDptx *InstancePtr)
{
u32 Status;
u32 Status;
/* Configure and establish a link. */
Status = Dptx_StartLink(InstancePtr);
if (Status == XST_SUCCESS) {
/* Start the video stream. */
Dptx_StartVideoStream(InstancePtr);
} else {
xil_printf("<-- Failed to establish/train the link.\n");
return XST_FAILURE;
}
/* Configure and establish a link. */
Status = Dptx_StartLink(InstancePtr);
if (Status == XST_SUCCESS) {
/* Start the video stream. */
Dptx_StartVideoStream(InstancePtr);
} else {
xil_printf("<-- Failed to establish/train the link.\n");
return XST_FAILURE;
}
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
@ -107,221 +107,221 @@ u32 Dptx_Run(XDptx *InstancePtr)
* configuration parameters will be retrieved based on the configuration
* to the DisplayPort TX core instance with the specified device ID.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
*
* @return
* - XST_SUCCESS if the device configuration was found and obtained
* and if the main link was successfully established.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if the device configuration was found and obtained
* and if the main link was successfully established.
* - XST_FAILURE otherwise.
*
* @note None.
* @note None.
*
*******************************************************************************/
u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId)
{
XDptx_Config *ConfigPtr;
u32 Status;
XDptx_Config *ConfigPtr;
u32 Status;
/* Obtain the device configuration for the DisplayPort TX core. */
ConfigPtr = XDptx_LookupConfig(DeviceId);
if (!ConfigPtr) {
return XST_FAILURE;
}
/* Copy the device configuration into the InstancePtr's Config
* structure. */
XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
/* Obtain the device configuration for the DisplayPort TX core. */
ConfigPtr = XDptx_LookupConfig(DeviceId);
if (!ConfigPtr) {
return XST_FAILURE;
}
/* Copy the device configuration into the InstancePtr's Config
* structure. */
XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
/* Initialize the DisplayPort TX core. */
Status = XDptx_InitializeTx(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Initialize the DisplayPort TX core. */
Status = XDptx_InitializeTx(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function will configure and establish a link with the receiver device.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return
* - XST_SUCCESS the if main link was successfully established.
* - XST_FAILURE otherwise.
* - XST_SUCCESS the if main link was successfully established.
* - XST_FAILURE otherwise.
*
* @note None.
* @note None.
*
*******************************************************************************/
static u32 Dptx_StartLink(XDptx *InstancePtr)
{
u32 VsLevelTx;
u32 PeLevelTx;
u32 Status;
u8 LaneCount;
u8 LinkRate;
u32 VsLevelTx;
u32 PeLevelTx;
u32 Status;
u8 LaneCount;
u8 LinkRate;
/* Obtain the capabilities of the RX device by reading the monitor's
* DPCD. */
Status = XDptx_GetRxCapabilities(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Obtain the capabilities of the RX device by reading the monitor's
* DPCD. */
Status = XDptx_GetRxCapabilities(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#if (TRAIN_USE_MAX_LINK == 1)
LaneCount = InstancePtr->LinkConfig.MaxLaneCount;
LinkRate = InstancePtr->LinkConfig.MaxLinkRate;
LaneCount = InstancePtr->LinkConfig.MaxLaneCount;
LinkRate = InstancePtr->LinkConfig.MaxLinkRate;
#else
LaneCount = TRAIN_USE_LANE_COUNT;
LinkRate = TRAIN_USE_LINK_RATE;
LaneCount = TRAIN_USE_LANE_COUNT;
LinkRate = TRAIN_USE_LINK_RATE;
#endif
/* Check if the link is already trained */
Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount);
if (Status == XST_SUCCESS) {
xil_printf("-> Link is already trained on %d lanes.\n",
LaneCount);
if (XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_LINK_BW_SET) == LinkRate) {
xil_printf("-> Link needs to be re-trained %d Mbps.\n",
(270 * LinkRate));
}
else {
xil_printf("-> Link is already trained on %d Mbps.\n",
(270 * LinkRate));
return XST_SUCCESS;
}
}
else if (Status == XST_FAILURE) {
xil_printf("-> Needs training.\n");
}
else {
/* Either a connection does not exist or the supplied lane count
* is invalid. */
xil_printf("-> Error checking link status.\n");
return XST_FAILURE;
}
/* Check if the link is already trained */
Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount);
if (Status == XST_SUCCESS) {
xil_printf("-> Link is already trained on %d lanes.\n",
LaneCount);
if (XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_LINK_BW_SET) == LinkRate) {
xil_printf("-> Link needs to be re-trained %d Mbps.\n",
(270 * LinkRate));
}
else {
xil_printf("-> Link is already trained at %d Mbps.\n",
(270 * LinkRate));
return XST_SUCCESS;
}
}
else if (Status == XST_FAILURE) {
xil_printf("-> Needs training.\n");
}
else {
/* Either a connection does not exist or the supplied lane count
* is invalid. */
xil_printf("-> Error checking link status.\n");
return XST_FAILURE;
}
XDptx_SetEnhancedFrameMode(InstancePtr, 1);
XDptx_SetDownspread(InstancePtr, 0);
XDptx_SetEnhancedFrameMode(InstancePtr, 1);
XDptx_SetDownspread(InstancePtr, 0);
#if (TRAIN_USE_MAX_LINK == 1)
/* Configure the main link based on the maximum common capabilities of
* the DisplayPort TX core and the receiver device. */
Status = XDptx_CfgMainLinkMax(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Configure the main link based on the maximum common capabilities of
* the DisplayPort TX core and the receiver device. */
Status = XDptx_CfgMainLinkMax(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#else
XDptx_SetLinkRate(InstancePtr, LinkRate);
XDptx_SetLaneCount(InstancePtr, LaneCount);
XDptx_SetLinkRate(InstancePtr, LinkRate);
XDptx_SetLaneCount(InstancePtr, LaneCount);
#endif
/* Train the link. */
xil_printf("******************************************\n");
Status = XDptx_EstablishLink(InstancePtr);
if (Status != XST_SUCCESS) {
xil_printf("!!! Training failed !!!\n");
xil_printf("******************************************\n");
return XST_FAILURE;
}
/* Train the link. */
xil_printf("******************************************\n");
Status = XDptx_EstablishLink(InstancePtr);
if (Status != XST_SUCCESS) {
xil_printf("!!! Training failed !!!\n");
xil_printf("******************************************\n");
return XST_FAILURE;
}
VsLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_PHY_VOLTAGE_DIFF_LANE_0);
PeLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_PHY_POSTCURSOR_LANE_0);
xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n",
InstancePtr->LinkConfig.LinkRate,
InstancePtr->LinkConfig.LaneCount);
xil_printf("VS:%d (TX:%d) PE:%d (TX:%d)\n",
InstancePtr->LinkConfig.VsLevel, VsLevelTx,
InstancePtr->LinkConfig.PeLevel, PeLevelTx);
xil_printf("******************************************\n");
VsLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_PHY_VOLTAGE_DIFF_LANE_0);
PeLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_PHY_POSTCURSOR_LANE_0);
xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n",
InstancePtr->LinkConfig.LinkRate,
InstancePtr->LinkConfig.LaneCount);
xil_printf("VS:%d (TX:%d) PE:%d (TX:%d)\n",
InstancePtr->LinkConfig.VsLevel, VsLevelTx,
InstancePtr->LinkConfig.PeLevel, PeLevelTx);
xil_printf("******************************************\n");
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function will start sending a video stream over the main link. The
* settings to be used are as follows:
* - 8 bits per color.
* - Video timing and screen resolution used:
* - The connected monitor's preferred timing is used to determine the
* video resolution (and associated timings) for the stream.
* - 8 bits per color.
* - Video timing and screen resolution used:
* - The connected monitor's preferred timing is used to determine the
* video resolution (and associated timings) for the stream.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note Dptx_ConfigureStreamSrc is intentionally left for the user to
* implement since configuration of the stream source is
* application-specific.
* @note The Extended Display Identification Data (EDID) is read in order
* to obtain the video resolution and timings. If this read fails,
* a resolution of 640x480 is used at a refresh rate of 60Hz.
* @note Dptx_ConfigureStreamSrc is intentionally left for the user to
* implement since configuration of the stream source is
* application-specific.
* @note The Extended Display Identification Data (EDID) is read in order
* to obtain the video resolution and timings. If this read fails,
* a resolution of 640x480 is used at a refresh rate of 60Hz.
*
*******************************************************************************/
static void Dptx_StartVideoStream(XDptx *InstancePtr)
{
u32 Status;
u8 AuxData[1];
u32 Status;
u8 AuxData[1];
/* Set the bits per color. If not set, the default is 6. */
XDptx_CfgMsaSetBpc(InstancePtr, 8);
/* Set the bits per color. If not set, the default is 6. */
XDptx_CfgMsaSetBpc(InstancePtr, 8);
/* Choose a method for selecting the video mode. There are 3 ways to do this:
* 1) Use the preferred timing from the monitor's EDID:
* XDptx_GetEdid(InstancePtr);
* XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
* XDptx_GetEdid(InstancePtr);
* XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
*
* 2) Use a standard video timing mode (see mode_table.h):
* XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_VM_640x480_60_P);
* XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_VM_640x480_60_P);
*
* 3) Use a custom configuration for the main stream attributes (MSA):
* XDptx_MainStreamAttributes MsaConfigCustom;
* MsaConfigCustom.MVid = 108000;
* MsaConfigCustom.HSyncPolarity = 0;
* MsaConfigCustom.VSyncPolarity = 0;
* MsaConfigCustom.HSyncPulseWidth = 112;
* MsaConfigCustom.VSyncPulseWidth = 3;
* MsaConfigCustom.HResolution = 1280;
* MsaConfigCustom.VResolution = 1024;
* MsaConfigCustom.VBackPorch = 38;
* MsaConfigCustom.VFrontPorch = 1;
* MsaConfigCustom.HBackPorch = 248;
* MsaConfigCustom.HFrontPorch = 48;
* XDptx_CfgMsaUseCustom(InstancePtr, &MsaConfigCustom, 1);
* XDptx_MainStreamAttributes MsaConfigCustom;
* MsaConfigCustom.MVid = 108000;
* MsaConfigCustom.HSyncPolarity = 0;
* MsaConfigCustom.VSyncPolarity = 0;
* MsaConfigCustom.HSyncPulseWidth = 112;
* MsaConfigCustom.VSyncPulseWidth = 3;
* MsaConfigCustom.HResolution = 1280;
* MsaConfigCustom.VResolution = 1024;
* MsaConfigCustom.VBackPorch = 38;
* MsaConfigCustom.VFrontPorch = 1;
* MsaConfigCustom.HBackPorch = 248;
* MsaConfigCustom.HFrontPorch = 48;
* XDptx_CfgMsaUseCustom(InstancePtr, &MsaConfigCustom, 1);
*/
Status = XDptx_GetEdid(InstancePtr);
if (Status == XST_SUCCESS) {
XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
}
else {
XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
XDPTX_VM_640x480_60_P);
}
Status = XDptx_GetEdid(InstancePtr);
if (Status == XST_SUCCESS) {
XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
}
else {
XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
XDPTX_VM_640x480_60_P);
}
/* Disable MST for this example. */
AuxData[0] = 0;
XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 1, AuxData);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, 0x0);
/* Disable MST for this example. */
AuxData[0] = 0;
XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 0x1, AuxData);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, 0x0);
/* Disable main stream to force sending of IDLE patterns. */
XDptx_DisableMainLink(InstancePtr);
/* Disable main stream to force sending of IDLE patterns. */
XDptx_DisableMainLink(InstancePtr);
/* Reset the transmitter. */
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET,
XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
/* Reset the transmitter. */
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET,
XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
/* Configure video stream source or generator here. This function needs
* to be implemented in order for video to be displayed and is hardware
* system specific. It is up to the user to implement this function. */
Dptx_ConfigureStreamSrc(InstancePtr);
/*********************************/
/* Configure video stream source or generator here. This function needs
* to be implemented in order for video to be displayed and is hardware
* system specific. It is up to the user to implement this function. */
Dptx_ConfigureStreamSrc(InstancePtr);
/*********************************/
XDptx_EnableMainLink(InstancePtr);
XDptx_EnableMainLink(InstancePtr);
}

16
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h
View file

@ -38,13 +38,13 @@
* the DisplayPort TX core by training the main link at the maximum common
* capabilities between the TX and RX and checking the lane status.
*
* @note The DisplayPort TX core does not work alone - video/audio
* sources need to be set up in the system correctly, as well as
* setting up the output path (for example, configuring the
* hardware system with the DisplayPort TX core output to an FMC
* card with DisplayPort output capabilities. Some platform
* initialization will need to happen prior to calling XDptx driver
* functions. See XAPP1178 as a reference.
* @note The DisplayPort TX core does not work alone - video/audio
* sources need to be set up in the system correctly, as well as
* setting up the output path (for example, configuring the
* hardware system with the DisplayPort TX core output to an FMC
* card with DisplayPort output capabilities. Some platform
* initialization will need to happen prior to calling XDptx driver
* functions. See XAPP1178 as a reference.
*
* <pre>
* MODIFICATION HISTORY:
@ -70,7 +70,7 @@
/**************************** Constant Definitions ****************************/
/* The unique device ID of the DisplayPort TX core instance to be used with the
* examples.*/
* examples. */
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
/* If set to 1, the link training process will continue training despite failing

302
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c
View file

@ -38,17 +38,17 @@
* Plug-Detect (HPD - DisplayPort cable is plugged/unplugged or the monitor is
* turned on/off), the main link will be trained.
*
* @note This example requires an interrupt controller connected to the
* processor and the DisplayPort TX core in the system.
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
* @note This example requires an interrupt controller connected to the
* processor and the DisplayPort TX core in the system.
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
*
* <pre>
* MODIFICATION HISTORY:
@ -76,11 +76,11 @@
/* The following constants map to the XPAR parameters created in the
* xparameters.h file. */
#ifdef XPAR_INTC_0_DEVICE_ID
#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#else
#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#endif /* XPAR_INTC_0_DEVICE_ID */
/****************************** Type Definitions ******************************/
@ -88,27 +88,27 @@
/* Depending on whether the system is a MicroBlaze or ARM/Zynq SoC system,
* different drivers and associated types will be used. */
#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC XIntc
#define INTC_HANDLER XIntc_InterruptHandler
#define INTC XIntc
#define INTC_HANDLER XIntc_InterruptHandler
#else
#define INTC XScuGic
#define INTC_HANDLER XScuGic_InterruptHandler
#define INTC XScuGic
#define INTC_HANDLER XScuGic_InterruptHandler
#endif /* XPAR_INTC_0_DEVICE_ID */
/**************************** Function Prototypes *****************************/
u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler);
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler);
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler);
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler);
static void Dptx_HpdEventHandler(void *InstancePtr);
static void Dptx_HpdPulseHandler(void *InstancePtr);
/**************************** Variable Definitions ****************************/
INTC IntcInstance; /* The interrupt controller instance. */
INTC IntcInstance; /* The interrupt controller instance. */
/**************************** Function Definitions ****************************/
@ -120,25 +120,25 @@ INTC IntcInstance; /* The interrupt controller instance. */
* training will commence (if needed) and a video stream will start being sent
* over the main link.
*
* @param None.
* @param None.
*
* @return
* - XST_FAILURE if the interrupt example was unsuccessful - system
* setup failed.
* - XST_FAILURE if the interrupt example was unsuccessful - system
* setup failed.
*
* @note Unless setup failed, main will never return since
* DptxIntrExample is blocking (it is waiting on interrupts for
* Hot-Plug-Detect (HPD) events.
* @note Unless setup failed, main will never return since
* DptxIntrExample is blocking (it is waiting on interrupts for
* Hot-Plug-Detect (HPD) events.
*
*******************************************************************************/
int main(void)
{
/* Run the XDptx interrupt example. */
Dptx_IntrExample(&DptxInstance, DPTX_DEVICE_ID,
&IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID,
&Dptx_HpdEventHandler, &Dptx_HpdPulseHandler);
/* Run the XDptx interrupt example. */
Dptx_IntrExample(&DptxInstance, DPTX_DEVICE_ID,
&IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID,
&Dptx_HpdEventHandler, &Dptx_HpdPulseHandler);
return XST_FAILURE;
return XST_FAILURE;
}
/******************************************************************************/
@ -147,59 +147,59 @@ int main(void)
* function will set up the system with interrupts and set up the Hot-Plug-Event
* (HPD) handlers.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param IntcPtr is a pointer to the interrupt instance.
* @param IntrId is the unique device ID of the interrupt controller.
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
* the interrupt controller.
* @param HpdEventHandler is a pointer to the handler called when an HPD
* event occurs.
* @param HpdPulseHandler is a pointer to the handler called when an HPD
* pulse occurs.
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param IntcPtr is a pointer to the interrupt instance.
* @param IntrId is the unique device ID of the interrupt controller.
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
* the interrupt controller.
* @param HpdEventHandler is a pointer to the handler called when an HPD
* event occurs.
* @param HpdPulseHandler is a pointer to the handler called when an HPD
* pulse occurs.
*
* @return
* - XST_FAILURE if the system setup failed.
* - XST_SUCCESS should never return since this function, if setup
* was successful, is blocking.
* - XST_FAILURE if the system setup failed.
* - XST_SUCCESS should never return since this function, if setup
* was successful, is blocking.
*
* @note If system setup was successful, this function is blocking in
* order to illustrate interrupt handling taking place for HPD
* events.
* @note If system setup was successful, this function is blocking in
* order to illustrate interrupt handling taking place for HPD
* events.
*
*******************************************************************************/
u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler)
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler)
{
u32 Status;
u32 Status;
/* Do platform initialization here. This is hardware system specific -
* it is up to the user to implement this function. */
Dptx_PlatformInit();
/******************/
/* Do platform initialization here. This is hardware system specific -
* it is up to the user to implement this function. */
Dptx_PlatformInit();
/******************/
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
/* Setup interrupt handling in the system. */
Status = Dptx_SetupInterruptHandler(InstancePtr, IntcPtr, IntrId,
DpIntrId, HpdEventHandler, HpdPulseHandler);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Setup interrupt handling in the system. */
Status = Dptx_SetupInterruptHandler(InstancePtr, IntcPtr, IntrId,
DpIntrId, HpdEventHandler, HpdPulseHandler);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Do not return in order to allow interrupt handling to run. HPD events
* (connect, disconnect, and pulse) will be detected and handled. */
while (1);
/* Do not return in order to allow interrupt handling to run. HPD events
* (connect, disconnect, and pulse) will be detected and handled. */
while (1);
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
@ -210,88 +210,88 @@ u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
* to the processor. The user should modify this function to fit the
* application.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param IntcPtr is a pointer to the interrupt instance.
* @param IntrId is the unique device ID of the interrupt controller.
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
* the interrupt controller.
* @param HpdEventHandler is a pointer to the handler called when an HPD
* event occurs.
* @param HpdPulseHandler is a pointer to the handler called when an HPD
* pulse occurs.
* @param InstancePtr is a pointer to the XDptx instance.
* @param IntcPtr is a pointer to the interrupt instance.
* @param IntrId is the unique device ID of the interrupt controller.
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
* the interrupt controller.
* @param HpdEventHandler is a pointer to the handler called when an HPD
* event occurs.
* @param HpdPulseHandler is a pointer to the handler called when an HPD
* pulse occurs.
*
* @return
* - XST_SUCCESS if the interrupt system was successfully set up.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if the interrupt system was successfully set up.
* - XST_FAILURE otherwise.
*
* @note An interrupt controller must be present in the system, connected
* to the processor and the DisplayPort TX core.
* @note An interrupt controller must be present in the system, connected
* to the processor and the DisplayPort TX core.
*
*******************************************************************************/
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler)
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler)
{
u32 Status;
u32 Status;
/* Set the HPD interrupt handlers. */
XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr);
XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr);
/* Set the HPD interrupt handlers. */
XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr);
XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr);
/* Initialize interrupt controller driver. */
/* Initialize interrupt controller driver. */
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Initialize(IntcPtr, IntrId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = XIntc_Initialize(IntcPtr, IntrId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#else
XScuGic_Config *IntcConfig;
XScuGic_Config *IntcConfig;
IntcConfig = XScuGic_LookupConfig(IntrId);
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, DpIntrId, 0xA0, 0x1);
IntcConfig = XScuGic_LookupConfig(IntrId);
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(IntcPtr, DpIntrId, 0xA0, 0x1);
#endif /* XPAR_INTC_0_DEVICE_ID */
/* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device. */
/* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device. */
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Connect(IntcPtr, DpIntrId,
(XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
Status = XIntc_Connect(IntcPtr, DpIntrId,
(XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#else
Status = XScuGic_Connect(IntcPtr, DpIntrId,
(Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
Status = XScuGic_Connect(IntcPtr, DpIntrId,
(Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#endif /* XPAR_INTC_0_DEVICE_ID */
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Start the interrupt controller. */
/* Start the interrupt controller. */
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Start(IntcPtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIntc_Enable(IntcPtr, DpIntrId);
Status = XIntc_Start(IntcPtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIntc_Enable(IntcPtr, DpIntrId);
#else
XScuGic_Enable(IntcPtr, DpIntrId);
XScuGic_Enable(IntcPtr, DpIntrId);
#endif /* XPAR_INTC_0_DEVICE_ID */
/* Initialize the exception table. */
Xil_ExceptionInit();
/* Initialize the exception table. */
Xil_ExceptionInit();
/* Register the interrupt controller handler with the exception table. */
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER, IntcPtr);
/* Register the interrupt controller handler with the exception table. */
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)INTC_HANDLER, IntcPtr);
/* Enable exceptions. */
Xil_ExceptionEnable();
/* Enable exceptions. */
Xil_ExceptionEnable();
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
@ -301,26 +301,26 @@ static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
* core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
* occurred.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note Use the XDptx_SetHpdEventHandler driver function to set this
* function as the handler for HPD pulses.
* @note Use the XDptx_SetHpdEventHandler driver function to set this
* function as the handler for HPD pulses.
*
*******************************************************************************/
static void Dptx_HpdEventHandler(void *InstancePtr)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
if (XDptx_IsConnected(XDptx_InstancePtr)) {
xil_printf("+===> HPD connection event detected.\n");
if (XDptx_IsConnected(XDptx_InstancePtr)) {
xil_printf("+===> HPD connection event detected.\n");
Dptx_Run(XDptx_InstancePtr);
}
else {
xil_printf("+===> HPD disconnection event detected.\n\n");
}
Dptx_Run(XDptx_InstancePtr);
}
else {
xil_printf("+===> HPD disconnection event detected.\n\n");
}
}
/******************************************************************************/
@ -330,19 +330,19 @@ static void Dptx_HpdEventHandler(void *InstancePtr)
* of the core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
* occurred.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note Use the XDptx_SetHpdPulseHandler driver function to set this
* function as the handler for HPD pulses.
* @note Use the XDptx_SetHpdPulseHandler driver function to set this
* function as the handler for HPD pulses.
*
*******************************************************************************/
static void Dptx_HpdPulseHandler(void *InstancePtr)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
xil_printf("===> HPD pulse detected.\n");
xil_printf("===> HPD pulse detected.\n");
Dptx_Run(XDptx_InstancePtr);
Dptx_Run(XDptx_InstancePtr);
}

164
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c
View file

@ -38,15 +38,15 @@
* polling detects a Hot-Plug-Detect event (HPD - DisplayPort cable is plugged/
* unplugged or the monitor is turned on/off), the main link will be trained.
*
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
*
* <pre>
* MODIFICATION HISTORY:
@ -73,23 +73,23 @@ static void Dptx_HpdPoll(XDptx *InstancePtr);
/**
* This function is the main function of the XDptx polling example.
*
* @param None.
* @param None.
*
* @return
* - XST_FAILURE if the polling example was unsuccessful - system
* setup failed.
* - XST_FAILURE if the polling example was unsuccessful - system
* setup failed.
*
* @note Unless setup failed, main will never return since
* Dptx_PollExample is blocking (it is continuously polling for
* Hot-Plug-Detect (HPD) events.
* @note Unless setup failed, main will never return since
* Dptx_PollExample is blocking (it is continuously polling for
* Hot-Plug-Detect (HPD) events.
*
*******************************************************************************/
int main(void)
{
/* Run the XDptx polling example. */
Dptx_PollExample(&DptxInstance, DPTX_DEVICE_ID);
/* Run the XDptx polling example. */
Dptx_PollExample(&DptxInstance, DPTX_DEVICE_ID);
return XST_FAILURE;
return XST_FAILURE;
}
/******************************************************************************/
@ -100,42 +100,42 @@ int main(void)
* a connection event or a pulse is detected, link training will commence (if
* needed) and a video stream will start being sent over the main link.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
*
* @return
* - XST_FAILURE if the system setup failed.
* - XST_SUCCESS should never return since this function, if setup
* was successful, is blocking.
* - XST_FAILURE if the system setup failed.
* - XST_SUCCESS should never return since this function, if setup
* was successful, is blocking.
*
* @note If system setup was successful, this function is blocking in
* order to illustrate polling taking place for HPD events.
* @note If system setup was successful, this function is blocking in
* order to illustrate polling taking place for HPD events.
*
*******************************************************************************/
u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId)
{
u32 Status;
u32 Status;
/* Do platform initialization here. This is hardware system specific -
* it is up to the user to implement this function. */
Dptx_PlatformInit();
/******************/
/* Do platform initialization here. This is hardware system specific -
* it is up to the user to implement this function. */
Dptx_PlatformInit();
/******************/
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
/* Continuously poll for HPD events. */
while (1) {
Dptx_HpdPoll(InstancePtr);
}
/* Continuously poll for HPD events. */
while (1) {
Dptx_HpdPoll(InstancePtr);
}
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
@ -145,56 +145,56 @@ u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId)
* connection or pulse event is detected, link training will begin (if required)
* and a video stream will be initiated.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note None.
* @note None.
*
*******************************************************************************/
static void Dptx_HpdPoll(XDptx *InstancePtr)
{
u32 InterruptSignalState;
u32 InterruptStatus;
u32 HpdState;
u32 HpdEvent;
u32 HpdPulseDetected;
u32 HpdDuration;
u32 InterruptSignalState;
u32 InterruptStatus;
u32 HpdState;
u32 HpdEvent;
u32 HpdPulseDetected;
u32 HpdDuration;
/* Read interrupt registers. */
InterruptSignalState = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_SIG_STATE);
InterruptStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_STATUS);
/* Read interrupt registers. */
InterruptSignalState = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_SIG_STATE);
InterruptStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_STATUS);
/* Check for HPD events. */
HpdState = InterruptSignalState &
XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK;
HpdEvent = InterruptStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
HpdPulseDetected = InterruptStatus &
XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
if (HpdPulseDetected) {
HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_HPD_DURATION);
}
/* Check for HPD events. */
HpdState = InterruptSignalState &
XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK;
HpdEvent = InterruptStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
HpdPulseDetected = InterruptStatus &
XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
if (HpdPulseDetected) {
HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_HPD_DURATION);
}
/* HPD event handling. */
if (HpdState && HpdEvent) {
xil_printf("+===> HPD connection event detected.\n");
/* HPD event handling. */
if (HpdState && HpdEvent) {
xil_printf("+===> HPD connection event detected.\n");
/* Initiate link training. */
Dptx_Run(InstancePtr);
}
else if (HpdState && HpdPulseDetected && (HpdDuration >= 250)) {
xil_printf("===> HPD pulse detected.\n");
/* Initiate link training. */
Dptx_Run(InstancePtr);
}
else if (HpdState && HpdPulseDetected && (HpdDuration >= 250)) {
xil_printf("===> HPD pulse detected.\n");
/* Re-train if needed. */
Dptx_Run(InstancePtr);
}
else if (!HpdState && HpdEvent) {
xil_printf("+===> HPD disconnection event detected.\n\n");
/* Re-train if needed. */
Dptx_Run(InstancePtr);
}
else if (!HpdState && HpdEvent) {
xil_printf("+===> HPD disconnection event detected.\n\n");
/* Disable main link. */
XDptx_DisableMainLink(InstancePtr);
}
/* Disable main link. */
XDptx_DisableMainLink(InstancePtr);
}
}

44
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c
View file

@ -38,7 +38,7 @@
* the DisplayPort TX core that will compare many of the DisplayPort TX core's
* registers against their default reset values.
*
* @note None.
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
@ -62,32 +62,32 @@ u32 Dptx_SelfTestExample(XDptx *InstancePtr, u16 DeviceId);
int main(void)
{
u32 Status;
u32 Status;
Status = Dptx_SelfTestExample(&DptxInstance, DPTX_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf("XDptx_SelfTest failed, check register values.\n");
return XST_FAILURE;
}
xil_printf("XDptx_SelfTest passed.\n");
return Status;
Status = Dptx_SelfTestExample(&DptxInstance, DPTX_DEVICE_ID);
if (Status != XST_SUCCESS) {
xil_printf("XDptx_SelfTest failed, check register values.\n");
return XST_FAILURE;
}
xil_printf("XDptx_SelfTest passed.\n");
return Status;
}
u32 Dptx_SelfTestExample(XDptx *InstancePtr, u16 DeviceId)
{
u32 Status;
XDptx_Config *ConfigPtr;
u32 Status;
XDptx_Config *ConfigPtr;
/* Obtain the device configuration for the DisplayPort TX core. */
ConfigPtr = XDptx_LookupConfig(DeviceId);
if (!ConfigPtr) {
return XST_FAILURE;
}
/* Copy the device configuration into the InstancePtr's Config
* structure. */
XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
/* Obtain the device configuration for the DisplayPort TX core. */
ConfigPtr = XDptx_LookupConfig(DeviceId);
if (!ConfigPtr) {
return XST_FAILURE;
}
/* Copy the device configuration into the InstancePtr's Config
* structure. */
XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
/* Run the self test. */
Status = XDptx_SelfTest(InstancePtr);
return Status;
/* Run the self test. */
Status = XDptx_SelfTest(InstancePtr);
return Status;
}

148
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c
View file

@ -40,16 +40,16 @@
* the user may override the default MicroBlaze sleep with a function that will
* use the hardware timer.
*
* @note This example requires an AXI timer in the system.
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
* @note This example requires an AXI timer in the system.
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
*
* <pre>
* MODIFICATION HISTORY:
@ -69,12 +69,12 @@
/**************************** Function Prototypes *****************************/
u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc);
XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc);
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds);
/*************************** Variable Declarations ****************************/
XTmrCtr TimerCounterInst; /* The timer counter instance. */
XTmrCtr TimerCounterInst; /* The timer counter instance. */
/**************************** Function Definitions ****************************/
@ -82,27 +82,27 @@ XTmrCtr TimerCounterInst; /* The timer counter instance. */
/**
* This function is the main function of the XDptx timer example.
*
* @param None.
* @param None.
*
* @return
* - XST_SUCCESS if the timer example finished successfully.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if the timer example finished successfully.
* - XST_FAILURE otherwise.
*
* @note None.
* @note None.
*
*******************************************************************************/
int main(void)
{
int Status;
u32 Status;
/* Run the XDptx timer example. */
Status = Dptx_TimerExample(&DptxInstance, DPTX_DEVICE_ID,
&TimerCounterInst, &Dptx_CustomWaitUs);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Run the XDptx timer example. */
Status = Dptx_TimerExample(&DptxInstance, DPTX_DEVICE_ID,
&TimerCounterInst, &Dptx_CustomWaitUs);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
@ -112,54 +112,54 @@ int main(void)
* successful, link training will commence and a video stream will start being
* sent over the main link.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param TimerCounterPtr is a pointer to the timer instance.
* @param UserSleepFunc is a pointer to the custom handler for sleep.
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param TimerCounterPtr is a pointer to the timer instance.
* @param UserSleepFunc is a pointer to the custom handler for sleep.
*
* @return
* - XST_SUCCESS if the system was set up correctly and link
* training was successful.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if the system was set up correctly and link
* training was successful.
* - XST_FAILURE otherwise.
*
* @note None.
* @note None.
*
*******************************************************************************/
u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc)
XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc)
{
u32 Status;
u32 Status;
/* Do platform initialization here. This is hardware system specific -
* it is up to the user to implement this function. */
Dptx_PlatformInit();
/*******************/
/* Do platform initialization here. This is hardware system specific -
* it is up to the user to implement this function. */
Dptx_PlatformInit();
/*******************/
/* Set a custom timer handler for improved delay accuracy on MicroBlaze
* systems since the driver does not assume/have a dependency on the
* system having a timer in the FPGA.
* Note: This only has an affect for MicroBlaze systems since the Zynq
* ARM SoC contains a timer, which is used when the driver calls the
* delay function. */
XDptx_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr);
/* Set a custom timer handler for improved delay accuracy on MicroBlaze
* systems since the driver does not assume/have a dependency on the
* system having a timer in the FPGA.
* Note: This only has an affect for MicroBlaze systems since the Zynq
* ARM SoC contains a timer, which is used when the driver calls the
* delay function. */
XDptx_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr);
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
/* A sink monitor must be connected at this point. See the polling or
* interrupt examples for how to wait for a connection event. */
Status = Dptx_Run(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* A sink monitor must be connected at this point. See the polling or
* interrupt examples for how to wait for a connection event. */
Status = Dptx_Run(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
return XST_SUCCESS;
}
/******************************************************************************/
@ -171,28 +171,28 @@ u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
* hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is
* used - XDptx_WaitUs will ignore this custom timer handler.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note Use the XDptx_SetUserTimerHandler driver function to set this
* function as the handler for when the XDptx_WaitUs driver
* function is called.
* @note Use the XDptx_SetUserTimerHandler driver function to set this
* function as the handler for when the XDptx_WaitUs driver
* function is called.
*
*******************************************************************************/
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
u32 TimerVal;
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
u32 TimerVal;
XTmrCtr_Start(XDptx_InstancePtr->UserTimerPtr, 0);
XTmrCtr_Start(XDptx_InstancePtr->UserTimerPtr, 0);
/* Wait specified number of useconds. */
do {
TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0);
}
while (TimerVal < (MicroSeconds *
(XDptx_InstancePtr->Config.SAxiClkHz / 1000000)));
/* Wait specified number of useconds. */
do {
TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0);
}
while (TimerVal < (MicroSeconds *
(XDptx_InstancePtr->Config.SAxiClkHz / 1000000)));
XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0);
XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0);
}

3111
XilinxProcessorIPLib/drivers/dptx/src/xdptx.c
View file

File diff suppressed because it is too large Load diff

581
XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
View file

@ -38,39 +38,39 @@
* Xilinx DisplayPort soft IP core in source (TX) mode.
*
* The Xilinx DisplayPort soft IP supports the following features:
* - 1, 2, or 4 lanes.
* - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
* - 1, 2, or 4 pixel-wide video interfaces.
* - RGB and YCbCr color space.
* - Up to 16 bits per component.
* - Up to 4Kx2K monitor resolution.
* - Auto lane rate and width negotiation.
* - I2C over a 1Mb/s AUX channel.
* - Secondary channel audio support (2 channels).
* - 4 independent video multi-streams.
* - 1, 2, or 4 lanes.
* - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
* - 1, 2, or 4 pixel-wide video interfaces.
* - RGB and YCbCr color space.
* - Up to 16 bits per component.
* - Up to 4Kx2K monitor resolution.
* - Auto lane rate and width negotiation.
* - I2C over a 1Mb/s AUX channel.
* - Secondary channel audio support (2 channels).
* - 4 independent video multi-streams.
*
* The Xilinx DisplayPort soft IP does not support the following features:
* - The automated test feature.
* - Audio (3-8 channel).
* - FAUX.
* - Bridging function.
* - MST audio.
* - eDP optional features.
* - iDP.
* - GTC.
* - The automated test feature.
* - Audio (3-8 channel).
* - FAUX.
* - Bridging function.
* - MST audio.
* - eDP optional features.
* - iDP.
* - GTC.
*
* <b>DisplayPort overview</b>
*
* A DisplayPort link consists of:
* - A unidirectional main link which is used to transport isochronous data
* streams such as video and audio. The main link may use 1, 2, or 4
* lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
* needs to be trained prior to sending streams.
* - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
* link training, link management, and device control.
* - A hot-plug-detect (HPD) signal line is used to determine whether a
* DisplayPort connection exists between the DisplayPort TX connector and
* an RX device. It is serves as an interrupt request by the RX device.
* - A unidirectional main link which is used to transport isochronous data
* streams such as video and audio. The main link may use 1, 2, or 4
* lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
* needs to be trained prior to sending streams.
* - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
* link training, link management, and device control.
* - A hot-plug-detect (HPD) signal line is used to determine whether a
* DisplayPort connection exists between the DisplayPort TX connector and
* an RX device. It is serves as an interrupt request by the RX device.
*
* <b>Driver description</b>
*
@ -84,10 +84,10 @@
* - The LPM manages the main link and is responsible for keeping the link
* synchronized. It will establish a link with a downstream RX device by
* undergoing a link training sequence which consists of:
* - Clock recovery: The clock needs to be recovered and PLLs need to be
* locked for all lanes.
* - Channel equalization: All lanes need to achieve channel equalization
* and and symbol lock, as well as for interlane alignment to take place.
* - Clock recovery: The clock needs to be recovered and PLLs need to be
* locked for all lanes.
* - Channel equalization: All lanes need to achieve channel equalization
* and and symbol lock, as well as for interlane alignment to take place.
* - The SPM manages transportation of an isochronous stream. That is, it will
* initialize and maintain a video stream, establish a virtual channel to a
* sink monitor, and transmit the stream.
@ -158,8 +158,8 @@
* - The driver does not handle audio. See the audio example in the driver
* examples directory for the required sequence for enabling audio.
*
* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
* required with a speed grade of -2 or -3.
* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
* required with a speed grade of -2 or -3.
*
* <pre>
* MODIFICATION HISTORY:
@ -171,8 +171,8 @@
*
*******************************************************************************/
#ifndef XDPTX_H_ /* Prevent circular inclusions */
#define XDPTX_H_ /* by using protection macros. */
#ifndef XDPTX_H_ /* Prevent circular inclusions */
#define XDPTX_H_ /* by using protection macros. */
/******************************* Include Files ********************************/
@ -186,18 +186,19 @@
/**
* This macro checks if there is a connected RX device.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return - TRUE if there is a connection.
* - FALSE if there is no connection.
* @return
* - TRUE if there is a connection.
* - FALSE if there is no connection.
*
* @note C-style signature:
* void XDptx_IsConnected(XDptx *InstancePtr)
* @note C-style signature:
* void XDptx_IsConnected(XDptx *InstancePtr)
*
*******************************************************************************/
#define XDptx_IsConnected(InstancePtr) \
(XDptx_ReadReg(InstancePtr->Config.BaseAddr, \
XDPTX_INTERRUPT_SIG_STATE) & XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK)
(XDptx_ReadReg(InstancePtr->Config.BaseAddr, \
XDPTX_INTERRUPT_SIG_STATE) & XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK)
/****************************** Type Definitions ******************************/
@ -210,116 +211,116 @@
* Where RB stands for reduced blanking.
*/
typedef enum {
XDPTX_VM_640x480_60_P,
XDPTX_VM_800x600_60_P,
XDPTX_VM_848x480_60_P,
XDPTX_VM_1024x768_60_P,
XDPTX_VM_1280x768_60_P_RB,
XDPTX_VM_1280x768_60_P,
XDPTX_VM_1280x800_60_P_RB,
XDPTX_VM_1280x800_60_P,
XDPTX_VM_1280x960_60_P,
XDPTX_VM_1280x1024_60_P,
XDPTX_VM_1360x768_60_P,
XDPTX_VM_1400x1050_60_P_RB,
XDPTX_VM_1400x1050_60_P,
XDPTX_VM_1440x900_60_P_RB,
XDPTX_VM_1440x900_60_P,
XDPTX_VM_1600x1200_60_P,
XDPTX_VM_1680x1050_60_P_RB,
XDPTX_VM_1680x1050_60_P,
XDPTX_VM_1792x1344_60_P,
XDPTX_VM_1856x1392_60_P,
XDPTX_VM_1920x1200_60_P_RB,
XDPTX_VM_1920x1200_60_P,
XDPTX_VM_1920x1440_60_P,
XDPTX_VM_2560x1600_60_P_RB,
XDPTX_VM_2560x1600_60_P,
XDPTX_VM_800x600_56_P,
XDPTX_VM_1600x1200_65_P,
XDPTX_VM_1600x1200_70_P,
XDPTX_VM_1024x768_70_P,
XDPTX_VM_640x480_72_P,
XDPTX_VM_800x600_72_P,
XDPTX_VM_640x480_75_P,
XDPTX_VM_800x600_75_P,
XDPTX_VM_1024x768_75_P,
XDPTX_VM_1152x864_75_P,
XDPTX_VM_1280x768_75_P,
XDPTX_VM_1280x800_75_P,
XDPTX_VM_1280x1024_75_P,
XDPTX_VM_1400x1050_75_P,
XDPTX_VM_1440x900_75_P,
XDPTX_VM_1600x1200_75_P,
XDPTX_VM_1680x1050_75_P,
XDPTX_VM_1792x1344_75_P,
XDPTX_VM_1856x1392_75_P,
XDPTX_VM_1920x1200_75_P,
XDPTX_VM_1920x1440_75_P,
XDPTX_VM_2560x1600_75_P,
XDPTX_VM_640x350_85_P,
XDPTX_VM_640x400_85_P,
XDPTX_VM_720x400_85_P,
XDPTX_VM_640x480_85_P,
XDPTX_VM_800x600_85_P,
XDPTX_VM_1024x768_85_P,
XDPTX_VM_1280x768_85_P,
XDPTX_VM_1280x800_85_P,
XDPTX_VM_1280x960_85_P,
XDPTX_VM_1280x1024_85_P,
XDPTX_VM_1400x1050_85_P,
XDPTX_VM_1440x900_85_P,
XDPTX_VM_1600x1200_85_P,
XDPTX_VM_1680x1050_85_P,
XDPTX_VM_1920x1200_85_P,
XDPTX_VM_2560x1600_85_P,
XDPTX_VM_800x600_120_P_RB,
XDPTX_VM_1024x768_120_P_RB,
XDPTX_VM_1280x768_120_P_RB,
XDPTX_VM_1280x800_120_P_RB,
XDPTX_VM_1280x960_120_P_RB,
XDPTX_VM_1280x1024_120_P_RB,
XDPTX_VM_1360x768_120_P_RB,
XDPTX_VM_1400x1050_120_P_RB,
XDPTX_VM_1440x900_120_P_RB,
XDPTX_VM_1600x1200_120_P_RB,
XDPTX_VM_1680x1050_120_P_RB,
XDPTX_VM_1792x1344_120_P_RB,
XDPTX_VM_1856x1392_120_P_RB,
XDPTX_VM_1920x1200_120_P_RB,
XDPTX_VM_1920x1440_120_P_RB,
XDPTX_VM_2560x1600_120_P_RB,
XDPTX_VM_1366x768_60_P,
XDPTX_VM_1920x1080_60_P,
XDPTX_VM_UHD_30_P,
XDPTX_VM_720_60_P,
XDPTX_VM_480_60_P,
XDPTX_VM_UHD2_60_P,
XDPTX_VM_UHD_60,
XDPTX_VM_USE_EDID_PREFERRED,
XDPTX_VM_LAST = XDPTX_VM_USE_EDID_PREFERRED
XDPTX_VM_640x480_60_P,
XDPTX_VM_800x600_60_P,
XDPTX_VM_848x480_60_P,
XDPTX_VM_1024x768_60_P,
XDPTX_VM_1280x768_60_P_RB,
XDPTX_VM_1280x768_60_P,
XDPTX_VM_1280x800_60_P_RB,
XDPTX_VM_1280x800_60_P,
XDPTX_VM_1280x960_60_P,
XDPTX_VM_1280x1024_60_P,
XDPTX_VM_1360x768_60_P,
XDPTX_VM_1400x1050_60_P_RB,
XDPTX_VM_1400x1050_60_P,
XDPTX_VM_1440x900_60_P_RB,
XDPTX_VM_1440x900_60_P,
XDPTX_VM_1600x1200_60_P,
XDPTX_VM_1680x1050_60_P_RB,
XDPTX_VM_1680x1050_60_P,
XDPTX_VM_1792x1344_60_P,
XDPTX_VM_1856x1392_60_P,
XDPTX_VM_1920x1200_60_P_RB,
XDPTX_VM_1920x1200_60_P,
XDPTX_VM_1920x1440_60_P,
XDPTX_VM_2560x1600_60_P_RB,
XDPTX_VM_2560x1600_60_P,
XDPTX_VM_800x600_56_P,
XDPTX_VM_1600x1200_65_P,
XDPTX_VM_1600x1200_70_P,
XDPTX_VM_1024x768_70_P,
XDPTX_VM_640x480_72_P,
XDPTX_VM_800x600_72_P,
XDPTX_VM_640x480_75_P,
XDPTX_VM_800x600_75_P,
XDPTX_VM_1024x768_75_P,
XDPTX_VM_1152x864_75_P,
XDPTX_VM_1280x768_75_P,
XDPTX_VM_1280x800_75_P,
XDPTX_VM_1280x1024_75_P,
XDPTX_VM_1400x1050_75_P,
XDPTX_VM_1440x900_75_P,
XDPTX_VM_1600x1200_75_P,
XDPTX_VM_1680x1050_75_P,
XDPTX_VM_1792x1344_75_P,
XDPTX_VM_1856x1392_75_P,
XDPTX_VM_1920x1200_75_P,
XDPTX_VM_1920x1440_75_P,
XDPTX_VM_2560x1600_75_P,
XDPTX_VM_640x350_85_P,
XDPTX_VM_640x400_85_P,
XDPTX_VM_720x400_85_P,
XDPTX_VM_640x480_85_P,
XDPTX_VM_800x600_85_P,
XDPTX_VM_1024x768_85_P,
XDPTX_VM_1280x768_85_P,
XDPTX_VM_1280x800_85_P,
XDPTX_VM_1280x960_85_P,
XDPTX_VM_1280x1024_85_P,
XDPTX_VM_1400x1050_85_P,
XDPTX_VM_1440x900_85_P,
XDPTX_VM_1600x1200_85_P,
XDPTX_VM_1680x1050_85_P,
XDPTX_VM_1920x1200_85_P,
XDPTX_VM_2560x1600_85_P,
XDPTX_VM_800x600_120_P_RB,
XDPTX_VM_1024x768_120_P_RB,
XDPTX_VM_1280x768_120_P_RB,
XDPTX_VM_1280x800_120_P_RB,
XDPTX_VM_1280x960_120_P_RB,
XDPTX_VM_1280x1024_120_P_RB,
XDPTX_VM_1360x768_120_P_RB,
XDPTX_VM_1400x1050_120_P_RB,
XDPTX_VM_1440x900_120_P_RB,
XDPTX_VM_1600x1200_120_P_RB,
XDPTX_VM_1680x1050_120_P_RB,
XDPTX_VM_1792x1344_120_P_RB,
XDPTX_VM_1856x1392_120_P_RB,
XDPTX_VM_1920x1200_120_P_RB,
XDPTX_VM_1920x1440_120_P_RB,
XDPTX_VM_2560x1600_120_P_RB,
XDPTX_VM_1366x768_60_P,
XDPTX_VM_1920x1080_60_P,
XDPTX_VM_UHD_30_P,
XDPTX_VM_720_60_P,
XDPTX_VM_480_60_P,
XDPTX_VM_UHD2_60_P,
XDPTX_VM_UHD_60,
XDPTX_VM_USE_EDID_PREFERRED,
XDPTX_VM_LAST = XDPTX_VM_USE_EDID_PREFERRED
} XDptx_VideoMode;
/**
* This typedef contains the display monitor timing attributes for a video mode.
*/
typedef struct {
XDptx_VideoMode VideoMode; /**< Enumerated key. */
u8 DmtId; /**< Standard DMT ID number. */
u16 HResolution; /**< Horizontal resolution. */
u16 VResolution; /**< Vertical resolution. */
u32 PixelClkKhz; /**< Pixel frequency (in KHz). */
u8 Scan; /**< Interlaced/non-interlaced. */
u8 HSyncPolarity; /**< Horizontal polarity. */
u8 VSyncPolarity; /**< Vertical polarity. */
u32 HFrontPorch; /**< Horizontal front porch. */
u32 HSyncPulseWidth; /**< Horizontal synchronization pulse
width. */
u32 HBackPorch; /**< Horizontal back porch. */
u32 VFrontPorch; /**< Vertical front porch. */
u32 VSyncPulseWidth; /**< Vertical synchronization pulse
width.*/
u32 VBackPorch; /**< Vertical back porch. */
XDptx_VideoMode VideoMode; /**< Enumerated key. */
u8 DmtId; /**< Standard DMT ID number. */
u16 HResolution; /**< Horizontal resolution. */
u16 VResolution; /**< Vertical resolution. */
u32 PixelClkKhz; /**< Pixel frequency (in KHz). */
u8 Scan; /**< Interlaced/non-interlaced. */
u8 HSyncPolarity; /**< Horizontal polarity. */
u8 VSyncPolarity; /**< Vertical polarity. */
u32 HFrontPorch; /**< Horizontal front porch. */
u32 HSyncPulseWidth; /**< Horizontal synchronization pulse
width. */
u32 HBackPorch; /**< Horizontal back porch. */
u32 VFrontPorch; /**< Vertical front porch. */
u32 VSyncPulseWidth; /**< Vertical synchronization pulse
width.*/
u32 VBackPorch; /**< Vertical back porch. */
} XDptx_DmtMode;
extern XDptx_DmtMode XDptx_DmtModes[];
@ -328,86 +329,86 @@ extern XDptx_DmtMode XDptx_DmtModes[];
* This typedef contains configuration information for the DisplayPort TX core.
*/
typedef struct {
u16 DeviceId; /**< Device instance ID. */
u32 BaseAddr; /**< The base address of the core. */
u32 SAxiClkHz; /**< The clock frequency of the core's
S_AXI_ACLK port. */
u8 MaxLaneCount; /**< The maximum lane count supported by this
core's instance. */
u8 MaxLinkRate; /**< The maximum link rate supported by this
core's instance. */
u8 MaxBitsPerColor; /**< The maximum bits/color supported by this
core's instance*/
u8 QuadPixelEn; /**< Quad pixel support by this core's
instance. */
u8 DualPixelEn; /**< Dual pixel support by this core's
instance. */
u8 YOnlyEn; /**< YOnly format support by this core's
instance. */
u8 YCrCbEn; /**< YCrCb format support by this core's
instance. */
u16 DeviceId; /**< Device instance ID. */
u32 BaseAddr; /**< The base address of the core. */
u32 SAxiClkHz; /**< The clock frequency of the core's
S_AXI_ACLK port. */
u8 MaxLaneCount; /**< The maximum lane count supported by this
core's instance. */
u8 MaxLinkRate; /**< The maximum link rate supported by this
core's instance. */
u8 MaxBitsPerColor; /**< The maximum bits/color supported by this
core's instance*/
u8 QuadPixelEn; /**< Quad pixel support by this core's
instance. */
u8 DualPixelEn; /**< Dual pixel support by this core's
instance. */
u8 YOnlyEn; /**< YOnly format support by this core's
instance. */
u8 YCrCbEn; /**< YCrCb format support by this core's
instance. */
} XDptx_Config;
/**
* This typedef contains configuration information about the RX device.
*/
typedef struct {
u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
/**< The raw capabilities field
of the RX device's DisplayPort
Configuration Data (DPCD). */
u8 Edid[XDPTX_EDID_SIZE]; /**< The RX device's raw Extended
Display Identification Data
(EDID). */
u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the
RX device's status registers.
The first 4 bytes correspond to
the lane status associated with
clock recovery, channel
equalization, symbol lock, and
interlane alignment. The
remaining 2 bytes represent the
pre-emphasis and voltage swing
level adjustments requested by
the RX device. */
u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
/**< The raw capabilities field
of the RX device's DisplayPort
Configuration Data (DPCD). */
u8 Edid[XDPTX_EDID_SIZE]; /**< The RX device's raw Extended
Display Identification Data
(EDID). */
u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the
RX device's status registers.
The first 4 bytes correspond to
the lane status associated with
clock recovery, channel
equalization, symbol lock, and
interlane alignment. The
remaining 2 bytes represent the
pre-emphasis and voltage swing
level adjustments requested by
the RX device. */
} XDptx_SinkConfig;
/**
* This typedef contains configuration information about the main link settings.
*/
typedef struct {
u8 LaneCount; /**< The current lane count of the main
link. */
u8 LinkRate; /**< The current link rate of the main
link. */
u8 ScramblerEn; /**< Symbol scrambling is currently in
use over the main link. */
u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in
use over the main link. */
u8 DownspreadControl; /**< Downspread control is currently in
use over the main link. */
u8 MaxLaneCount; /**< The maximum lane count of the main
link. */
u8 MaxLinkRate; /**< The maximum link rate of the main
link. */
u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by
the RX device. */
u8 SupportDownspreadControl; /**< Downspread control is supported by
the RX device. */
u8 VsLevel; /**< The current voltage swing level for
each lane. */
u8 PeLevel; /**< The current pre-emphasis/cursor
level for each lane. */
u8 ComponentFormat; /**< The component format currently in
use over the main link. */
u8 DynamicRange; /**< The dynamic range currently in use
over the main link. */
u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in
use over the main link. */
u8 SynchronousClockMode; /**< Synchronous clock mode is currently
in use over the main link. */
u8 Pattern; /**< The current pattern currently in
use over the main link. */
u8 LaneCount; /**< The current lane count of the main
link. */
u8 LinkRate; /**< The current link rate of the main
link. */
u8 ScramblerEn; /**< Symbol scrambling is currently in
use over the main link. */
u8 EnhancedFramingMode; /**< Enhanced frame mode is currently in
use over the main link. */
u8 DownspreadControl; /**< Downspread control is currently in
use over the main link. */
u8 MaxLaneCount; /**< The maximum lane count of the main
link. */
u8 MaxLinkRate; /**< The maximum link rate of the main
link. */
u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by
the RX device. */
u8 SupportDownspreadControl; /**< Downspread control is supported by
the RX device. */
u8 VsLevel; /**< The current voltage swing level for
each lane. */
u8 PeLevel; /**< The current pre-emphasis/cursor
level for each lane. */
u8 ComponentFormat; /**< The component format currently in
use over the main link. */
u8 DynamicRange; /**< The dynamic range currently in use
over the main link. */
u8 YCbCrColorimetry; /**< The YCbCr colorimetry currently in
use over the main link. */
u8 SynchronousClockMode; /**< Synchronous clock mode is currently
in use over the main link. */
u8 Pattern; /**< The current pattern currently in
use over the main link. */
} XDptx_LinkConfig;
/**
@ -415,31 +416,31 @@ typedef struct {
* video will be displayed.
*/
typedef struct {
u32 HClkTotal;
u32 VClkTotal;
u32 HSyncPulseWidth;
u32 VSyncPulseWidth;
u32 HResolution;
u32 VResolution;
u32 HSyncPolarity;
u32 VSyncPolarity;
u32 HStart;
u32 VStart;
u32 VBackPorch;
u32 VFrontPorch;
u32 HBackPorch;
u32 HFrontPorch;
u32 Misc0;
u32 Misc1;
u32 MVid;
u32 NVid;
u32 TransferUnitSize;
u32 UserPixelWidth;
u32 DataPerLane;
u32 AvgBytesPerTU;
u32 InitWait;
u32 Interlaced;
u32 BitsPerColor;
u32 HClkTotal;
u32 VClkTotal;
u32 HSyncPulseWidth;
u32 VSyncPulseWidth;
u32 HResolution;
u32 VResolution;
u32 HSyncPolarity;
u32 VSyncPolarity;
u32 HStart;
u32 VStart;
u32 VBackPorch;
u32 VFrontPorch;
u32 HBackPorch;
u32 HFrontPorch;
u32 Misc0;
u32 Misc1;
u32 MVid;
u32 NVid;
u32 TransferUnitSize;
u32 UserPixelWidth;
u32 DataPerLane;
u32 AvgBytesPerTU;
u32 InitWait;
u32 Interlaced;
u32 BitsPerColor;
} XDptx_MainStreamAttributes;
/******************************************************************************/
@ -451,9 +452,11 @@ typedef struct {
* used, the user may implement their own wait implementation using a hardware
* timer (see example/) for better accuracy.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param MicroSeconds is the number of microseconds to be passed to the
* timer function.
* @param InstancePtr is a pointer to the XDptx instance.
* @param MicroSeconds is the number of microseconds to be passed to the
* timer function.
*
* @note None.
*
*******************************************************************************/
typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
@ -463,7 +466,9 @@ typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) event
* interrupt.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @note None.
*
*******************************************************************************/
typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
@ -473,7 +478,9 @@ typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse
* interrupt.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @note None.
*
*******************************************************************************/
typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr);
@ -484,41 +491,41 @@ typedef void (*XDptx_HpdPulseHandler)(void *InstancePtr);
* this type is then passed to the driver API functions.
*/
typedef struct {
u32 IsReady; /**< Device is initialized and
ready. */
u8 TrainAdaptive; /**< Downshift lane count and
link rate if necessary
during training. */
u8 HasRedriverInPath; /**< Redriver in path requires
different voltage swing
and pre-emphasis. */
XDptx_Config Config; /**< Configuration structure for
the DisplayPort TX
core. */
XDptx_SinkConfig RxConfig; /**< Configuration structure for
the RX device. */
XDptx_LinkConfig LinkConfig; /**< Configuration structure for
the main link. */
XDptx_MainStreamAttributes MsaConfig; /**< Configuration structure for
the main stream
attributes. */
XDptx_TimerHandler UserTimerWaitUs; /**< Custom user function for
delay/sleep. */
void *UserTimerPtr; /**< Pointer to a timer instance
used by the custom user
delay/sleep function. */
XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for Hot-
Plug-Detect (HPD) event
interrupts. */
void *HpdEventCallbackRef; /**< A pointer to the user data
passed to the HPD event
callback function.*/
XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for Hot-
Plug-Detect (HPD) pulse
interrupts. */
void *HpdPulseCallbackRef; /**< A pointer to the user data
passed to the HPD pulse
callback function.*/
u32 IsReady; /**< Device is initialized and
ready. */
u8 TrainAdaptive; /**< Downshift lane count and
link rate if necessary
during training. */
u8 HasRedriverInPath; /**< Redriver in path requires
different voltage swing
and pre-emphasis. */
XDptx_Config Config; /**< Configuration structure for
the DisplayPort TX
core. */
XDptx_SinkConfig RxConfig; /**< Configuration structure for
the RX device. */
XDptx_LinkConfig LinkConfig; /**< Configuration structure for
the main link. */
XDptx_MainStreamAttributes MsaConfig; /**< Configuration structure for
the main stream
attributes. */
XDptx_TimerHandler UserTimerWaitUs; /**< Custom user function for
delay/sleep. */
void *UserTimerPtr; /**< Pointer to a timer instance
used by the custom user
delay/sleep function. */
XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for Hot-
Plug-Detect (HPD) event
interrupts. */
void *HpdEventCallbackRef; /**< A pointer to the user data
passed to the HPD event
callback function.*/
XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for Hot-
Plug-Detect (HPD) pulse
interrupts. */
void *HpdPulseCallbackRef; /**< A pointer to the user data
passed to the HPD pulse
callback function.*/
} XDptx;
/**************************** Function Prototypes *****************************/
@ -526,7 +533,7 @@ typedef struct {
/* xdptx.c: Setup and initialization functions. */
u32 XDptx_InitializeTx(XDptx *InstancePtr);
void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
u32 EffectiveAddr);
u32 EffectiveAddr);
u32 XDptx_GetRxCapabilities(XDptx *InstancePtr);
u32 XDptx_GetEdid(XDptx *InstancePtr);
@ -541,9 +548,9 @@ void XDptx_SetHasRedriverInPath(XDptx *InstancePtr, u8 Set);
u32 XDptx_AuxRead(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data);
u32 XDptx_AuxWrite(XDptx *InstancePtr, u32 Address, u32 NumBytes, void *Data);
u32 XDptx_IicRead(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
u8 NumBytes, void *Data);
u8 NumBytes, void *Data);
u32 XDptx_IicWrite(XDptx *InstancePtr, u8 IicAddress, u8 RegStartAddress,
u8 NumBytes, void *Data);
u8 NumBytes, void *Data);
/* xdptx.c: Functions for controlling the link configuration. */
u32 XDptx_SetDownspread(XDptx *InstancePtr, u8 Enable);
@ -558,23 +565,23 @@ void XDptx_DisableMainLink(XDptx *InstancePtr);
void XDptx_ResetPhy(XDptx *InstancePtr, u32 Reset);
void XDptx_WaitUs(XDptx *InstancePtr, u32 MicroSeconds);
void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
XDptx_TimerHandler CallbackFunc, void *CallbackRef);
XDptx_TimerHandler CallbackFunc, void *CallbackRef);
/* xdptx_spm.c: Stream policy maker functions. */
void XDptx_CfgMsaRecalculate(XDptx *InstancePtr);
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
XDptx_VideoMode VideoMode);
XDptx_VideoMode VideoMode);
void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr);
void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor);
void XDptx_SetVideoMode(XDptx *InstancePtr);
/* xdptx_intr.c: Interrupt handling functions. */
void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
XDptx_HpdEventHandler CallbackFunc, void *CallbackRef);
XDptx_HpdEventHandler CallbackFunc, void *CallbackRef);
void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef);
XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef);
void XDptx_HpdInterruptHandler(XDptx *InstancePtr);
/* xdptx_selftest.c: Self test function. */

1590
XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
View file

File diff suppressed because it is too large Load diff

110
XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
View file

@ -36,7 +36,7 @@
*
* This file contains functions related to XDptx interrupt handling.
*
* @note None.
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
@ -59,26 +59,26 @@
* This function installs a callback function for when a hot-plug-detect event
* interrupt occurs.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param CallbackFunc is the address to the callback function.
* @param CallbackRef is the user data item that will be passed to the
* callback function when it is invoked.
* @param InstancePtr is a pointer to the XDptx instance.
* @param CallbackFunc is the address to the callback function.
* @param CallbackRef is the user data item that will be passed to the
* callback function when it is invoked.
*
* @return None.
* @return None.
*
* @note None.
* @note None.
*
*******************************************************************************/
void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(CallbackFunc != NULL);
Xil_AssertVoid(CallbackRef != NULL);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(CallbackFunc != NULL);
Xil_AssertVoid(CallbackRef != NULL);
InstancePtr->HpdEventHandler = CallbackFunc;
InstancePtr->HpdEventCallbackRef = CallbackRef;
InstancePtr->HpdEventHandler = CallbackFunc;
InstancePtr->HpdEventCallbackRef = CallbackRef;
}
/******************************************************************************/
@ -86,26 +86,26 @@ void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
* This function installs a callback function for when a hot-plug-detect pulse
* interrupt occurs.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param CallbackFunc is the address to the callback function.
* @param CallbackRef is the user data item that will be passed to the
* callback function when it is invoked.
* @param InstancePtr is a pointer to the XDptx instance.
* @param CallbackFunc is the address to the callback function.
* @param CallbackRef is the user data item that will be passed to the
* callback function when it is invoked.
*
* @return None.
* @return None.
*
* @note None.
* @note None.
*
*******************************************************************************/
void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(CallbackFunc != NULL);
Xil_AssertVoid(CallbackRef != NULL);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(CallbackFunc != NULL);
Xil_AssertVoid(CallbackRef != NULL);
InstancePtr->HpdPulseHandler = CallbackFunc;
InstancePtr->HpdPulseCallbackRef = CallbackRef;
InstancePtr->HpdPulseHandler = CallbackFunc;
InstancePtr->HpdPulseCallbackRef = CallbackRef;
}
/******************************************************************************/
@ -115,46 +115,46 @@ void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
* When an interrupt happens, it first detects what kind of interrupt happened,
* then decides which callback function to invoke.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note None.
* @note None.
*
*******************************************************************************/
void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
{
u32 IntrStatus;
u8 HpdEventDetected;
u8 HpdPulseDetected;
u32 HpdDuration;
u32 IntrStatus;
u8 HpdEventDetected;
u8 HpdPulseDetected;
u32 HpdDuration;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
/* Determine what kind of interrupt occurred.
* Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */
IntrStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_STATUS);
IntrStatus &= ~XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_MASK);
/* Determine what kind of interrupt occurred.
* Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */
IntrStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_STATUS);
IntrStatus &= ~XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_MASK);
HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
HpdPulseDetected = IntrStatus &
HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
HpdPulseDetected = IntrStatus &
XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
if (HpdEventDetected) {
InstancePtr->HpdEventHandler(InstancePtr->HpdEventCallbackRef);
}
if (HpdEventDetected) {
InstancePtr->HpdEventHandler(InstancePtr->HpdEventCallbackRef);
}
if (HpdPulseDetected) {
if (HpdPulseDetected) {
/* The source device must debounce the incoming HPD signal by
* sampling the value at an interval greater than 250 ms. */
HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_HPD_DURATION);
if (HpdDuration >= 250) {
InstancePtr->HpdPulseHandler(
InstancePtr->HpdPulseCallbackRef);
}
}
HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_HPD_DURATION);
if (HpdDuration >= 250) {
InstancePtr->HpdPulseHandler(
InstancePtr->HpdPulseCallbackRef);
}
}
}

238
XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
View file

@ -38,7 +38,7 @@
* will check many of the DisplayPort TX's register values against the default
* reset values as a sanity-check that the core is ready to be used.
*
* @note None.
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
@ -63,59 +63,59 @@
*/
u32 ResetValues[53][2] =
{
{XDPTX_LINK_BW_SET, 0},
{XDPTX_LANE_COUNT_SET, 0},
{XDPTX_ENHANCED_FRAME_EN, 0},
{XDPTX_TRAINING_PATTERN_SET, 0},
{XDPTX_LINK_QUAL_PATTERN_SET, 0},
{XDPTX_SCRAMBLING_DISABLE, 0},
{XDPTX_DOWNSPREAD_CTRL, 0},
{XDPTX_SOFT_RESET, 0},
{XDPTX_ENABLE, 0},
{XDPTX_ENABLE_MAIN_STREAM, 0},
{XDPTX_ENABLE_SEC_STREAM, 0},
{XDPTX_FORCE_SCRAMBLER_RESET, 0},
{XDPTX_TX_MST_CONFIG, 0},
{XDPTX_AUX_CMD, 0},
{XDPTX_AUX_WRITE_FIFO, 0},
{XDPTX_AUX_ADDRESS, 0},
{XDPTX_AUX_CLK_DIVIDER, 0},
{XDPTX_TX_USER_FIFO_OVERFLOW, 0},
{XDPTX_AUX_REPLY_DATA, 0},
{XDPTX_AUX_REPLY_CODE, 0},
{XDPTX_AUX_REPLY_COUNT, 0},
{XDPTX_INTERRUPT_MASK, 0x3F},
{XDPTX_REPLY_DATA_COUNT, 0},
{XDPTX_REPLY_STATUS, 0x10},
{XDPTX_STREAM0, 0},
{XDPTX_STREAM1, 0},
{XDPTX_STREAM2, 0},
{XDPTX_STREAM3, 0},
{XDPTX_PHY_CONFIG, 0x03},
{XDPTX_PHY_VOLTAGE_DIFF_LANE_0, 0},
{XDPTX_PHY_VOLTAGE_DIFF_LANE_1, 0},
{XDPTX_PHY_VOLTAGE_DIFF_LANE_2, 0},
{XDPTX_PHY_VOLTAGE_DIFF_LANE_3, 0},
{XDPTX_PHY_TRANSMIT_PRBS7, 0},
{XDPTX_PHY_CLOCK_SELECT, 0},
{XDPTX_TX_PHY_POWER_DOWN, 0},
{XDPTX_PHY_PRECURSOR_LANE_0, 0},
{XDPTX_PHY_PRECURSOR_LANE_1, 0},
{XDPTX_PHY_PRECURSOR_LANE_2, 0},
{XDPTX_PHY_PRECURSOR_LANE_3, 0},
{XDPTX_PHY_POSTCURSOR_LANE_0, 0},
{XDPTX_PHY_POSTCURSOR_LANE_1, 0},
{XDPTX_PHY_POSTCURSOR_LANE_2, 0},
{XDPTX_PHY_POSTCURSOR_LANE_3, 0},
{XDPTX_GT_DRP_COMMAND, 0},
{XDPTX_GT_DRP_READ_DATA, 0},
{XDPTX_GT_DRP_CHANNEL_STATUS, 0},
{XDPTX_TX_AUDIO_CONTROL, 0},
{XDPTX_TX_AUDIO_CHANNELS, 0},
{XDPTX_TX_AUDIO_INFO_DATA, 0},
{XDPTX_TX_AUDIO_MAUD, 0},
{XDPTX_TX_AUDIO_NAUD, 0},
{XDPTX_TX_AUDIO_EXT_DATA, 0}
{XDPTX_LINK_BW_SET, 0},
{XDPTX_LANE_COUNT_SET, 0},
{XDPTX_ENHANCED_FRAME_EN, 0},
{XDPTX_TRAINING_PATTERN_SET, 0},
{XDPTX_LINK_QUAL_PATTERN_SET, 0},
{XDPTX_SCRAMBLING_DISABLE, 0},
{XDPTX_DOWNSPREAD_CTRL, 0},
{XDPTX_SOFT_RESET, 0},
{XDPTX_ENABLE, 0},
{XDPTX_ENABLE_MAIN_STREAM, 0},
{XDPTX_ENABLE_SEC_STREAM, 0},
{XDPTX_FORCE_SCRAMBLER_RESET, 0},
{XDPTX_TX_MST_CONFIG, 0},
{XDPTX_AUX_CMD, 0},
{XDPTX_AUX_WRITE_FIFO, 0},
{XDPTX_AUX_ADDRESS, 0},
{XDPTX_AUX_CLK_DIVIDER, 0},
{XDPTX_TX_USER_FIFO_OVERFLOW, 0},
{XDPTX_AUX_REPLY_DATA, 0},
{XDPTX_AUX_REPLY_CODE, 0},
{XDPTX_AUX_REPLY_COUNT, 0},
{XDPTX_INTERRUPT_MASK, 0x3F},
{XDPTX_REPLY_DATA_COUNT, 0},
{XDPTX_REPLY_STATUS, 0x10},
{XDPTX_STREAM0, 0},
{XDPTX_STREAM1, 0},
{XDPTX_STREAM2, 0},
{XDPTX_STREAM3, 0},
{XDPTX_PHY_CONFIG, 0x03},
{XDPTX_PHY_VOLTAGE_DIFF_LANE_0, 0},
{XDPTX_PHY_VOLTAGE_DIFF_LANE_1, 0},
{XDPTX_PHY_VOLTAGE_DIFF_LANE_2, 0},
{XDPTX_PHY_VOLTAGE_DIFF_LANE_3, 0},
{XDPTX_PHY_TRANSMIT_PRBS7, 0},
{XDPTX_PHY_CLOCK_SELECT, 0},
{XDPTX_TX_PHY_POWER_DOWN, 0},
{XDPTX_PHY_PRECURSOR_LANE_0, 0},
{XDPTX_PHY_PRECURSOR_LANE_1, 0},
{XDPTX_PHY_PRECURSOR_LANE_2, 0},
{XDPTX_PHY_PRECURSOR_LANE_3, 0},
{XDPTX_PHY_POSTCURSOR_LANE_0, 0},
{XDPTX_PHY_POSTCURSOR_LANE_1, 0},
{XDPTX_PHY_POSTCURSOR_LANE_2, 0},
{XDPTX_PHY_POSTCURSOR_LANE_3, 0},
{XDPTX_GT_DRP_COMMAND, 0},
{XDPTX_GT_DRP_READ_DATA, 0},
{XDPTX_GT_DRP_CHANNEL_STATUS, 0},
{XDPTX_TX_AUDIO_CONTROL, 0},
{XDPTX_TX_AUDIO_CHANNELS, 0},
{XDPTX_TX_AUDIO_INFO_DATA, 0},
{XDPTX_TX_AUDIO_MAUD, 0},
{XDPTX_TX_AUDIO_NAUD, 0},
{XDPTX_TX_AUDIO_EXT_DATA, 0}
};
/**
@ -124,26 +124,26 @@ u32 ResetValues[53][2] =
*/
u32 ResetValuesMsa[20][2] =
{
{XDPTX_MAIN_STREAM_HTOTAL, 0},
{XDPTX_MAIN_STREAM_VTOTAL, 0},
{XDPTX_MAIN_STREAM_POLARITY, 0},
{XDPTX_MAIN_STREAM_HSWIDTH, 0},
{XDPTX_MAIN_STREAM_VSWIDTH, 0},
{XDPTX_MAIN_STREAM_HRES, 0},
{XDPTX_MAIN_STREAM_VRES, 0},
{XDPTX_MAIN_STREAM_HSTART, 0},
{XDPTX_MAIN_STREAM_VSTART, 0},
{XDPTX_MAIN_STREAM_MISC0, 0},
{XDPTX_MAIN_STREAM_MISC1, 0},
{XDPTX_M_VID, 0},
{XDPTX_TU_SIZE, 0},
{XDPTX_N_VID, 0},
{XDPTX_USER_PIXEL_WIDTH, 0},
{XDPTX_USER_DATA_COUNT_PER_LANE, 0},
{XDPTX_MAIN_STREAM_INTERLACED, 0},
{XDPTX_MIN_BYTES_PER_TU, 0},
{XDPTX_FRAC_BYTES_PER_TU, 0},
{XDPTX_INIT_WAIT, 32}
{XDPTX_MAIN_STREAM_HTOTAL, 0},
{XDPTX_MAIN_STREAM_VTOTAL, 0},
{XDPTX_MAIN_STREAM_POLARITY, 0},
{XDPTX_MAIN_STREAM_HSWIDTH, 0},
{XDPTX_MAIN_STREAM_VSWIDTH, 0},
{XDPTX_MAIN_STREAM_HRES, 0},
{XDPTX_MAIN_STREAM_VRES, 0},
{XDPTX_MAIN_STREAM_HSTART, 0},
{XDPTX_MAIN_STREAM_VSTART, 0},
{XDPTX_MAIN_STREAM_MISC0, 0},
{XDPTX_MAIN_STREAM_MISC1, 0},
{XDPTX_M_VID, 0},
{XDPTX_TU_SIZE, 0},
{XDPTX_N_VID, 0},
{XDPTX_USER_PIXEL_WIDTH, 0},
{XDPTX_USER_DATA_COUNT_PER_LANE, 0},
{XDPTX_MAIN_STREAM_INTERLACED, 0},
{XDPTX_MIN_BYTES_PER_TU, 0},
{XDPTX_FRAC_BYTES_PER_TU, 0},
{XDPTX_INIT_WAIT, 32}
};
/**************************** Function Definitions ****************************/
@ -153,60 +153,60 @@ u32 ResetValuesMsa[20][2] =
* This function runs a self-test on the XDptx driver/device. The sanity test
* checks whether or not all tested registers hold their default reset values.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return
* - XST_SUCCESS if the self-test passed - all tested registers
* hold their default reset values.
* - XST_FAILURE otherwise.
* - XST_SUCCESS if the self-test passed - all tested registers
* hold their default reset values.
* - XST_FAILURE otherwise.
*
* @note None.
* @note None.
*
*******************************************************************************/
u32 XDptx_SelfTest(XDptx *InstancePtr)
{
u8 Index;
u8 StreamIndex;
u32 StreamOffset;
u32 Val;
u8 Index;
u8 StreamIndex;
u32 StreamOffset;
u32 Val;
/* Compare general usage registers with their default values. */
for (Index = 0; Index < 53; Index++) {
Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
ResetValues[Index][0]);
/* Fail if register does not hold default value. */
if (Val != ResetValues[Index][1]) {
return XST_FAILURE;
}
}
/* Compare general usage registers with their default values. */
for (Index = 0; Index < 53; Index++) {
Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
ResetValues[Index][0]);
/* Fail if register does not hold default value. */
if (Val != ResetValues[Index][1]) {
return XST_FAILURE;
}
}
/* Compare main stream attribute (MSA) registers for all 4 streams with
* their default values. */
for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
/* Determine the MSA register offset for each stream. */
if (StreamIndex == 0) {
StreamOffset = 0;
}
else if (StreamIndex == 1) {
StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET;
}
else if (StreamIndex == 2) {
StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET;
}
else if (StreamIndex == 3) {
StreamOffset = XDPTX_STREAM4_MSA_START_OFFSET;
}
/* Compare main stream attribute (MSA) registers for all 4 streams with
* their default values. */
for (StreamIndex = 0; StreamIndex < 4; StreamIndex++) {
/* Determine the MSA register offset for each stream. */
if (StreamIndex == 0) {
StreamOffset = 0;
}
else if (StreamIndex == 1) {
StreamOffset = XDPTX_STREAM2_MSA_START_OFFSET;
}
else if (StreamIndex == 2) {
StreamOffset = XDPTX_STREAM3_MSA_START_OFFSET;
}
else if (StreamIndex == 3) {
StreamOffset = XDPTX_STREAM4_MSA_START_OFFSET;
}
for (Index = 0; Index < 20; Index++) {
Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
StreamOffset + ResetValuesMsa[Index][0]);
/* Fail if register does not hold default value. */
if (Val != ResetValuesMsa[Index][1]) {
return XST_FAILURE;
}
}
}
for (Index = 0; Index < 20; Index++) {
Val = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
StreamOffset + ResetValuesMsa[Index][0]);
/* Fail if register does not hold default value. */
if (Val != ResetValuesMsa[Index][1]) {
return XST_FAILURE;
}
}
}
/* All tested registers hold their default reset values. */
return XST_SUCCESS;
/* All tested registers hold their default reset values. */
return XST_SUCCESS;
}

28
XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
View file

@ -36,7 +36,7 @@
*
* This file contains static initialization methods for the XDptx driver.
*
* @note None.
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
@ -69,25 +69,25 @@ extern XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES];
* ID. The table XDptx_ConfigTable[] contains the configuration information for
* each device in the system.
*
* @param DeviceId is the unique device ID of the device being looked up.
* @param DeviceId is the unique device ID of the device being looked up.
*
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
* @note None.
*
*******************************************************************************/
XDptx_Config *XDptx_LookupConfig(u16 DeviceId)
{
XDptx_Config *CfgPtr;
u32 Index;
XDptx_Config *CfgPtr;
u32 Index;
for (Index = 0; Index < XPAR_XDPTX_NUM_INSTANCES; Index++) {
if (XDptx_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XDptx_ConfigTable[Index];
break;
}
}
for (Index = 0; Index < XPAR_XDPTX_NUM_INSTANCES; Index++) {
if (XDptx_ConfigTable[Index].DeviceId == DeviceId) {
CfgPtr = &XDptx_ConfigTable[Index];
break;
}
}
return CfgPtr;
return CfgPtr;
}

720
XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
View file

@ -38,7 +38,7 @@
* These functions set up the DisplayPort TX core's main stream attributes that
* determine how a video stream will be displayed.
*
* @note None.
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
@ -60,164 +60,164 @@
static void XDptx_ClearMsaValues(XDptx *InstancePtr);
static void XDptx_SetMsaValues(XDptx *InstancePtr,
XDptx_MainStreamAttributes *MsaConfig);
XDptx_MainStreamAttributes *MsaConfig);
/**************************** Function Definitions ****************************/
/******************************************************************************/
/**
* This function calculates the following Main Stream Attributes (MSA):
* - Transfer unit size
* - User pixel width
* - NVid
* - Horizontal start
* - Vertical start
* - Horizontal total clock
* - Vertical total clock
* - Misc0
* - Misc1
* - Data per lane
* - Average number of bytes per transfer unit
* - Number of initial wait cycles
* - Transfer unit size
* - User pixel width
* - NVid
* - Horizontal start
* - Vertical start
* - Horizontal total clock
* - Vertical total clock
* - Misc0
* - Misc1
* - Data per lane
* - Average number of bytes per transfer unit
* - Number of initial wait cycles
* These values are derived from:
* - Bits per color
* - MVid
* - Horizontal sync polarity
* - Vertical sync polarity
* - Horizontal sync pulse width
* - Vertical sync pulse width
* - Horizontal resolution
* - Vertical resolution
* - Vertical back porch
* - Vertical front porch
* - Horizontal back porch
* - Horizontal front porch
* - Bits per color
* - MVid
* - Horizontal sync polarity
* - Vertical sync polarity
* - Horizontal sync pulse width
* - Vertical sync pulse width
* - Horizontal resolution
* - Vertical resolution
* - Vertical back porch
* - Vertical front porch
* - Horizontal back porch
* - Horizontal front porch
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note The MsaConfig structure is modified with the new, calculated
* values. The main stream attributes that were used to derive the
* calculated values are untouched in the MsaConfig structure.
* @note The MsaConfig structure is modified with the new, calculated
* values. The main stream attributes that were used to derive the
* calculated values are untouched in the MsaConfig structure.
*
*******************************************************************************/
void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
{
u32 VideoBw;
u32 BitsPerPixel;
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
u32 VideoBw;
u32 BitsPerPixel;
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
XDptx_LinkConfig *LinkConfig = &InstancePtr->LinkConfig;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((LinkConfig->LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS));
Xil_AssertVoid((LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_1) ||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_2) ||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4));
Xil_AssertVoid((LinkConfig->SynchronousClockMode == 0) ||
(LinkConfig->SynchronousClockMode == 1));
Xil_AssertVoid((LinkConfig->DynamicRange == 0) ||
(LinkConfig->DynamicRange == 1));
Xil_AssertVoid((LinkConfig->YCbCrColorimetry == 0) ||
(LinkConfig->YCbCrColorimetry == 1));
Xil_AssertVoid((MsaConfig->BitsPerColor == 6) ||
(MsaConfig->BitsPerColor == 8) ||
(MsaConfig->BitsPerColor == 10) ||
(MsaConfig->BitsPerColor == 12) ||
(MsaConfig->BitsPerColor == 16));
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((LinkConfig->LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS));
Xil_AssertVoid((LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_1) ||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_2) ||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4));
Xil_AssertVoid((LinkConfig->SynchronousClockMode == 0) ||
(LinkConfig->SynchronousClockMode == 1));
Xil_AssertVoid((LinkConfig->DynamicRange == 0) ||
(LinkConfig->DynamicRange == 1));
Xil_AssertVoid((LinkConfig->YCbCrColorimetry == 0) ||
(LinkConfig->YCbCrColorimetry == 1));
Xil_AssertVoid((MsaConfig->BitsPerColor == 6) ||
(MsaConfig->BitsPerColor == 8) ||
(MsaConfig->BitsPerColor == 10) ||
(MsaConfig->BitsPerColor == 12) ||
(MsaConfig->BitsPerColor == 16));
/* Fixed transfer unit size. */
MsaConfig->TransferUnitSize = 64;
/* Fixed transfer unit size. */
MsaConfig->TransferUnitSize = 64;
/* Set the user pixel width to handle clocks that exceed the
* capabilities of the DisplayPort TX core. */
if ((MsaConfig->MVid > 300000) &&
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)) {
MsaConfig->UserPixelWidth = 4;
}
else if ((MsaConfig->MVid > 75000) &&
(LinkConfig->LaneCount != XDPTX_LANE_COUNT_SET_1)) {
MsaConfig->UserPixelWidth = 2;
}
else {
MsaConfig->UserPixelWidth = 1;
}
/* Set the user pixel width to handle clocks that exceed the
* capabilities of the DisplayPort TX core. */
if ((MsaConfig->MVid > 300000) &&
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)) {
MsaConfig->UserPixelWidth = 4;
}
else if ((MsaConfig->MVid > 75000) &&
(LinkConfig->LaneCount != XDPTX_LANE_COUNT_SET_1)) {
MsaConfig->UserPixelWidth = 2;
}
else {
MsaConfig->UserPixelWidth = 1;
}
/* Compute the rest of the MSA values. */
MsaConfig->NVid = 27 * 1000 * LinkConfig->LinkRate;
MsaConfig->HStart = MsaConfig->HSyncPulseWidth + MsaConfig->HBackPorch;
MsaConfig->VStart = MsaConfig->VSyncPulseWidth + MsaConfig->VBackPorch;
MsaConfig->HClkTotal = (MsaConfig->HSyncPulseWidth +
MsaConfig->HBackPorch + MsaConfig->HFrontPorch +
MsaConfig->HResolution);
MsaConfig->VClkTotal = (MsaConfig->VSyncPulseWidth +
MsaConfig->VBackPorch + MsaConfig->VFrontPorch +
MsaConfig->VResolution);
/* Compute the rest of the MSA values. */
MsaConfig->NVid = 27 * 1000 * LinkConfig->LinkRate;
MsaConfig->HStart = MsaConfig->HSyncPulseWidth + MsaConfig->HBackPorch;
MsaConfig->VStart = MsaConfig->VSyncPulseWidth + MsaConfig->VBackPorch;
MsaConfig->HClkTotal = (MsaConfig->HSyncPulseWidth +
MsaConfig->HBackPorch + MsaConfig->HFrontPorch +
MsaConfig->HResolution);
MsaConfig->VClkTotal = (MsaConfig->VSyncPulseWidth +
MsaConfig->VBackPorch + MsaConfig->VFrontPorch +
MsaConfig->VResolution);
/* Miscellaneous attributes. */
if (MsaConfig->BitsPerColor == 6) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC;
}
else if (MsaConfig->BitsPerColor == 8) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC;
}
else if (MsaConfig->BitsPerColor == 10) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC;
}
else if (MsaConfig->BitsPerColor == 12) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC;
}
else if (MsaConfig->BitsPerColor == 16) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC;
}
MsaConfig->Misc0 = (MsaConfig->Misc0 <<
XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT) |
(LinkConfig->YCbCrColorimetry <<
XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
(LinkConfig->DynamicRange <<
XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
(LinkConfig->ComponentFormat <<
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
(LinkConfig->SynchronousClockMode);
MsaConfig->Misc1 = 0;
/* Miscellaneous attributes. */
if (MsaConfig->BitsPerColor == 6) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC;
}
else if (MsaConfig->BitsPerColor == 8) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC;
}
else if (MsaConfig->BitsPerColor == 10) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC;
}
else if (MsaConfig->BitsPerColor == 12) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC;
}
else if (MsaConfig->BitsPerColor == 16) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC;
}
MsaConfig->Misc0 = (MsaConfig->Misc0 <<
XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT) |
(LinkConfig->YCbCrColorimetry <<
XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
(LinkConfig->DynamicRange <<
XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
(LinkConfig->ComponentFormat <<
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
(LinkConfig->SynchronousClockMode);
MsaConfig->Misc1 = 0;
MsaConfig->DataPerLane = (MsaConfig->HResolution *
MsaConfig->BitsPerColor * 3 / 16) - LinkConfig->LaneCount;
MsaConfig->DataPerLane = (MsaConfig->HResolution *
MsaConfig->BitsPerColor * 3 / 16) - LinkConfig->LaneCount;
/* Determine the number of bits per pixel for the specified color
* component format. */
if (LinkConfig->ComponentFormat ==
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) {
/* YCbCr422 color component format. */
BitsPerPixel = MsaConfig->BitsPerColor * 2;
}
else {
/* RGB or YCbCr 4:4:4 color component format. */
BitsPerPixel = MsaConfig->BitsPerColor * 3;
}
/* Determine the number of bits per pixel for the specified color
* component format. */
if (LinkConfig->ComponentFormat ==
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) {
/* YCbCr422 color component format. */
BitsPerPixel = MsaConfig->BitsPerColor * 2;
}
else {
/* RGB or YCbCr 4:4:4 color component format. */
BitsPerPixel = MsaConfig->BitsPerColor * 3;
}
/* Calculate the transfer unit size. */
VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8;
MsaConfig->AvgBytesPerTU = (VideoBw * MsaConfig->TransferUnitSize) /
(LinkConfig->LaneCount * (MsaConfig->NVid / 1000));
/* Calculate the transfer unit size. */
VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8;
MsaConfig->AvgBytesPerTU = (VideoBw * MsaConfig->TransferUnitSize) /
(LinkConfig->LaneCount * (MsaConfig->NVid / 1000));
/* The number of initial wait cycles at the start of a new line by the
* framing logic. This allows enough data to be buffered in the input
* FIFO before video is sent. */
MsaConfig->InitWait = (MsaConfig->TransferUnitSize -
(MsaConfig->AvgBytesPerTU / 1000));
if ((MsaConfig->AvgBytesPerTU / 1000) > MsaConfig->TransferUnitSize) {
MsaConfig->InitWait = 0;
}
else if (MsaConfig->InitWait > 10) {
MsaConfig->InitWait -= 10;
}
else {
MsaConfig->InitWait = 0;
}
/* The number of initial wait cycles at the start of a new line by the
* framing logic. This allows enough data to be buffered in the input
* FIFO before video is sent. */
MsaConfig->InitWait = (MsaConfig->TransferUnitSize -
(MsaConfig->AvgBytesPerTU / 1000));
if ((MsaConfig->AvgBytesPerTU / 1000) > MsaConfig->TransferUnitSize) {
MsaConfig->InitWait = 0;
}
else if (MsaConfig->InitWait > 10) {
MsaConfig->InitWait -= 10;
}
else {
MsaConfig->InitWait = 0;
}
}
/******************************************************************************/
@ -227,41 +227,41 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
* from the XDptx_DmtModes[] standard Display Monitor Timing (DMT) table. The
* XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param VideoMode is one of the enumerated standard video modes that is
* used to determine the MSA values to be used.
* @param InstancePtr is a pointer to the XDptx instance.
* @param VideoMode is one of the enumerated standard video modes that is
* used to determine the MSA values to be used.
*
* @return None.
* @return None.
*
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* MSA values associated to the specified video mode.
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* MSA values associated to the specified video mode.
*
*******************************************************************************/
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
XDptx_VideoMode VideoMode)
XDptx_VideoMode VideoMode)
{
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST);
/* Configure the MSA values from the display monitor DMT table. */
MsaConfig->MVid = XDptx_DmtModes[VideoMode].PixelClkKhz;
MsaConfig->HSyncPolarity = XDptx_DmtModes[VideoMode].HSyncPolarity;
MsaConfig->VSyncPolarity = XDptx_DmtModes[VideoMode].VSyncPolarity;
MsaConfig->HSyncPulseWidth = XDptx_DmtModes[VideoMode].HSyncPulseWidth;
MsaConfig->VSyncPulseWidth = XDptx_DmtModes[VideoMode].VSyncPulseWidth;
MsaConfig->HResolution = XDptx_DmtModes[VideoMode].HResolution;
MsaConfig->VResolution = XDptx_DmtModes[VideoMode].VResolution;
MsaConfig->VBackPorch = XDptx_DmtModes[VideoMode].VBackPorch;
MsaConfig->VFrontPorch = XDptx_DmtModes[VideoMode].VFrontPorch;
MsaConfig->HBackPorch = XDptx_DmtModes[VideoMode].HBackPorch;
MsaConfig->HFrontPorch = XDptx_DmtModes[VideoMode].HFrontPorch;
/* Configure the MSA values from the display monitor DMT table. */
MsaConfig->MVid = XDptx_DmtModes[VideoMode].PixelClkKhz;
MsaConfig->HSyncPolarity = XDptx_DmtModes[VideoMode].HSyncPolarity;
MsaConfig->VSyncPolarity = XDptx_DmtModes[VideoMode].VSyncPolarity;
MsaConfig->HSyncPulseWidth = XDptx_DmtModes[VideoMode].HSyncPulseWidth;
MsaConfig->VSyncPulseWidth = XDptx_DmtModes[VideoMode].VSyncPulseWidth;
MsaConfig->HResolution = XDptx_DmtModes[VideoMode].HResolution;
MsaConfig->VResolution = XDptx_DmtModes[VideoMode].VResolution;
MsaConfig->VBackPorch = XDptx_DmtModes[VideoMode].VBackPorch;
MsaConfig->VFrontPorch = XDptx_DmtModes[VideoMode].VFrontPorch;
MsaConfig->HBackPorch = XDptx_DmtModes[VideoMode].HBackPorch;
MsaConfig->HFrontPorch = XDptx_DmtModes[VideoMode].HFrontPorch;
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
}
/******************************************************************************/
@ -271,92 +271,92 @@ void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
* Timing Mode (PTM) information is stored in the sink's Extended Display
* Identification Data (EDID).
*
* @param InstancePtr is a pointer to the XDptx instance
* @param InstancePtr is a pointer to the XDptx instance
*
* @return None.
* @return None.
*
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* main stream attribute values associated to the preferred timing
* of the sink monitor.
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* main stream attribute values associated to the preferred timing
* of the sink monitor.
*
*******************************************************************************/
void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr)
{
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
u8 *Ptm = &InstancePtr->RxConfig.Edid[XDPTX_EDID_PTM];
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
u8 *Ptm = &InstancePtr->RxConfig.Edid[XDPTX_EDID_PTM];
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(Ptm != NULL);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(Ptm != NULL);
/* Configure the MSA values with the PTM information as
* specified by the preferred Detailed Timing Descriptor (DTD) of the
* monitor's EDID.
* Note, the PTM is only required for EDID versions 1.3 a newer. Earlier
* versions may not contain this information. */
u16 HBlank = ((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
Ptm[XDPTX_EDID_DTD_HBLANK_LSB];
/* Configure the MSA values with the PTM information as
* specified by the preferred Detailed Timing Descriptor (DTD) of the
* monitor's EDID.
* Note, the PTM is only required for EDID versions 1.3 a newer. Earlier
* versions may not contain this information. */
u16 HBlank = ((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
Ptm[XDPTX_EDID_DTD_HBLANK_LSB];
u16 VBlank = ((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
Ptm[XDPTX_EDID_DTD_VBLANK_LSB];
u16 VBlank = ((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK) << 8) |
Ptm[XDPTX_EDID_DTD_VBLANK_LSB];
MsaConfig->MVid = ((Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB] << 8) |
Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10;
MsaConfig->MVid = ((Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_MSB] << 8) |
Ptm[XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB]) * 10;
MsaConfig->HSyncPulseWidth =
(((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >>
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) |
Ptm[XDPTX_EDID_DTD_HSPW_LSB];
MsaConfig->HSyncPulseWidth =
(((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_MASK) >>
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HSPW_SHIFT) << 8) |
Ptm[XDPTX_EDID_DTD_HSPW_LSB];
MsaConfig->VSyncPulseWidth =
((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) |
(Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK);
MsaConfig->VSyncPulseWidth =
((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VSPW_MASK) << 8) |
(Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VSPW_MASK);
MsaConfig->HResolution =
(((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
Ptm[XDPTX_EDID_DTD_HRES_LSB];
MsaConfig->HResolution =
(((Ptm[XDPTX_EDID_DTD_HRES_HBLANK_U4] &
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
Ptm[XDPTX_EDID_DTD_HRES_LSB];
MsaConfig->VResolution = (((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
Ptm[XDPTX_EDID_DTD_VRES_LSB];
MsaConfig->VResolution = (((Ptm[XDPTX_EDID_DTD_VRES_VBLANK_U4] &
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_MASK) >>
XDPTX_EDID_DTD_XRES_XBLANK_U4_XRES_SHIFT) << 8) |
Ptm[XDPTX_EDID_DTD_VRES_LSB];
MsaConfig->VFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >>
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) |
((Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >>
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT);
MsaConfig->VFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_MASK) >>
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_VFPORCH_SHIFT) << 8) |
((Ptm[XDPTX_EDID_DTD_VFPORCH_VSPW_L4] &
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_MASK) >>
XDPTX_EDID_DTD_VFPORCH_VSPW_L4_VFPORCH_SHIFT);
MsaConfig->HFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >>
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) |
Ptm[XDPTX_EDID_DTD_HFPORCH_LSB];
MsaConfig->HFrontPorch = (((Ptm[XDPTX_EDID_DTD_XFPORCH_XSPW_U2] &
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_MASK) >>
XDPTX_EDID_DTD_XFPORCH_XSPW_U2_HFPORCH_SHIFT) << 8) |
Ptm[XDPTX_EDID_DTD_HFPORCH_LSB];
MsaConfig->HSyncPolarity = (Ptm[XDPTX_EDID_DTD_SIGNAL] &
XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK) >>
XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT;
MsaConfig->HSyncPolarity = (Ptm[XDPTX_EDID_DTD_SIGNAL] &
XDPTX_EDID_DTD_SIGNAL_HPOLARITY_MASK) >>
XDPTX_EDID_DTD_SIGNAL_HPOLARITY_SHIFT;
MsaConfig->VSyncPolarity = Ptm[XDPTX_EDID_DTD_SIGNAL] &
XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK >>
XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT;
MsaConfig->VSyncPolarity = Ptm[XDPTX_EDID_DTD_SIGNAL] &
XDPTX_EDID_DTD_SIGNAL_VPOLARITY_MASK >>
XDPTX_EDID_DTD_SIGNAL_VPOLARITY_SHIFT;
MsaConfig->VBackPorch = VBlank -
(MsaConfig->VFrontPorch + MsaConfig->VSyncPulseWidth);
MsaConfig->VBackPorch = VBlank -
(MsaConfig->VFrontPorch + MsaConfig->VSyncPulseWidth);
MsaConfig->HBackPorch = HBlank -
(MsaConfig->HFrontPorch + MsaConfig->HSyncPulseWidth);
MsaConfig->HBackPorch = HBlank -
(MsaConfig->HFrontPorch + MsaConfig->HSyncPulseWidth);
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
}
/******************************************************************************/
@ -366,101 +366,101 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr)
* attributes, the rest of the attributes may be derived. The minimal required
* main stream attributes that must be contained in the MsaConfigCustom
* structure are:
* - MVid
* - Horizontal sync polarity
* - Vertical sync polarity
* - Horizontal sync pulse width
* - Vertical sync pulse width
* - Horizontal resolution
* - Vertical resolution
* - Vertical back porch
* - Vertical front porch
* - Horizontal back porch
* - Horizontal front porch
* - MVid
* - Horizontal sync polarity
* - Vertical sync polarity
* - Horizontal sync pulse width
* - Vertical sync pulse width
* - Horizontal resolution
* - Vertical resolution
* - Vertical back porch
* - Vertical front porch
* - Horizontal back porch
* - Horizontal front porch
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param MsaConfigCustom is the structure that will be used to copy the
* main stream attributes from (into InstancePtr->MsaConfig).
* @param Recalculate is a boolean enable that determines whether or not
* the main stream attributes should be recalculated.
* @param InstancePtr is a pointer to the XDptx instance.
* @param MsaConfigCustom is the structure that will be used to copy the
* main stream attributes from (into InstancePtr->MsaConfig).
* @param Recalculate is a boolean enable that determines whether or not
* the main stream attributes should be recalculated.
*
* @return None.
* @return None.
*
* @note The InstancePtr-> MsaConfig structure is modified with the new
* values.
* @note The InstancePtr-> MsaConfig structure is modified with the new
* values.
*
*******************************************************************************/
void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate)
{
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(MsaConfigCustom != NULL);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(MsaConfigCustom != NULL);
/* Copy the MSA values from the user configuration structure. */
MsaConfig->MVid = MsaConfigCustom->MVid;
MsaConfig->HSyncPolarity = MsaConfigCustom->HSyncPolarity;
MsaConfig->VSyncPolarity = MsaConfigCustom->VSyncPolarity;
MsaConfig->HSyncPulseWidth = MsaConfigCustom->HSyncPulseWidth;
MsaConfig->VSyncPulseWidth = MsaConfigCustom->VSyncPulseWidth;
MsaConfig->HResolution = MsaConfigCustom->HResolution;
MsaConfig->VResolution = MsaConfigCustom->VResolution;
/* Copy the MSA values from the user configuration structure. */
MsaConfig->MVid = MsaConfigCustom->MVid;
MsaConfig->HSyncPolarity = MsaConfigCustom->HSyncPolarity;
MsaConfig->VSyncPolarity = MsaConfigCustom->VSyncPolarity;
MsaConfig->HSyncPulseWidth = MsaConfigCustom->HSyncPulseWidth;
MsaConfig->VSyncPulseWidth = MsaConfigCustom->VSyncPulseWidth;
MsaConfig->HResolution = MsaConfigCustom->HResolution;
MsaConfig->VResolution = MsaConfigCustom->VResolution;
MsaConfig->VBackPorch = MsaConfigCustom->VBackPorch;
MsaConfig->VFrontPorch = MsaConfigCustom->VFrontPorch;
MsaConfig->HBackPorch = MsaConfigCustom->HBackPorch;
MsaConfig->HFrontPorch = MsaConfigCustom->HFrontPorch;
MsaConfig->VBackPorch = MsaConfigCustom->VBackPorch;
MsaConfig->VFrontPorch = MsaConfigCustom->VFrontPorch;
MsaConfig->HBackPorch = MsaConfigCustom->HBackPorch;
MsaConfig->HFrontPorch = MsaConfigCustom->HFrontPorch;
if (Recalculate) {
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
}
else {
/* Use the custom values for the rest. */
MsaConfig->TransferUnitSize = MsaConfigCustom->TransferUnitSize;
MsaConfig->UserPixelWidth = MsaConfigCustom->UserPixelWidth;
MsaConfig->NVid = MsaConfigCustom->NVid;
MsaConfig->HStart = MsaConfigCustom->HStart;
MsaConfig->VStart = MsaConfigCustom->VStart;
MsaConfig->HClkTotal = MsaConfigCustom->HClkTotal;
MsaConfig->VClkTotal = MsaConfigCustom->VClkTotal;
MsaConfig->Misc0 = MsaConfigCustom->Misc0;
MsaConfig->Misc1 = MsaConfigCustom->Misc1;
MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane;
MsaConfig->AvgBytesPerTU = MsaConfigCustom->AvgBytesPerTU;
MsaConfig->InitWait = MsaConfigCustom->InitWait;
}
if (Recalculate) {
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
}
else {
/* Use the custom values for the rest. */
MsaConfig->TransferUnitSize = MsaConfigCustom->TransferUnitSize;
MsaConfig->UserPixelWidth = MsaConfigCustom->UserPixelWidth;
MsaConfig->NVid = MsaConfigCustom->NVid;
MsaConfig->HStart = MsaConfigCustom->HStart;
MsaConfig->VStart = MsaConfigCustom->VStart;
MsaConfig->HClkTotal = MsaConfigCustom->HClkTotal;
MsaConfig->VClkTotal = MsaConfigCustom->VClkTotal;
MsaConfig->Misc0 = MsaConfigCustom->Misc0;
MsaConfig->Misc1 = MsaConfigCustom->Misc1;
MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane;
MsaConfig->AvgBytesPerTU = MsaConfigCustom->AvgBytesPerTU;
MsaConfig->InitWait = MsaConfigCustom->InitWait;
}
}
/******************************************************************************/
/**
* This function sets the bits per color value of the video stream.
*
* @param InstancePtr is a pointer to the XDptx instance
* @param BitsPerColor is the new number of bits per color to use.
* @param InstancePtr is a pointer to the XDptx instance
* @param BitsPerColor is the new number of bits per color to use.
*
* @return None.
* @return None.
*
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* new main stream attributes associated with a new bits per color
* value.
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* new main stream attributes associated with a new bits per color
* value.
*
*******************************************************************************/
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
(BitsPerColor == 10) || (BitsPerColor == 12) ||
(BitsPerColor == 16));
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
(BitsPerColor == 10) || (BitsPerColor == 12) ||
(BitsPerColor == 16));
InstancePtr->MsaConfig.BitsPerColor = BitsPerColor;
InstancePtr->MsaConfig.BitsPerColor = BitsPerColor;
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
}
/******************************************************************************/
@ -469,22 +469,22 @@ void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
* TX core and sets them to the values specified in the main stream attributes
* configuration structure.
*
* @param InstancePtr is a pointer to the XDptx instance
* @param InstancePtr is a pointer to the XDptx instance
*
* @return None.
* @return None.
*
* @note None.
* @note None.
*
*******************************************************************************/
void XDptx_SetVideoMode(XDptx *InstancePtr)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(&InstancePtr->MsaConfig != NULL);
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(&InstancePtr->MsaConfig != NULL);
XDptx_ClearMsaValues(InstancePtr);
XDptx_SetMsaValues(InstancePtr, &InstancePtr->MsaConfig);
XDptx_ClearMsaValues(InstancePtr);
XDptx_SetMsaValues(InstancePtr, &InstancePtr->MsaConfig);
}
/******************************************************************************/
@ -492,16 +492,16 @@ void XDptx_SetVideoMode(XDptx *InstancePtr)
* This function clears the main stream attributes registers of the DisplayPort
* TX core.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
* @return None.
*
* @note None.
* @note None.
*
*******************************************************************************/
static void XDptx_ClearMsaValues(XDptx *InstancePtr)
{
XDptx_Config *Config = &InstancePtr->Config;
XDptx_Config *Config = &InstancePtr->Config;
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL, 0);
@ -530,62 +530,62 @@ static void XDptx_ClearMsaValues(XDptx *InstancePtr)
* core with the values specified in the main stream attributes configuration
* structure.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param MsaConfig is a pointer to the main stream attributes
* configuration structure.
* @param InstancePtr is a pointer to the XDptx instance.
* @param MsaConfig is a pointer to the main stream attributes
* configuration structure.
*
* @return None.
* @return None.
*
* @note None.
* @note None.
*
*******************************************************************************/
static void XDptx_SetMsaValues(XDptx *InstancePtr,
XDptx_MainStreamAttributes *MsaConfig)
XDptx_MainStreamAttributes *MsaConfig)
{
XDptx_Config *Config = &InstancePtr->Config;
XDptx_Config *Config = &InstancePtr->Config;
/* Set the main stream attributes to the associated DisplayPort TX core
* registers. */
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL,
MsaConfig->HClkTotal);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL,
MsaConfig->VClkTotal);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY,
MsaConfig->HSyncPolarity | (MsaConfig->VSyncPolarity <<
XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH,
MsaConfig->HSyncPulseWidth);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH,
MsaConfig->VSyncPulseWidth);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES,
MsaConfig->HResolution);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES,
MsaConfig->VResolution);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART,
MsaConfig->HStart);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART,
MsaConfig->VStart);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0,
MsaConfig->Misc0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1,
MsaConfig->Misc1);
XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID,
MsaConfig->MVid);
XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID,
MsaConfig->NVid);
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH,
MsaConfig->UserPixelWidth);
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE,
MsaConfig->DataPerLane);
/* Set the main stream attributes to the associated DisplayPort TX core
* registers. */
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL,
MsaConfig->HClkTotal);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL,
MsaConfig->VClkTotal);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY,
MsaConfig->HSyncPolarity | (MsaConfig->VSyncPolarity <<
XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH,
MsaConfig->HSyncPulseWidth);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH,
MsaConfig->VSyncPulseWidth);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES,
MsaConfig->HResolution);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES,
MsaConfig->VResolution);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART,
MsaConfig->HStart);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART,
MsaConfig->VStart);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0,
MsaConfig->Misc0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1,
MsaConfig->Misc1);
XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID,
MsaConfig->MVid);
XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID,
MsaConfig->NVid);
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH,
MsaConfig->UserPixelWidth);
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE,
MsaConfig->DataPerLane);
/* Set the transfer unit values to the associated DisplayPort TX core
* registers. */
XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE,
MsaConfig->TransferUnitSize);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU,
MsaConfig->AvgBytesPerTU / 1000);
XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU,
MsaConfig->AvgBytesPerTU % 1000);
XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT,
MsaConfig->InitWait);
/* Set the transfer unit values to the associated DisplayPort TX core
* registers. */
XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE,
MsaConfig->TransferUnitSize);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU,
MsaConfig->AvgBytesPerTU / 1000);
XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU,
MsaConfig->AvgBytesPerTU % 1000);
XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT,
MsaConfig->InitWait);
}

346
XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
View file

@ -36,7 +36,7 @@
*
* Contains display monitor timing (DMT) modes for various standard resolutions.
*
* @note None.
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
@ -61,176 +61,176 @@
*/
XDptx_DmtMode XDptx_DmtModes[] =
{
{XDPTX_VM_640x480_60_P, 0x04, 640, 480, 25175,
0, 1, 1, 8, 96, 40, 2, 2, 25},
{XDPTX_VM_800x600_60_P, 0x09, 800, 600, 40000,
0, 0, 0, 40, 128, 88, 1, 4, 23},
{XDPTX_VM_848x480_60_P, 0x0E, 848, 480, 33750,
0, 0, 0, 16, 112, 112, 6, 8, 23},
{XDPTX_VM_1024x768_60_P, 0x10, 1024, 768, 65000,
0, 1, 1, 24, 136, 160, 3, 6, 29},
{XDPTX_VM_1280x768_60_P_RB, 0x16, 1280, 768, 68250,
0, 0, 1, 48, 32, 80, 3, 7, 12},
{XDPTX_VM_1280x768_60_P, 0x17, 1280, 768, 79500,
0, 1, 0, 64, 128, 192, 3, 7, 20},
{XDPTX_VM_1280x800_60_P_RB, 0x1B, 1280, 800, 71000,
0, 0, 1, 48, 32, 80, 3, 6, 14},
{XDPTX_VM_1280x800_60_P, 0x1C, 1280, 800, 83500,
0, 1, 0, 72, 128, 200, 3, 6, 22},
{XDPTX_VM_1280x960_60_P, 0x20, 1280, 960, 108000,
0, 0, 0, 96, 112, 312, 1, 3, 36},
{XDPTX_VM_1280x1024_60_P, 0x23, 1280, 1024, 108000,
0, 0, 0, 48, 112, 248, 1, 3, 38},
{XDPTX_VM_1360x768_60_P, 0x27, 1360, 768, 85500,
0, 0, 0, 64, 112, 256, 3, 6, 18},
{XDPTX_VM_1400x1050_60_P_RB, 0x29, 1400, 1050, 101000,
0, 0, 1, 48, 32, 80, 3, 4, 23},
{XDPTX_VM_1400x1050_60_P, 0x2A, 1400, 1050, 121750,
0, 1, 0, 88, 144, 232, 3, 4, 32},
{XDPTX_VM_1440x900_60_P_RB, 0x2E, 1440, 900, 88750,
0, 0, 1, 48, 32, 80, 3, 6, 17},
{XDPTX_VM_1440x900_60_P, 0x2F, 1440, 900, 106500,
0, 1, 0, 80, 152, 232, 3, 6, 25},
{XDPTX_VM_1600x1200_60_P, 0x33, 1600, 1200, 162000,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1680x1050_60_P_RB, 0x39, 1680, 1050, 119000,
0, 1, 0, 48, 32, 80, 3, 6, 21},
{XDPTX_VM_1680x1050_60_P, 0x3A, 1680, 1050, 146250,
0, 1, 0, 104, 176, 280, 3, 6, 30},
{XDPTX_VM_1792x1344_60_P, 0x3E, 1792, 1344, 204750,
0, 1, 0, 128, 200, 328, 1, 3, 46},
{XDPTX_VM_1856x1392_60_P, 0x41, 1856, 1392, 218250,
0, 1, 0, 96, 224, 352, 1, 3, 43},
{XDPTX_VM_1920x1200_60_P_RB, 0x44, 1920, 1200, 154000,
0, 0, 1, 48, 32, 80, 3, 6, 26},
{XDPTX_VM_1920x1200_60_P, 0x45, 1920, 1200, 193250,
0, 1, 0, 136, 200, 336, 3, 6, 36},
{XDPTX_VM_1920x1440_60_P, 0x49, 1920, 1440, 234000,
0, 1, 0, 128, 208, 344, 1, 3, 56},
{XDPTX_VM_2560x1600_60_P_RB, 0x4C, 2560, 1600, 268500,
0, 0, 1, 48, 32, 80, 3, 6, 37},
{XDPTX_VM_2560x1600_60_P, 0x4D, 2560, 1600, 348500,
0, 1, 0, 192, 280, 472, 3, 6, 49},
{XDPTX_VM_800x600_56_P, 0x08, 800, 600, 36000,
0, 0, 0, 24, 72, 128, 1, 2, 22},
{XDPTX_VM_1600x1200_65_P, 0x34, 1600, 1200, 175500,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1600x1200_70_P, 0x35, 1600, 1200, 189000,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1024x768_70_P, 0x11, 1024, 768, 75000,
0, 1, 1, 24, 136, 144, 3, 6, 29},
{XDPTX_VM_640x480_72_P, 0x05, 640, 480, 31500,
0, 1, 1, 16, 40, 120, 1, 3, 20},
{XDPTX_VM_800x600_72_P, 0x0A, 800, 600, 50000,
0, 0, 0, 56, 120, 64, 37, 6, 23},
{XDPTX_VM_640x480_75_P, 0x06, 640, 480, 31500,
0, 1, 1, 16, 64, 120, 1, 3, 16},
{XDPTX_VM_800x600_75_P, 0x0B, 800, 600, 49500,
0, 0, 0, 16, 80, 160, 1, 3, 21},
{XDPTX_VM_1024x768_75_P, 0x12, 1024, 768, 78750,
0, 0, 0, 16, 96, 176, 1, 3, 28},
{XDPTX_VM_1152x864_75_P, 0x15, 1152, 864, 108000,
0, 0, 0, 64, 128, 256, 1, 3, 32},
{XDPTX_VM_1280x768_75_P, 0x18, 1280, 768, 102250,
0, 1, 0, 80, 128, 208, 3, 7, 27},
{XDPTX_VM_1280x800_75_P, 0x1D, 1280, 800, 106500,
0, 1, 0, 80, 128, 208, 3, 6, 29},
{XDPTX_VM_1280x1024_75_P, 0x24, 1280, 1024, 135000,
0, 0, 0, 16, 144, 248, 1, 3, 38},
{XDPTX_VM_1400x1050_75_P, 0x2B, 1400, 1050, 156000,
0, 1, 0, 104, 144, 248, 3, 4, 42},
{XDPTX_VM_1440x900_75_P, 0x30, 1440, 900, 136750,
0, 1, 0, 96, 152, 31, 3, 6, 33},
{XDPTX_VM_1600x1200_75_P, 0x36, 1600, 1200, 202500,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1680x1050_75_P, 0x3B, 1680, 1050, 187000,
0, 1, 0, 120, 176, 37, 3, 6, 40},
{XDPTX_VM_1792x1344_75_P, 0x3F, 1792, 1344, 261000,
0, 1, 0, 96, 216, 352, 1, 3, 69},
{XDPTX_VM_1856x1392_75_P, 0x42, 1856, 1392, 288000,
0, 1, 0, 128, 224, 352, 1, 3, 104},
{XDPTX_VM_1920x1200_75_P, 0x46, 1920, 1200, 245250,
0, 1, 0, 136, 208, 344, 3, 6, 46},
{XDPTX_VM_1920x1440_75_P, 0x4A, 1920, 1440, 297000,
0, 1, 0, 144, 224, 352, 1, 3, 56},
{XDPTX_VM_2560x1600_75_P, 0x4E, 2560, 1600, 443250,
0, 1, 0, 208, 280, 488, 3, 6, 63},
{XDPTX_VM_640x350_85_P, 0x01, 640, 350, 31500,
0, 0, 1, 32, 64, 96, 32, 3, 60},
{XDPTX_VM_640x400_85_P, 0x02, 640, 400, 31500,
0, 1, 0, 32, 64, 96, 1, 3, 41},
{XDPTX_VM_720x400_85_P, 0x03, 720, 400, 35500,
0, 1, 0, 36, 72, 108, 1, 3, 42},
{XDPTX_VM_640x480_85_P, 0x07, 640, 480, 36000,
0, 1, 1, 56, 56, 80, 1, 3, 25},
{XDPTX_VM_800x600_85_P, 0x0C, 800, 600, 56250,
0, 0, 0, 32, 64, 152, 1, 3, 27},
{XDPTX_VM_1024x768_85_P, 0x13, 1024, 768, 94500,
0, 0, 0, 48, 96, 208, 1, 3, 36},
{XDPTX_VM_1280x768_85_P, 0x19, 1280, 768, 117500,
0, 1, 0, 80, 136, 216, 3, 7, 31},
{XDPTX_VM_1280x800_85_P, 0x1E, 1280, 800, 122500,
0, 1, 0, 80, 136, 216, 3, 6, 34},
{XDPTX_VM_1280x960_85_P, 0x21, 1280, 960, 148500,
0, 0, 0, 64, 160, 224, 1, 3, 47},
{XDPTX_VM_1280x1024_85_P, 0x25, 1280, 1024, 157500,
0, 0, 0, 64, 160, 224, 1, 3, 44},
{XDPTX_VM_1400x1050_85_P, 0x2C, 1400, 1050, 179500,
0, 1, 0, 104, 152, 256, 3, 4, 48},
{XDPTX_VM_1440x900_85_P, 0x31, 1440, 900, 157000,
0, 1, 0, 104, 152, 32, 3, 6, 39},
{XDPTX_VM_1600x1200_85_P, 0x37, 1600, 1200, 229500,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1680x1050_85_P, 0x3C, 1680, 1050, 214750,
0, 1, 0, 128, 176, 304, 3, 6, 46},
{XDPTX_VM_1920x1200_85_P, 0x47, 1920, 1200, 281250,
0, 1, 0, 144, 208, 352, 3, 6, 53},
{XDPTX_VM_2560x1600_85_P, 0x4F, 2560, 1600, 505250,
0, 1, 0, 208, 280, 488, 3, 6, 73},
{XDPTX_VM_800x600_120_P_RB, 0x0D, 800, 600, 73250,
0, 0, 1, 48, 32, 80, 3, 4, 29},
{XDPTX_VM_1024x768_120_P_RB, 0x14, 1024, 768, 115500,
0, 0, 1, 48, 32, 80, 3, 4, 38},
{XDPTX_VM_1280x768_120_P_RB, 0x1A, 1280, 768, 140250,
0, 0, 1, 48, 32, 80, 3, 7, 35},
{XDPTX_VM_1280x800_120_P_RB, 0x1F, 1280, 800, 146250,
0, 0, 1, 48, 32, 80, 3, 6, 38},
{XDPTX_VM_1280x960_120_P_RB, 0x22, 1280, 960, 175500,
0, 0, 1, 48, 32, 80, 3, 4, 50},
{XDPTX_VM_1280x1024_120_P_RB, 0x26, 1280, 1024, 187250,
0, 0, 1, 48, 32, 80, 3, 7, 50},
{XDPTX_VM_1360x768_120_P_RB, 0x28, 1360, 768, 148250,
0, 0, 1, 48, 32, 80, 3, 5, 37},
{XDPTX_VM_1400x1050_120_P_RB, 0x2D, 1400, 1050, 208000,
0, 0, 1, 48, 32, 80, 3, 4, 55},
{XDPTX_VM_1440x900_120_P_RB, 0x32, 1440, 900, 182750,
0, 0, 1, 48, 32, 80, 3, 6, 44},
{XDPTX_VM_1600x1200_120_P_RB, 0x38, 1600, 1200, 268250,
0, 0, 1, 48, 32, 80, 3, 4, 64},
{XDPTX_VM_1680x1050_120_P_RB, 0x3D, 1680, 1050, 245500,
0, 0, 1, 48, 32, 80, 3, 6, 53},
{XDPTX_VM_1792x1344_120_P_RB, 0x40, 1792, 1344, 333250,
0, 0, 1, 48, 32, 80, 3, 4, 72},
{XDPTX_VM_1856x1392_120_P_RB, 0x43, 1856, 1392, 356500,
0, 0, 1, 48, 32, 80, 3, 4, 75},
{XDPTX_VM_1920x1200_120_P_RB, 0x48, 1920, 1200, 317000,
0, 0, 1, 48, 32, 80, 3, 6, 62},
{XDPTX_VM_1920x1440_120_P_RB, 0x4B, 1920, 1440, 380500,
0, 0, 1, 48, 32, 80, 3, 4, 78},
{XDPTX_VM_2560x1600_120_P_RB, 0x50, 2560, 1600, 552750,
0, 0, 1, 48, 32, 80, 3, 6, 85},
{XDPTX_VM_1366x768_60_P, 0x00, 1366, 768, 72000,
0, 0, 0, 14, 56, 64, 1, 3, 28},
{XDPTX_VM_1920x1080_60_P, 0x00, 1920, 1080, 148500,
0, 1, 1, 88, 44, 148, 4, 5, 36},
{XDPTX_VM_UHD_30_P, 0x00, 3840, 2160, 297000, 0, 0, 1, 176,
88, 296, 20, 10, 60},
{XDPTX_VM_720_60_P, 0x00, 1280, 720, 74250, 0, 1, 1, 110,
40, 220, 5, 5, 20},
{XDPTX_VM_480_60_P, 0x00, 720, 480, 27027, 0, 1, 1, 16, 62,
60, 9, 6, 30},
{XDPTX_VM_UHD2_60_P, 0x00, 1920, 2160, 297000, 0, 0, 1, 88,
44, 148, 20, 10, 60},
{XDPTX_VM_UHD_60, 0x00, 3840, 2160, 594000, 0, 0, 1, 176,
88, 296, 20, 10, 60}
{XDPTX_VM_640x480_60_P, 0x04, 640, 480, 25175,
0, 1, 1, 8, 96, 40, 2, 2, 25},
{XDPTX_VM_800x600_60_P, 0x09, 800, 600, 40000,
0, 0, 0, 40, 128, 88, 1, 4, 23},
{XDPTX_VM_848x480_60_P, 0x0E, 848, 480, 33750,
0, 0, 0, 16, 112, 112, 6, 8, 23},
{XDPTX_VM_1024x768_60_P, 0x10, 1024, 768, 65000,
0, 1, 1, 24, 136, 160, 3, 6, 29},
{XDPTX_VM_1280x768_60_P_RB, 0x16, 1280, 768, 68250,
0, 0, 1, 48, 32, 80, 3, 7, 12},
{XDPTX_VM_1280x768_60_P, 0x17, 1280, 768, 79500,
0, 1, 0, 64, 128, 192, 3, 7, 20},
{XDPTX_VM_1280x800_60_P_RB, 0x1B, 1280, 800, 71000,
0, 0, 1, 48, 32, 80, 3, 6, 14},
{XDPTX_VM_1280x800_60_P, 0x1C, 1280, 800, 83500,
0, 1, 0, 72, 128, 200, 3, 6, 22},
{XDPTX_VM_1280x960_60_P, 0x20, 1280, 960, 108000,
0, 0, 0, 96, 112, 312, 1, 3, 36},
{XDPTX_VM_1280x1024_60_P, 0x23, 1280, 1024, 108000,
0, 0, 0, 48, 112, 248, 1, 3, 38},
{XDPTX_VM_1360x768_60_P, 0x27, 1360, 768, 85500,
0, 0, 0, 64, 112, 256, 3, 6, 18},
{XDPTX_VM_1400x1050_60_P_RB, 0x29, 1400, 1050, 101000,
0, 0, 1, 48, 32, 80, 3, 4, 23},
{XDPTX_VM_1400x1050_60_P, 0x2A, 1400, 1050, 121750,
0, 1, 0, 88, 144, 232, 3, 4, 32},
{XDPTX_VM_1440x900_60_P_RB, 0x2E, 1440, 900, 88750,
0, 0, 1, 48, 32, 80, 3, 6, 17},
{XDPTX_VM_1440x900_60_P, 0x2F, 1440, 900, 106500,
0, 1, 0, 80, 152, 232, 3, 6, 25},
{XDPTX_VM_1600x1200_60_P, 0x33, 1600, 1200, 162000,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1680x1050_60_P_RB, 0x39, 1680, 1050, 119000,
0, 1, 0, 48, 32, 80, 3, 6, 21},
{XDPTX_VM_1680x1050_60_P, 0x3A, 1680, 1050, 146250,
0, 1, 0, 104, 176, 280, 3, 6, 30},
{XDPTX_VM_1792x1344_60_P, 0x3E, 1792, 1344, 204750,
0, 1, 0, 128, 200, 328, 1, 3, 46},
{XDPTX_VM_1856x1392_60_P, 0x41, 1856, 1392, 218250,
0, 1, 0, 96, 224, 352, 1, 3, 43},
{XDPTX_VM_1920x1200_60_P_RB, 0x44, 1920, 1200, 154000,
0, 0, 1, 48, 32, 80, 3, 6, 26},
{XDPTX_VM_1920x1200_60_P, 0x45, 1920, 1200, 193250,
0, 1, 0, 136, 200, 336, 3, 6, 36},
{XDPTX_VM_1920x1440_60_P, 0x49, 1920, 1440, 234000,
0, 1, 0, 128, 208, 344, 1, 3, 56},
{XDPTX_VM_2560x1600_60_P_RB, 0x4C, 2560, 1600, 268500,
0, 0, 1, 48, 32, 80, 3, 6, 37},
{XDPTX_VM_2560x1600_60_P, 0x4D, 2560, 1600, 348500,
0, 1, 0, 192, 280, 472, 3, 6, 49},
{XDPTX_VM_800x600_56_P, 0x08, 800, 600, 36000,
0, 0, 0, 24, 72, 128, 1, 2, 22},
{XDPTX_VM_1600x1200_65_P, 0x34, 1600, 1200, 175500,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1600x1200_70_P, 0x35, 1600, 1200, 189000,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1024x768_70_P, 0x11, 1024, 768, 75000,
0, 1, 1, 24, 136, 144, 3, 6, 29},
{XDPTX_VM_640x480_72_P, 0x05, 640, 480, 31500,
0, 1, 1, 16, 40, 120, 1, 3, 20},
{XDPTX_VM_800x600_72_P, 0x0A, 800, 600, 50000,
0, 0, 0, 56, 120, 64, 37, 6, 23},
{XDPTX_VM_640x480_75_P, 0x06, 640, 480, 31500,
0, 1, 1, 16, 64, 120, 1, 3, 16},
{XDPTX_VM_800x600_75_P, 0x0B, 800, 600, 49500,
0, 0, 0, 16, 80, 160, 1, 3, 21},
{XDPTX_VM_1024x768_75_P, 0x12, 1024, 768, 78750,
0, 0, 0, 16, 96, 176, 1, 3, 28},
{XDPTX_VM_1152x864_75_P, 0x15, 1152, 864, 108000,
0, 0, 0, 64, 128, 256, 1, 3, 32},
{XDPTX_VM_1280x768_75_P, 0x18, 1280, 768, 102250,
0, 1, 0, 80, 128, 208, 3, 7, 27},
{XDPTX_VM_1280x800_75_P, 0x1D, 1280, 800, 106500,
0, 1, 0, 80, 128, 208, 3, 6, 29},
{XDPTX_VM_1280x1024_75_P, 0x24, 1280, 1024, 135000,
0, 0, 0, 16, 144, 248, 1, 3, 38},
{XDPTX_VM_1400x1050_75_P, 0x2B, 1400, 1050, 156000,
0, 1, 0, 104, 144, 248, 3, 4, 42},
{XDPTX_VM_1440x900_75_P, 0x30, 1440, 900, 136750,
0, 1, 0, 96, 152, 31, 3, 6, 33},
{XDPTX_VM_1600x1200_75_P, 0x36, 1600, 1200, 202500,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1680x1050_75_P, 0x3B, 1680, 1050, 187000,
0, 1, 0, 120, 176, 37, 3, 6, 40},
{XDPTX_VM_1792x1344_75_P, 0x3F, 1792, 1344, 261000,
0, 1, 0, 96, 216, 352, 1, 3, 69},
{XDPTX_VM_1856x1392_75_P, 0x42, 1856, 1392, 288000,
0, 1, 0, 128, 224, 352, 1, 3, 104},
{XDPTX_VM_1920x1200_75_P, 0x46, 1920, 1200, 245250,
0, 1, 0, 136, 208, 344, 3, 6, 46},
{XDPTX_VM_1920x1440_75_P, 0x4A, 1920, 1440, 297000,
0, 1, 0, 144, 224, 352, 1, 3, 56},
{XDPTX_VM_2560x1600_75_P, 0x4E, 2560, 1600, 443250,
0, 1, 0, 208, 280, 488, 3, 6, 63},
{XDPTX_VM_640x350_85_P, 0x01, 640, 350, 31500,
0, 0, 1, 32, 64, 96, 32, 3, 60},
{XDPTX_VM_640x400_85_P, 0x02, 640, 400, 31500,
0, 1, 0, 32, 64, 96, 1, 3, 41},
{XDPTX_VM_720x400_85_P, 0x03, 720, 400, 35500,
0, 1, 0, 36, 72, 108, 1, 3, 42},
{XDPTX_VM_640x480_85_P, 0x07, 640, 480, 36000,
0, 1, 1, 56, 56, 80, 1, 3, 25},
{XDPTX_VM_800x600_85_P, 0x0C, 800, 600, 56250,
0, 0, 0, 32, 64, 152, 1, 3, 27},
{XDPTX_VM_1024x768_85_P, 0x13, 1024, 768, 94500,
0, 0, 0, 48, 96, 208, 1, 3, 36},
{XDPTX_VM_1280x768_85_P, 0x19, 1280, 768, 117500,
0, 1, 0, 80, 136, 216, 3, 7, 31},
{XDPTX_VM_1280x800_85_P, 0x1E, 1280, 800, 122500,
0, 1, 0, 80, 136, 216, 3, 6, 34},
{XDPTX_VM_1280x960_85_P, 0x21, 1280, 960, 148500,
0, 0, 0, 64, 160, 224, 1, 3, 47},
{XDPTX_VM_1280x1024_85_P, 0x25, 1280, 1024, 157500,
0, 0, 0, 64, 160, 224, 1, 3, 44},
{XDPTX_VM_1400x1050_85_P, 0x2C, 1400, 1050, 179500,
0, 1, 0, 104, 152, 256, 3, 4, 48},
{XDPTX_VM_1440x900_85_P, 0x31, 1440, 900, 157000,
0, 1, 0, 104, 152, 32, 3, 6, 39},
{XDPTX_VM_1600x1200_85_P, 0x37, 1600, 1200, 229500,
0, 0, 0, 64, 192, 304, 1, 3, 46},
{XDPTX_VM_1680x1050_85_P, 0x3C, 1680, 1050, 214750,
0, 1, 0, 128, 176, 304, 3, 6, 46},
{XDPTX_VM_1920x1200_85_P, 0x47, 1920, 1200, 281250,
0, 1, 0, 144, 208, 352, 3, 6, 53},
{XDPTX_VM_2560x1600_85_P, 0x4F, 2560, 1600, 505250,
0, 1, 0, 208, 280, 488, 3, 6, 73},
{XDPTX_VM_800x600_120_P_RB, 0x0D, 800, 600, 73250,
0, 0, 1, 48, 32, 80, 3, 4, 29},
{XDPTX_VM_1024x768_120_P_RB, 0x14, 1024, 768, 115500,
0, 0, 1, 48, 32, 80, 3, 4, 38},
{XDPTX_VM_1280x768_120_P_RB, 0x1A, 1280, 768, 140250,
0, 0, 1, 48, 32, 80, 3, 7, 35},
{XDPTX_VM_1280x800_120_P_RB, 0x1F, 1280, 800, 146250,
0, 0, 1, 48, 32, 80, 3, 6, 38},
{XDPTX_VM_1280x960_120_P_RB, 0x22, 1280, 960, 175500,
0, 0, 1, 48, 32, 80, 3, 4, 50},
{XDPTX_VM_1280x1024_120_P_RB, 0x26, 1280, 1024, 187250,
0, 0, 1, 48, 32, 80, 3, 7, 50},
{XDPTX_VM_1360x768_120_P_RB, 0x28, 1360, 768, 148250,
0, 0, 1, 48, 32, 80, 3, 5, 37},
{XDPTX_VM_1400x1050_120_P_RB, 0x2D, 1400, 1050, 208000,
0, 0, 1, 48, 32, 80, 3, 4, 55},
{XDPTX_VM_1440x900_120_P_RB, 0x32, 1440, 900, 182750,
0, 0, 1, 48, 32, 80, 3, 6, 44},
{XDPTX_VM_1600x1200_120_P_RB, 0x38, 1600, 1200, 268250,
0, 0, 1, 48, 32, 80, 3, 4, 64},
{XDPTX_VM_1680x1050_120_P_RB, 0x3D, 1680, 1050, 245500,
0, 0, 1, 48, 32, 80, 3, 6, 53},
{XDPTX_VM_1792x1344_120_P_RB, 0x40, 1792, 1344, 333250,
0, 0, 1, 48, 32, 80, 3, 4, 72},
{XDPTX_VM_1856x1392_120_P_RB, 0x43, 1856, 1392, 356500,
0, 0, 1, 48, 32, 80, 3, 4, 75},
{XDPTX_VM_1920x1200_120_P_RB, 0x48, 1920, 1200, 317000,
0, 0, 1, 48, 32, 80, 3, 6, 62},
{XDPTX_VM_1920x1440_120_P_RB, 0x4B, 1920, 1440, 380500,
0, 0, 1, 48, 32, 80, 3, 4, 78},
{XDPTX_VM_2560x1600_120_P_RB, 0x50, 2560, 1600, 552750,
0, 0, 1, 48, 32, 80, 3, 6, 85},
{XDPTX_VM_1366x768_60_P, 0x00, 1366, 768, 72000,
0, 0, 0, 14, 56, 64, 1, 3, 28},
{XDPTX_VM_1920x1080_60_P, 0x00, 1920, 1080, 148500,
0, 1, 1, 88, 44, 148, 4, 5, 36},
{XDPTX_VM_UHD_30_P, 0x00, 3840, 2160, 297000,
0, 0, 1, 176, 88, 296, 20, 10, 60},
{XDPTX_VM_720_60_P, 0x00, 1280, 720, 74250,
0, 1, 1, 110, 40, 220, 5, 5, 20},
{XDPTX_VM_480_60_P, 0x00, 720, 480, 27027,
0, 1, 1, 16, 62, 60, 9, 6, 30},
{XDPTX_VM_UHD2_60_P, 0x00, 1920, 2160, 297000,
0, 0, 1, 88, 44, 148, 20, 10, 60},
{XDPTX_VM_UHD_60, 0x00, 3840, 2160, 594000,
0, 0, 1, 176, 88, 296, 20, 10, 60}
};