llfifo: Add llfifo_v5_0 and Deprecate llfifo_v4_0
Add llfifo_v5_0 deprecate llfifo_v4_0. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
This commit is contained in:
Kedareswara rao Appana
Nava kishore Manne
parent
398cbdc152
commit
86997cfd31
14 changed files with 3645 additions and 0 deletions
47
XilinxProcessorIPLib/drivers/llfifo/data/llfifo.mdd
Executable file
47
XilinxProcessorIPLib/drivers/llfifo/data/llfifo.mdd
Executable file
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@ -0,0 +1,47 @@
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###############################################################################
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#
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# Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# Use of the Software is limited solely to applications:
|
||||
# (a) running on a Xilinx device, or
|
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# (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
#
|
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
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# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
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# SOFTWARE.
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#
|
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# Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
# in advertising or otherwise to promote the sale, use or other dealings in
|
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# this Software without prior written authorization from Xilinx.
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#
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###############################################################################
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#
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# Ver Who Date Changes
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# -------- ------ -------- --------------------------------------------------
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# 4.0 adk 10/12/13 Removed support for xps_ll_fifo
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##############################################################################
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OPTION psf_version = 2.1;
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BEGIN driver llfifo
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OPTION supported_peripherals = (axi_fifo_mm_s_v[4-9]_[1-9]);
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OPTION driver_state = ACTIVE;
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OPTION copyfiles = all;
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OPTION VERSION = 5.0;
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OPTION NAME = llfifo;
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END driver
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53
XilinxProcessorIPLib/drivers/llfifo/data/llfifo.tcl
Executable file
53
XilinxProcessorIPLib/drivers/llfifo/data/llfifo.tcl
Executable file
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@ -0,0 +1,53 @@
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###############################################################################
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#
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# Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
|
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# of this software and associated documentation files (the "Software"), to deal
|
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# in the Software without restriction, including without limitation the rights
|
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
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#
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# The above copyright notice and this permission notice shall be included in
|
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# all copies or substantial portions of the Software.
|
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#
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# Use of the Software is limited solely to applications:
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# (a) running on a Xilinx device, or
|
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# (b) that interact with a Xilinx device through a bus or interconnect.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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#
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# Except as contained in this notice, the name of the Xilinx shall not be used
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# in advertising or otherwise to promote the sale, use or other dealings in
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# this Software without prior written authorization from Xilinx.
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#
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###############################################################################
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#
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# Modification History
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#
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# Ver Who Date Changes
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# ----- ---- -------- -----------------------------------------------
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# 2.00a sdm 07/26/10 Updated to use the string "Axi_Fifo" in canonical
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# definitions for AxiFifo
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# 3.00a adk 08/10/13 Added parameters C_AXI4_BASEADDR and C_AXI4_HIGHADDR
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# and C_DATA_INTERFACE_TYPE inorder to support AXI4
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# Datainterface.
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# 4.0 adk 12/10/13 Updated as per the New Tcl API's
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#
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##############################################################################
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proc generate {drv_handle} {
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::hsi::utils::define_include_file $drv_handle "xparameters.h" "XLlFifo" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_AXI4_BASEADDR" "C_AXI4_HIGHADDR" "C_DATA_INTERFACE_TYPE"
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::hsi::utils::define_canonical_xpars $drv_handle "xparameters.h" "Axi_Fifo" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_AXI4_BASEADDR" "C_AXI4_HIGHADDR" "C_DATA_INTERFACE_TYPE"
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::hsi::utils::define_config_file $drv_handle "xllfifo_g.c" "XLlFifo" "DEVICE_ID" "C_BASEADDR" "C_AXI4_BASEADDR" "C_DATA_INTERFACE_TYPE"
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}
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18
XilinxProcessorIPLib/drivers/llfifo/examples/index.html
Executable file
18
XilinxProcessorIPLib/drivers/llfifo/examples/index.html
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@ -0,0 +1,18 @@
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
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<html>
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<head>
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<meta http-equiv="Content-Language" content="en-us">
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<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
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<title>Driver example applications</title>
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<link rel="stylesheet" type="text/css" href="../help.css">
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</head>
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<body bgcolor="#FFFFFF">
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<h1> Example Applications for the driver llfifo_v4_0 </h1>
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<HR>
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<ul>
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<li>xllfifo_interrupt_example.c <a href="xllfifo_interrupt_example.c">(source)</a> </li>
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<li>xllfifo_polling_example.c <a href="xllfifo_polling_example.c">(source)</a> </li>
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</ul>
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<p><font face="Times New Roman" color="#800000">Copyright <20> 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
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</body>
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</html>
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@ -0,0 +1,619 @@
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/******************************************************************************
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*
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* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
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* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
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*
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||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xllfifo_interrupt_example.c
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* This file demonstrates how to use the Streaming fifo driver on the xilinx AXI
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* Streaming FIFO IP.The AXI4-Stream FIFO core allows memory mapped access to a
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* AXI-Stream interface. The core can be used to interface to AXI Streaming IPs
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* similar to the LogiCORE IP AXI Ethernet core, without having to use full DMA
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* solution.
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*
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* This is the interrupt example for the FIFO it assumes that at the
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* h/w level FIFO is connected in loopback.In these we write known amount of
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* data to the FIFO and wait for interrupts and after compltely receiving the
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* data compares it with the data transmitted.
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*
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* Note: The TDEST Must be enabled in the H/W design inorder to get
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* correct RDR value.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 3.00a adk 08/10/2013 initial release CR:727787
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*
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* </pre>
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*
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* ***************************************************************************
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*/
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/***************************** Include Files *********************************/
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#include "xparameters.h"
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#include "xil_exception.h"
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#include "xstreamer.h"
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#include "xil_cache.h"
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#include "xllfifo.h"
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#include "xstatus.h"
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#ifdef XPAR_UARTNS550_0_BASEADDR
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#include "xuartns550_l.h" /* to use uartns550 */
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#endif
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#ifdef XPAR_INTC_0_DEVICE_ID
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#include "xintc.h"
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#else
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#include "xscugic.h"
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#endif
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FIFO_DEV_ID XPAR_AXI_FIFO_0_DEVICE_ID
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#ifdef XPAR_INTC_0_DEVICE_ID
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#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
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#define FIFO_INTR_ID XPAR_INTC_0_LLFIFO_0_VEC_ID
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#else
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#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
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#define FIFO_INTR_ID XPAR_FABRIC_LLFIFO_0_VEC_ID
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#endif
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#ifdef XPAR_INTC_0_DEVICE_ID
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#define INTC XIntc
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#define INTC_HANDLER XIntc_InterruptHandler
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#else
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#define INTC XScuGic
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#define INTC_HANDLER XScuGic_InterruptHandler
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#endif
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#define WORD_SIZE 4 /* Size of words in bytes */
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#define MAX_PACKET_LEN 4
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#define NO_OF_PACKETS 64
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#define MAX_DATA_BUFFER_SIZE NO_OF_PACKETS*MAX_PACKET_LEN
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#undef DEBUG
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/************************** Function Prototypes ******************************/
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#ifdef XPAR_UARTNS550_0_BASEADDR
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static void Uart550_Setup(void);
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#endif
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int XLlFifoInterruptExample(XLlFifo *InstancePtr, u16 DeviceId);
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int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr);
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static void FifoHandler(XLlFifo *Fifo);
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static void FifoRecvHandler(XLlFifo *Fifo);
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static void FifoSendHandler(XLlFifo *Fifo);
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static void FifoErrorHandler(XLlFifo *InstancePtr, u32 Pending);
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int SetupInterruptSystem(INTC *IntcInstancePtr, XLlFifo *InstancePtr,
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u16 FifoIntrId);
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static void DisableIntrSystem(INTC *IntcInstancePtr, u16 FifoIntrId);
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/*
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* Flags interrupt handlers use to notify the application context the events.
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*/
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volatile int Done;
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volatile int Error;
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/************************** Variable Definitions *****************************/
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/*
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* Device instance definitions
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*/
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XLlFifo FifoInstance;
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/*
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* Instance of the Interrupt Controller
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*/
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static INTC Intc;
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u32 SourceBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE];
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u32 DestinationBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE];
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/*****************************************************************************/
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/**
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*
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* Main function
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*
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* This function is the main entry of the AXI FIFO interrupt test.
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*
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* @param None
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*
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* @return - XST_SUCCESS if tests pass
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* - XST_FAILURE if fails.
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*
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* @note None
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*
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******************************************************************************/
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int main()
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{
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int Status;
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xil_printf("--- Entering main() ---\n\r");
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Status = XLlFifoInterruptExample(&FifoInstance, FIFO_DEV_ID);
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if (Status != XST_SUCCESS) {
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xil_printf("Axi Streaming FIFO Interrupt Example Test Failed");
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xil_printf("--- Exiting main() ---\n\r");
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return XST_FAILURE;
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}
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xil_printf("Axi Streaming FIFO Interrupt Example Test passed\n\r");
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xil_printf("--- Exiting main() ---\n\r");
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return XST_SUCCESS;
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}
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/*****************************************************************************/
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/**
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*
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* This function demonstrates the usage of AXI FIFO
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* It does the following:
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* - Set up the output terminal if UART16550 is in the hardware build
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* - Initialize the Axi FIFO Device.
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* - Set up the interrupt handler for fifo
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* - Transmit the data
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* - Compare the data
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* - Return the result
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*
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* @param InstancePtr is a pointer to the instance of the
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* XLlFifo instance.
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* @param DeviceId is Device ID of the Axi Fifo Deive instance,
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* typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
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* xparameters.h.
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*
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* @return -XST_SUCCESS to indicate success
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* -XST_FAILURE to indicate failure
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*
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******************************************************************************/
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int XLlFifoInterruptExample(XLlFifo *InstancePtr, u16 DeviceId)
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{
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XLlFifo_Config *Config;
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int Status;
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int i;
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int err;
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Status = XST_SUCCESS;
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/* Initial setup for Uart16550 */
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#ifdef XPAR_UARTNS550_0_BASEADDR
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Uart550_Setup();
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#endif
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/* Initialize the Device Configuration Interface driver */
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Config = XLlFfio_LookupConfig(DeviceId);
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if (!Config) {
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xil_printf("No config found for %d\r\n", DeviceId);
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return XST_FAILURE;
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}
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/*
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* This is where the virtual address would be used, this example
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* uses physical address.
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*/
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Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
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if (Status != XST_SUCCESS) {
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xil_printf("Initialization failed\n\r");
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return Status;
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}
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/* Check for the Reset value */
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Status = XLlFifo_Status(InstancePtr);
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XLlFifo_IntClear(InstancePtr,0xffffffff);
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Status = XLlFifo_Status(InstancePtr);
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if(Status != 0x0) {
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xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
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"Expected : 0x0\n\r",
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XLlFifo_Status(InstancePtr));
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return XST_FAILURE;
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}
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/*
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* Connect the Axi Streaming FIFO to the interrupt subsystem such
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* that interrupts can occur. This function is application specific.
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*/
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Status = SetupInterruptSystem(&Intc, InstancePtr, FIFO_INTR_ID);
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if (Status != XST_SUCCESS) {
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xil_printf("Failed intr setup\r\n");
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return XST_FAILURE;
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}
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XLlFifo_IntEnable(InstancePtr, XLLF_INT_ALL_MASK);
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Done = 0;
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/* Transmit the Data Stream */
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Status = TxSend(InstancePtr, SourceBuffer);
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if (Status != XST_SUCCESS){
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xil_printf("Transmission of Data failed\n\r");
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return XST_FAILURE;
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}
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while(!Done);
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/* Check for errors */
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if(Error) {
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xil_printf("Errors in the FIFO\n\r");
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return XST_FAILURE;
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}
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err = 0;
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/* Compare the data sent with the data received */
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xil_printf("Comparing data...\n\r");
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for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
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if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
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err = 1;
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break;
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}
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}
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if (err != 0){
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return XST_FAILURE;
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}
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DisableIntrSystem(&Intc, FIFO_INTR_ID);
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return Status;
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}
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/*****************************************************************************/
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/*
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*
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* TxSend routine, It will send the requested amount of data at the
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* specified addr.
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*
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* @param InstancePtr is a pointer to the instance of the
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* XLlFifo component.
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*
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* @param SourceAddr is the address of the memory
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*
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* @return -XST_SUCCESS to indicate success
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* -XST_FAILURE to indicate failure
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*
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* @note None
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*
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******************************************************************************/
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int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr)
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{
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int i;
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int j;
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xil_printf("Transmitting Data ... \r\n");
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/* Filling the buffer with the */
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for (i=0; i < MAX_DATA_BUFFER_SIZE; i++)
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*(SourceAddr + i) = 0;
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for(i=0; i < NO_OF_PACKETS; i++){
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/* Writing into the FIFO Transmit Port Buffer */
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for (j=0; j < MAX_PACKET_LEN; j++){
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if( XLlFifo_iTxVacancy(InstancePtr) ){
|
||||
XLlFifo_TxPutWord(InstancePtr,
|
||||
*(SourceAddr+(i*MAX_PACKET_LEN)+j));
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Start Transmission by writing transmission length into the TLR */
|
||||
XLlFifo_iTxSetLen(InstancePtr, (MAX_DATA_BUFFER_SIZE * WORD_SIZE));
|
||||
|
||||
|
||||
/* Transmission Complete */
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This is the interrupt handler for the fifo it checks for the type of interrupt
|
||||
* and proceeds according to it.
|
||||
*
|
||||
* @param InstancePtr is a reference to the Fifo device instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void FifoHandler(XLlFifo *InstancePtr)
|
||||
{
|
||||
u32 Pending;
|
||||
|
||||
Pending = XLlFifo_IntPending(InstancePtr);
|
||||
while (Pending) {
|
||||
if (Pending & XLLF_INT_RC_MASK) {
|
||||
FifoRecvHandler(InstancePtr);
|
||||
XLlFifo_IntClear(InstancePtr, XLLF_INT_RC_MASK);
|
||||
}
|
||||
else if (Pending & XLLF_INT_TC_MASK) {
|
||||
FifoSendHandler(InstancePtr);
|
||||
}
|
||||
else if (Pending & XLLF_INT_ERROR_MASK){
|
||||
FifoErrorHandler(InstancePtr, Pending);
|
||||
XLlFifo_IntClear(InstancePtr, XLLF_INT_ERROR_MASK);
|
||||
} else {
|
||||
XLlFifo_IntClear(InstancePtr, Pending);
|
||||
}
|
||||
Pending = XLlFifo_IntPending(InstancePtr);
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This is the Receive handler callback function.
|
||||
*
|
||||
* @param InstancePtr is a reference to the Fifo device instance.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void FifoRecvHandler(XLlFifo *InstancePtr)
|
||||
{
|
||||
int i;
|
||||
u32 RxWord;
|
||||
static u32 ReceiveLength;
|
||||
|
||||
xil_printf("Receiving Data... \n\r");
|
||||
|
||||
/* Read Recieve Length */
|
||||
ReceiveLength = (XLlFifo_iRxGetLen(InstancePtr))/WORD_SIZE;
|
||||
|
||||
while(XLlFifo_iRxOccupancy(InstancePtr)) {
|
||||
for (i=0; i < ReceiveLength; i++) {
|
||||
RxWord = XLlFifo_RxGetWord(InstancePtr);
|
||||
*(DestinationBuffer+i) = RxWord;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* This is the transfer Complete Interrupt handler function.
|
||||
*
|
||||
* This clears the trasmit complete interrupt and set the done flag.
|
||||
*
|
||||
* @param InstancePtr is a pointer to Instance of AXI FIFO device.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
static void FifoSendHandler(XLlFifo *InstancePtr)
|
||||
{
|
||||
XLlFifo_IntClear(InstancePtr, XLLF_INT_TC_MASK);
|
||||
|
||||
Done = 1;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This is the Error handler callback function and this function increments the
|
||||
* the error counter so that the main thread knows the number of errors.
|
||||
*
|
||||
* @param InstancePtr is a pointer to Instance of AXI FIFO device.
|
||||
*
|
||||
* @param Pending is a bitmask of the pending interrupts.
|
||||
*
|
||||
* @return None.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
******************************************************************************/
|
||||
static void FifoErrorHandler(XLlFifo *InstancePtr, u32 Pending)
|
||||
{
|
||||
if (Pending & XLLF_INT_RPURE_MASK) {
|
||||
XLlFifo_RxReset(InstancePtr);
|
||||
} else if (Pending & XLLF_INT_RPORE_MASK) {
|
||||
XLlFifo_RxReset(InstancePtr);
|
||||
} else if(Pending & XLLF_INT_RPUE_MASK) {
|
||||
XLlFifo_RxReset(InstancePtr);
|
||||
} else if (Pending & XLLF_INT_TPOE_MASK) {
|
||||
XLlFifo_TxReset(InstancePtr);
|
||||
} else if (Pending & XLLF_INT_TSE_MASK) {
|
||||
}
|
||||
Error++;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function setups the interrupt system such that interrupts can occur
|
||||
* for the FIFO device. This function is application specific since the
|
||||
* actual system may or may not have an interrupt controller. The FIFO
|
||||
* could be directly connected to a processor without an interrupt controller.
|
||||
* The user should modify this function to fit the application.
|
||||
*
|
||||
* @param InstancePtr contains a pointer to the instance of the FIFO
|
||||
* component which is going to be connected to the interrupt
|
||||
* controller.
|
||||
*
|
||||
* @return XST_SUCCESS if successful, otherwise XST_FAILURE.
|
||||
*
|
||||
* @note None.
|
||||
*
|
||||
****************************************************************************/
|
||||
int SetupInterruptSystem(INTC *IntcInstancePtr, XLlFifo *InstancePtr,
|
||||
u16 FifoIntrId)
|
||||
{
|
||||
|
||||
int Status;
|
||||
|
||||
#ifdef XPAR_INTC_0_DEVICE_ID
|
||||
/*
|
||||
* Initialize the interrupt controller driver so that it is ready to
|
||||
* use.
|
||||
*/
|
||||
Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Connect a device driver handler that will be called when an interrupt
|
||||
* for the device occurs, the device driver handler performs the
|
||||
* specific interrupt processing for the device.
|
||||
*/
|
||||
Status = XIntc_Connect(IntcInstancePtr, FifoIntrId,
|
||||
(XInterruptHandler)FifoHandler,
|
||||
(void *)InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Start the interrupt controller such that interrupts are enabled for
|
||||
* all devices that cause interrupts, specific real mode so that
|
||||
* the FIFO can cause interrupts through the interrupt controller.
|
||||
*/
|
||||
Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable the interrupt for the AXI FIFO device.
|
||||
*/
|
||||
XIntc_Enable(IntcInstancePtr, FifoIntrId);
|
||||
#else
|
||||
XScuGic_Config *IntcConfig;
|
||||
|
||||
/*
|
||||
* Initialize the interrupt controller driver so that it is ready to
|
||||
* use.
|
||||
*/
|
||||
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
|
||||
if (NULL == IntcConfig) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
|
||||
IntcConfig->CpuBaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
XScuGic_SetPriorityTriggerType(IntcInstancePtr, FifoIntrId, 0xA0, 0x3);
|
||||
|
||||
/*
|
||||
* Connect the device driver handler that will be called when an
|
||||
* interrupt for the device occurs, the handler defined above performs
|
||||
* the specific interrupt processing for the device.
|
||||
*/
|
||||
Status = XScuGic_Connect(IntcInstancePtr, FifoIntrId,
|
||||
(Xil_InterruptHandler)FifoHandler,
|
||||
InstancePtr);
|
||||
if (Status != XST_SUCCESS) {
|
||||
return Status;
|
||||
}
|
||||
|
||||
XScuGic_Enable(IntcInstancePtr, FifoIntrId);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize the exception table.
|
||||
*/
|
||||
Xil_ExceptionInit();
|
||||
|
||||
/*
|
||||
* Register the interrupt controller handler with the exception table.
|
||||
*/
|
||||
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
|
||||
(Xil_ExceptionHandler)INTC_HANDLER,
|
||||
(void *)IntcInstancePtr);;
|
||||
|
||||
/*
|
||||
* Enable exceptions.
|
||||
*/
|
||||
Xil_ExceptionEnable();
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function disables the interrupts for the AXI FIFO device.
|
||||
*
|
||||
* @param IntcInstancePtr is the pointer to the INTC component instance
|
||||
* @param FifoIntrId is interrupt ID associated for the FIFO component
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
static void DisableIntrSystem(INTC *IntcInstancePtr, u16 FifoIntrId)
|
||||
{
|
||||
#ifdef XPAR_INTC_0_DEVICE_ID
|
||||
/* Disconnect the interrupts */
|
||||
XIntc_Disconnect(IntcInstancePtr, FifoIntrId);
|
||||
#else
|
||||
XScuGic_Disconnect(IntcInstancePtr, FifoIntrId);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef XPAR_UARTNS550_0_BASEADDR
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
static void Uart550_Setup(void)
|
||||
{
|
||||
|
||||
XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
|
||||
XPAR_XUARTNS550_CLOCK_HZ, 9600);
|
||||
|
||||
XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
|
||||
XUN_LCR_8_DATA_BITS);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,361 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file XLlFifo_polling_example.c
|
||||
* This file demonstrates how to use the Streaming fifo driver on the xilinx AXI
|
||||
* Streaming FIFO IP.The AXI4-Stream FIFO core allows memory mapped access to a
|
||||
* AXI-Stream interface. The core can be used to interface to AXI Streaming IPs
|
||||
* similar to the LogiCORE IP AXI Ethernet core, without having to use full DMA
|
||||
* solution.
|
||||
*
|
||||
* This is the polling example for the FIFO it assumes that at the
|
||||
* h/w level FIFO is connected in loopback.In these we write known amount of
|
||||
* data to the FIFO and Receive the data and compare with the data transmitted.
|
||||
*
|
||||
* Note: The TDEST Must be enabled in the H/W design inorder to
|
||||
* get correct RDR value.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 3.00a adk 08/10/2013 initial release CR:727787
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
* ***************************************************************************
|
||||
*/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
#include "xparameters.h"
|
||||
#include "xil_exception.h"
|
||||
#include "xstreamer.h"
|
||||
#include "xil_cache.h"
|
||||
#include "xllfifo.h"
|
||||
#include "xstatus.h"
|
||||
|
||||
#ifdef XPAR_UARTNS550_0_BASEADDR
|
||||
#include "xuartns550_l.h" /* to use uartns550 */
|
||||
#endif
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
#define FIFO_DEV_ID XPAR_AXI_FIFO_0_DEVICE_ID
|
||||
|
||||
#define WORD_SIZE 4 /* Size of words in bytes */
|
||||
|
||||
#define MAX_PACKET_LEN 4
|
||||
|
||||
#define NO_OF_PACKETS 64
|
||||
|
||||
#define MAX_DATA_BUFFER_SIZE NO_OF_PACKETS*MAX_PACKET_LEN
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
#ifdef XPAR_UARTNS550_0_BASEADDR
|
||||
static void Uart550_Setup(void);
|
||||
#endif
|
||||
|
||||
int XLlFifoPollingExample(XLlFifo *InstancePtr, u16 DeviceId);
|
||||
int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr);
|
||||
int RxReceive(XLlFifo *InstancePtr, u32 *DestinationAddr);
|
||||
|
||||
/************************** Variable Definitions *****************************/
|
||||
/*
|
||||
* Device instance definitions
|
||||
*/
|
||||
XLlFifo FifoInstance;
|
||||
|
||||
u32 SourceBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE];
|
||||
u32 DestinationBuffer[MAX_DATA_BUFFER_SIZE * WORD_SIZE];
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* Main function
|
||||
*
|
||||
* This function is the main entry of the Axi FIFO Polling test.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return - XST_SUCCESS if tests pass
|
||||
* - XST_FAILURE if fails.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
int main()
|
||||
{
|
||||
int Status;
|
||||
|
||||
xil_printf("--- Entering main() ---\n\r");
|
||||
|
||||
Status = XLlFifoPollingExample(&FifoInstance, FIFO_DEV_ID);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("Axi Streaming FIFO Polling Example TestFailed\n\r");
|
||||
xil_printf("--- Exiting main() ---\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
xil_printf("Axi Streaming FIFO Polling Example Test passed\n\r");
|
||||
xil_printf("--- Exiting main() ---\n\r");
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* This function demonstrates the usage AXI FIFO
|
||||
* It does the following:
|
||||
* - Set up the output terminal if UART16550 is in the hardware build
|
||||
* - Initialize the Axi FIFO Device.
|
||||
* - Transmit the data
|
||||
* - Receive the data from fifo
|
||||
* - Compare the data
|
||||
* - Return the result
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance of the
|
||||
* XLlFifo component.
|
||||
* @param DeviceId is Device ID of the Axi Fifo Deive instance,
|
||||
* typically XPAR_<AXI_FIFO_instance>_DEVICE_ID value from
|
||||
* xparameters.h.
|
||||
*
|
||||
* @return -XST_SUCCESS to indicate success
|
||||
* -XST_FAILURE to indicate failure
|
||||
*
|
||||
******************************************************************************/
|
||||
int XLlFifoPollingExample(XLlFifo *InstancePtr, u16 DeviceId)
|
||||
{
|
||||
XLlFifo_Config *Config;
|
||||
int Status;
|
||||
int i;
|
||||
int Error;
|
||||
Status = XST_SUCCESS;
|
||||
|
||||
/* Initial setup for Uart16550 */
|
||||
#ifdef XPAR_UARTNS550_0_BASEADDR
|
||||
|
||||
Uart550_Setup();
|
||||
|
||||
#endif
|
||||
|
||||
/* Initialize the Device Configuration Interface driver */
|
||||
Config = XLlFfio_LookupConfig(DeviceId);
|
||||
if (!Config) {
|
||||
xil_printf("No config found for %d\r\n", DeviceId);
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is where the virtual address would be used, this example
|
||||
* uses physical address.
|
||||
*/
|
||||
Status = XLlFifo_CfgInitialize(InstancePtr, Config, Config->BaseAddress);
|
||||
if (Status != XST_SUCCESS) {
|
||||
xil_printf("Initialization failed\n\r");
|
||||
return Status;
|
||||
}
|
||||
|
||||
/* Check for the Reset value */
|
||||
Status = XLlFifo_Status(InstancePtr);
|
||||
XLlFifo_IntClear(InstancePtr,0xffffffff);
|
||||
Status = XLlFifo_Status(InstancePtr);
|
||||
if(Status != 0x0) {
|
||||
xil_printf("\n ERROR : Reset value of ISR0 : 0x%x\t"
|
||||
"Expected : 0x0\n\r",
|
||||
XLlFifo_Status(InstancePtr));
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/* Transmit the Data Stream */
|
||||
Status = TxSend(InstancePtr, SourceBuffer);
|
||||
if (Status != XST_SUCCESS){
|
||||
xil_printf("Transmisson of Data failed\n\r");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
/* Revceive the Data Stream */
|
||||
Status = RxReceive(InstancePtr, DestinationBuffer);
|
||||
if (Status != XST_SUCCESS){
|
||||
xil_printf("Receiving data failed");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
Error = 0;
|
||||
|
||||
/* Compare the data send with the data received */
|
||||
xil_printf(" Comparing data ...\n\r");
|
||||
for( i=0 ; i<MAX_DATA_BUFFER_SIZE ; i++ ){
|
||||
if ( *(SourceBuffer + i) != *(DestinationBuffer + i) ){
|
||||
Error = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
if (Error != 0){
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return Status;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* TxSend routine, It will send the requested amount of data at the
|
||||
* specified addr.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance of the
|
||||
* XLlFifo component.
|
||||
*
|
||||
* @param SourceAddr is the address where the FIFO stars writing
|
||||
*
|
||||
* @return -XST_SUCCESS to indicate success
|
||||
* -XST_FAILURE to indicate failure
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
int TxSend(XLlFifo *InstancePtr, u32 *SourceAddr)
|
||||
{
|
||||
|
||||
int i;
|
||||
int j;
|
||||
xil_printf(" Transmitting Data ... \r\n");
|
||||
|
||||
/* Filling the buffer with data */
|
||||
for (i=0;i<MAX_DATA_BUFFER_SIZE;i++)
|
||||
*(SourceAddr + i) = 0;
|
||||
|
||||
for(i=0 ; i < NO_OF_PACKETS ; i++){
|
||||
|
||||
/* Writing into the FIFO Transmit Port Buffer */
|
||||
for (j=0 ; j < MAX_PACKET_LEN ; j++){
|
||||
if( XLlFifo_iTxVacancy(InstancePtr) ){
|
||||
XLlFifo_TxPutWord(InstancePtr,
|
||||
*(SourceAddr+(i*MAX_PACKET_LEN)+j));
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Start Transmission by writing transmission length into the TLR */
|
||||
XLlFifo_iTxSetLen(InstancePtr, (MAX_DATA_BUFFER_SIZE * WORD_SIZE));
|
||||
|
||||
/* Check for Transmission completion */
|
||||
while( !(XLlFifo_IsTxDone(InstancePtr)) ){
|
||||
|
||||
}
|
||||
|
||||
/* Transmission Complete */
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* RxReceive routine.It will receive the data from the FIFO.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the instance of the
|
||||
* XLlFifo instance.
|
||||
*
|
||||
* @param DestinationAddr is the address where to copy the received data.
|
||||
*
|
||||
* @return -XST_SUCCESS to indicate success
|
||||
* -XST_FAILURE to indicate failure
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
int RxReceive (XLlFifo *InstancePtr, u32* DestinationAddr)
|
||||
{
|
||||
|
||||
int i;
|
||||
int Status;
|
||||
u32 RxWord;
|
||||
static u32 ReceiveLength;
|
||||
|
||||
xil_printf(" Receiving data ....\n\r");
|
||||
/* Read Recieve Length */
|
||||
ReceiveLength = (XLlFifo_iRxGetLen(InstancePtr))/WORD_SIZE;
|
||||
|
||||
/* Start Receiving */
|
||||
for ( i=0; i < ReceiveLength; i++){
|
||||
RxWord = 0;
|
||||
RxWord = XLlFifo_RxGetWord(InstancePtr);
|
||||
|
||||
if(XLlFifo_iRxOccupancy(InstancePtr)){
|
||||
RxWord = XLlFifo_RxGetWord(InstancePtr);
|
||||
}
|
||||
*(DestinationAddr+i) = RxWord;
|
||||
}
|
||||
|
||||
Status = XLlFifo_IsRxDone(InstancePtr);
|
||||
if(Status != TRUE){
|
||||
xil_printf("Failing in receive complete ... \r\n");
|
||||
return XST_FAILURE;
|
||||
}
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
#ifdef XPAR_UARTNS550_0_BASEADDR
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
static void Uart550_Setup(void)
|
||||
{
|
||||
|
||||
XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
|
||||
XPAR_XUARTNS550_CLOCK_HZ, 9600);
|
||||
|
||||
XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
|
||||
XUN_LCR_8_DATA_BITS);
|
||||
}
|
||||
#endif
|
||||
27
XilinxProcessorIPLib/drivers/llfifo/src/Makefile
Normal file
27
XilinxProcessorIPLib/drivers/llfifo/src/Makefile
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
COMPILER=
|
||||
ARCHIVER=
|
||||
CP=cp
|
||||
COMPILER_FLAGS=
|
||||
EXTRA_COMPILER_FLAGS=
|
||||
LIB=libxil.a
|
||||
|
||||
RELEASEDIR=../../../lib
|
||||
INCLUDEDIR=../../../include
|
||||
INCLUDES=-I./. -I${INCLUDEDIR}
|
||||
|
||||
INCLUDEFILES:=xllfifo.h xllfifo_hw.h xstreamer.h
|
||||
LIBSOURCES:=*.c
|
||||
OUTS := *.o
|
||||
|
||||
|
||||
libs:
|
||||
echo "Compiling llfifo"
|
||||
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
|
||||
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
|
||||
make clean
|
||||
|
||||
include:
|
||||
${CP} ${INCLUDEFILES} ${INCLUDEDIR}
|
||||
|
||||
clean:
|
||||
rm -rf ${OUTS}
|
||||
92
XilinxProcessorIPLib/drivers/llfifo/src/xdebug.h
Normal file
92
XilinxProcessorIPLib/drivers/llfifo/src/xdebug.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef XDEBUG
|
||||
#define XDEBUG
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#if defined(DEBUG) && !defined(NDEBUG)
|
||||
|
||||
#ifndef XDEBUG_WARNING
|
||||
#define XDEBUG_WARNING
|
||||
#warning DEBUG is enabled
|
||||
#endif
|
||||
|
||||
int printf(const char *format, ...);
|
||||
|
||||
#define XDBG_DEBUG_ERROR 0x00000001 /* error condition messages */
|
||||
#define XDBG_DEBUG_GENERAL 0x00000002 /* general debug messages */
|
||||
#define XDBG_DEBUG_ALL 0xFFFFFFFF /* all debugging data */
|
||||
|
||||
#define XDBG_DEBUG_FIFO_REG 0x00000100 /* display register reads/writes */
|
||||
#define XDBG_DEBUG_FIFO_RX 0x00000101 /* receive debug messages */
|
||||
#define XDBG_DEBUG_FIFO_TX 0x00000102 /* transmit debug messages */
|
||||
#define XDBG_DEBUG_FIFO_ALL 0x0000010F /* all fifo debug messages */
|
||||
|
||||
#define XDBG_DEBUG_TEMAC_REG 0x00000400 /* display register reads/writes */
|
||||
#define XDBG_DEBUG_TEMAC_RX 0x00000401 /* receive debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_TX 0x00000402 /* transmit debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_ALL 0x0000040F /* all temac debug messages */
|
||||
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_RX 0x00000800 /* receive debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_TX 0x00000801 /* transmit debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_IOCTL 0x00000802 /* ioctl debug messages */
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_MISC 0x00000803 /* debug msg for other routines */
|
||||
#define XDBG_DEBUG_TEMAC_ADPT_ALL 0x0000080F /* all temac adapter debug messages */
|
||||
|
||||
#define xdbg_current_types (XDBG_DEBUG_ERROR | XDBG_DEBUG_GENERAL | XDBG_DEBUG_FIFO_REG | XDBG_DEBUG_TEMAC_REG)
|
||||
|
||||
#define xdbg_stmnt(x) x
|
||||
|
||||
/* In VxWorks, if _WRS_GNU_VAR_MACROS is defined, special syntax is needed for
|
||||
* macros that accept variable number of arguments
|
||||
*/
|
||||
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
|
||||
#define xdbg_printf(type, args...) (((type) & xdbg_current_types) ? printf (## args) : 0)
|
||||
#else /* ANSI Syntax */
|
||||
#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
|
||||
#endif
|
||||
|
||||
#else /* defined(DEBUG) && !defined(NDEBUG) */
|
||||
|
||||
#define xdbg_stmnt(x)
|
||||
|
||||
/* See VxWorks comments above */
|
||||
#if defined(XENV_VXWORKS) && defined(_WRS_GNU_VAR_MACROS)
|
||||
#define xdbg_printf(type, args...)
|
||||
#else /* ANSI Syntax */
|
||||
#define xdbg_printf(...)
|
||||
#endif
|
||||
|
||||
#endif /* defined(DEBUG) && !defined(NDEBUG) */
|
||||
|
||||
#endif /* XDEBUG */
|
||||
488
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.c
Normal file
488
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.c
Normal file
|
|
@ -0,0 +1,488 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xllfifo.c
|
||||
*
|
||||
* The Xilinx local link FIFO driver component. This driver supports the
|
||||
* Xilinx xps_ll_fifo core.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a jvb 10/13/06 First release
|
||||
* 1.00a xd 12/17/07 Added type casting to fix CR #456850
|
||||
* 1.02a jz 12/04/09 Hal phase 1 support
|
||||
* 2.00a hbm 01/20/10 Hal phase 1 support, bump up major release
|
||||
* 2.01a asa 09/17/10 Added code for resetting Streaming interface
|
||||
* for CR574868
|
||||
* 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Updated
|
||||
* XLlFifo_RxGetWord, XLlFifo_TxPutword inorder to
|
||||
* handle AXI4 Datainterface. Added Config
|
||||
* initialization for the driver.
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xstatus.h"
|
||||
#include "xllfifo.h"
|
||||
#include "xil_assert.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
#define FIFO_WIDTH_BYTES 4
|
||||
|
||||
/*
|
||||
* Implementation Notes:
|
||||
*
|
||||
* This Fifo driver makes use of a byte streamer driver (xstreamer.h). The code
|
||||
* is structured like so:
|
||||
*
|
||||
* +--------------------+
|
||||
* | llfifo |
|
||||
* | +----------------+
|
||||
* | | +--------------+
|
||||
* | | | xstreamer |
|
||||
* | | +--------------+
|
||||
* | +----------------+
|
||||
* | |
|
||||
* +--------------------+
|
||||
*
|
||||
* Initialization
|
||||
* At initialization time this driver (llfifo) sets up the streamer objects to
|
||||
* use routines in this driver (llfifo) to perform the actual I/O to the H/W
|
||||
* FIFO core.
|
||||
*
|
||||
* Operation
|
||||
* Once the streamer objects are set up, the API routines in this driver, just
|
||||
* call through to the streamer driver to perform the read/write operations.
|
||||
* The streamer driver will eventually make calls back into the routines (which
|
||||
* reside in this driver) given at initialization to peform the actual I/O.
|
||||
*
|
||||
* Interrupts
|
||||
* Interrupts are handled in the OS/Application layer above this driver.
|
||||
*/
|
||||
|
||||
xdbg_stmnt(u32 _xllfifo_rr_value;)
|
||||
xdbg_stmnt(u32 _xllfifo_ipie_value;)
|
||||
xdbg_stmnt(u32 _xllfifo_ipis_value;)
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XLlFifo_iRxOccupancy returns the number of 32-bit words available (occupancy)
|
||||
* to be read from the receive channel of the FIFO, specified by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_iRxOccupancy returns the occupancy count in 32-bit words for
|
||||
* the specified FIFO.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 XLlFifo_iRxOccupancy(XLlFifo *InstancePtr)
|
||||
{
|
||||
Xil_AssertNonvoid(InstancePtr);
|
||||
|
||||
return XLlFifo_ReadReg(InstancePtr->BaseAddress,
|
||||
XLLF_RDFO_OFFSET);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XLlFifo_iRxGetLen notifies the hardware that the program is ready to receive the
|
||||
* next frame from the receive channel of the FIFO specified by <i>InstancePtr</i>.
|
||||
*
|
||||
* Note that the program must first call XLlFifo_iRxGetLen before pulling data
|
||||
* out of the receive channel of the FIFO with XLlFifo_Read.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_iRxGetLen returns the number of bytes available in the next
|
||||
* frame.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 XLlFifo_iRxGetLen(XLlFifo *InstancePtr)
|
||||
{
|
||||
Xil_AssertNonvoid(InstancePtr);
|
||||
|
||||
return XLlFifo_ReadReg(InstancePtr->BaseAddress,
|
||||
XLLF_RLF_OFFSET);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XLlFifo_iRead_Aligned reads, <i>WordCount</i>, words from the FIFO referenced by
|
||||
* <i>InstancePtr</i> to the block of memory, referenced by <i>BufPtr</i>.
|
||||
*
|
||||
* XLlFifo_iRead_Aligned assumes that <i>BufPtr</i> is already aligned according
|
||||
* to the following hardware limitations:
|
||||
* ppc - aligned on 32 bit boundaries to avoid performance penalties
|
||||
* from unaligned exception handling.
|
||||
* microblaze - aligned on 32 bit boundaries as microblaze does not handle
|
||||
* unaligned transfers.
|
||||
*
|
||||
* Care must be taken to ensure that the number of words read with one or more
|
||||
* calls to XLlFifo_Read() does not exceed the number of bytes (rounded up to
|
||||
* the nearest whole 32 bit word) available given from the last call to
|
||||
* XLlFifo_RxGetLen().
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param BufPtr specifies the memory address to place the data read.
|
||||
*
|
||||
* @param WordCount specifies the number of 32 bit words to read.
|
||||
*
|
||||
* @return XLlFifo_iRead_Aligned always returns XST_SUCCESS. Error handling is
|
||||
* otherwise handled through hardware exceptions and interrupts.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* C Signature: int XLlFifo_iRead_Aligned(XLlFifo *InstancePtr,
|
||||
* void *BufPtr, unsigned WordCount);
|
||||
*
|
||||
******************************************************************************/
|
||||
/* static */ int XLlFifo_iRead_Aligned(XLlFifo *InstancePtr, void *BufPtr,
|
||||
unsigned WordCount)
|
||||
{
|
||||
unsigned WordsRemaining = WordCount;
|
||||
u32 *BufPtrIdx = (u32 *)BufPtr;
|
||||
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "XLlFifo_iRead_Aligned: start\n");
|
||||
Xil_AssertNonvoid(InstancePtr);
|
||||
Xil_AssertNonvoid(BufPtr);
|
||||
/* assert bufer is 32 bit aligned */
|
||||
Xil_AssertNonvoid(((unsigned)BufPtr & 0x3) == 0x0);
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "XLlFifo_iRead_Aligned: after asserts\n");
|
||||
|
||||
while (WordsRemaining) {
|
||||
/* xdbg_printf(XDBG_DEBUG_FIFO_RX,
|
||||
"XLlFifo_iRead_Aligned: WordsRemaining: %d\n",
|
||||
WordsRemaining);
|
||||
*/
|
||||
*BufPtrIdx = XLlFifo_RxGetWord(InstancePtr);
|
||||
BufPtrIdx++;
|
||||
WordsRemaining--;
|
||||
}
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX,
|
||||
"XLlFifo_iRead_Aligned: returning SUCCESS\n");
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XLlFifo_iTxVacancy returns the number of unused 32 bit words available
|
||||
* (vacancy) in the send channel of the FIFO, specified by <i>InstancePtr</i>.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_iTxVacancy returns the vacancy count in 32-bit words for
|
||||
* the specified FIFO.
|
||||
*
|
||||
*****************************************************************************/
|
||||
u32 XLlFifo_iTxVacancy(XLlFifo *InstancePtr)
|
||||
{
|
||||
Xil_AssertNonvoid(InstancePtr);
|
||||
|
||||
return XLlFifo_ReadReg(InstancePtr->BaseAddress,
|
||||
XLLF_TDFV_OFFSET);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XLlFifo_iTxSetLen begins a hardware transfer of data out of the transmit
|
||||
* channel of the FIFO, specified by <i>InstancePtr</i>. <i>Bytes</i> specifies the number
|
||||
* of bytes in the frame to transmit.
|
||||
*
|
||||
* Note that <i>Bytes</i> (rounded up to the nearest whole 32 bit word) must be same
|
||||
* number of words just written using one or more calls to
|
||||
* XLlFifo_iWrite_Aligned()
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param Bytes specifies the number of bytes to transmit.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
******************************************************************************/
|
||||
void XLlFifo_iTxSetLen(XLlFifo *InstancePtr, u32 Bytes)
|
||||
{
|
||||
Xil_AssertVoid(InstancePtr);
|
||||
|
||||
XLlFifo_WriteReg(InstancePtr->BaseAddress, XLLF_TLF_OFFSET,
|
||||
Bytes);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XLlFifo_iWrite_Aligned writes, <i>WordCount</i>, words to the FIFO referenced by
|
||||
* <i>InstancePtr</i> from the block of memory, referenced by <i>BufPtr</i>.
|
||||
*
|
||||
* XLlFifo_iWrite_Aligned assumes that <i>BufPtr</i> is already aligned according
|
||||
* to the following hardware limitations:
|
||||
* ppc - aligned on 32 bit boundaries to avoid performance penalties
|
||||
* from unaligned exception handling.
|
||||
* microblaze - aligned on 32 bit boundaries as microblaze does not handle
|
||||
* unaligned transfers.
|
||||
*
|
||||
* Care must be taken to ensure that the number of words written with one or
|
||||
* more calls to XLlFifo_iWrite_Aligned() matches the number of bytes (rounded up
|
||||
* to the nearest whole 32 bit word) given in the next call to
|
||||
* XLlFifo_iTxSetLen().
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param BufPtr specifies the memory address to place the data read.
|
||||
*
|
||||
* @param WordCount specifies the number of 32 bit words to read.
|
||||
*
|
||||
* @return XLlFifo_iWrite_Aligned always returns XST_SUCCESS. Error handling is
|
||||
* otherwise handled through hardware exceptions and interrupts.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* C Signature: int XLlFifo_iWrite_Aligned(XLlFifo *InstancePtr,
|
||||
* void *BufPtr, unsigned WordCount);
|
||||
*
|
||||
******************************************************************************/
|
||||
/* static */ int XLlFifo_iWrite_Aligned(XLlFifo *InstancePtr, void *BufPtr,
|
||||
unsigned WordCount)
|
||||
{
|
||||
unsigned WordsRemaining = WordCount;
|
||||
u32 *BufPtrIdx = (u32 *)BufPtr;
|
||||
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_TX,
|
||||
"XLlFifo_iWrite_Aligned: Inst: %p; Buff: %p; Count: %d\n",
|
||||
InstancePtr, BufPtr, WordCount);
|
||||
Xil_AssertNonvoid(InstancePtr);
|
||||
Xil_AssertNonvoid(BufPtr);
|
||||
/* assert bufer is 32 bit aligned */
|
||||
Xil_AssertNonvoid(((unsigned)BufPtr & 0x3) == 0x0);
|
||||
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_TX,
|
||||
"XLlFifo_iWrite_Aligned: WordsRemaining: %d\n",
|
||||
WordsRemaining);
|
||||
while (WordsRemaining) {
|
||||
XLlFifo_TxPutWord(InstancePtr, *BufPtrIdx);
|
||||
BufPtrIdx++;
|
||||
WordsRemaining--;
|
||||
}
|
||||
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_TX,
|
||||
"XLlFifo_iWrite_Aligned: returning SUCCESS\n");
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_CfgInitialize initializes an XPS_ll_Fifo device along with the
|
||||
* <i>InstancePtr</i> that references it.
|
||||
*
|
||||
* @param InstancePtr is a pointer to the Axi Streaming FIFO instance
|
||||
* to be worked on.
|
||||
* @param CfgPtr references the structure holding the hardware
|
||||
* configuration for the Axi Streaming FIFO core to initialize.
|
||||
* @param EffectiveAddr is the device base address in the virtual memory
|
||||
* address space. The caller is responsible for keeping the
|
||||
* address mapping from EffectiveAddr to the device physical base
|
||||
* address unchanged once this function is invoked. Unexpected
|
||||
* errors may occur if the address mapping changes after this
|
||||
* function is called. If address translation is not used,
|
||||
* use Config->BaseAddress for this parameters, passing the
|
||||
* physical address instead.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
******************************************************************************/
|
||||
int XLlFifo_CfgInitialize(XLlFifo *InstancePtr,
|
||||
XLlFifo_Config *Config, u32 EffectiveAddress)
|
||||
{
|
||||
Xil_AssertNonvoid(InstancePtr);
|
||||
|
||||
if(!Config) {
|
||||
return XST_INVALID_PARAM;
|
||||
}
|
||||
|
||||
|
||||
/* Clear instance memory */
|
||||
memset(InstancePtr, 0, sizeof(XLlFifo));
|
||||
|
||||
/*
|
||||
* We don't care about the physical base address, just copy the
|
||||
* processor address over it.
|
||||
*/
|
||||
InstancePtr->BaseAddress = EffectiveAddress;
|
||||
|
||||
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
|
||||
|
||||
InstancePtr->Datainterface = Config->Datainterface;
|
||||
InstancePtr->Axi4BaseAddress = Config->Axi4BaseAddress;
|
||||
if (InstancePtr->Datainterface == 0)
|
||||
InstancePtr->Axi4BaseAddress = EffectiveAddress;
|
||||
|
||||
XLlFifo_TxReset(InstancePtr);
|
||||
XLlFifo_RxReset(InstancePtr);
|
||||
|
||||
/*
|
||||
* Reset the core and generate the external reset by writing to
|
||||
* the Local Link/AXI Streaming Reset Register.
|
||||
*/
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET,
|
||||
XLLF_RDFR_RESET_MASK);
|
||||
|
||||
XStrm_RxInitialize(&(InstancePtr->RxStreamer), FIFO_WIDTH_BYTES,
|
||||
(void *)InstancePtr,
|
||||
(XStrm_XferFnType)XLlFifo_iRead_Aligned,
|
||||
(XStrm_GetLenFnType)XLlFifo_iRxGetLen,
|
||||
(XStrm_GetOccupancyFnType)XLlFifo_iRxOccupancy);
|
||||
|
||||
XStrm_TxInitialize(&(InstancePtr->TxStreamer), FIFO_WIDTH_BYTES,
|
||||
(void *)InstancePtr,
|
||||
(XStrm_XferFnType)XLlFifo_iWrite_Aligned,
|
||||
(XStrm_SetLenFnType)XLlFifo_iTxSetLen,
|
||||
(XStrm_GetVacancyFnType)XLlFifo_iTxVacancy);
|
||||
|
||||
return XST_SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XLlFifo_RxGetWord reads one 32 bit word from the FIFO specified by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* XLlFifo_RxGetLen or XLlFifo_iRxGetLen must be called before calling
|
||||
* XLlFifo_RxGetWord. Otherwise, the hardware will raise an <i>Over Read
|
||||
* Exception</i>.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_RxGetWord returns the 32 bit word read from the FIFO.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr)
|
||||
{
|
||||
return XLlFifo_ReadReg((InstancePtr)->Axi4BaseAddress,
|
||||
XLLF_RDFD_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XLlFifo_TxPutWord writes the 32 bit word, <i>Word</i> to the FIFO specified by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word)
|
||||
*
|
||||
*****************************************************************************/
|
||||
void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word)
|
||||
{
|
||||
|
||||
XLlFifo_WriteReg((InstancePtr)->Axi4BaseAddress,
|
||||
XLLF_TDFD_OFFSET, (Word));
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_Initialize initializes an XPS_ll_Fifo device along with the
|
||||
* <i>InstancePtr</i> that references it.
|
||||
*
|
||||
* @param InstancePtr references the memory instance to be associated with
|
||||
* the FIFO device upon initialization.
|
||||
*
|
||||
* @param BaseAddress is the processor address used to access the
|
||||
* base address of the Fifo device.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
******************************************************************************/
|
||||
void XLlFifo_Initialize(XLlFifo *InstancePtr, u32 BaseAddress)
|
||||
{
|
||||
Xil_AssertVoid(InstancePtr);
|
||||
Xil_AssertVoid(BaseAddress);
|
||||
|
||||
/* Clear instance memory */
|
||||
memset(InstancePtr, 0, sizeof(XLlFifo));
|
||||
|
||||
/*
|
||||
* We don't care about the physical base address, just copy the
|
||||
* processor address over it.
|
||||
*/
|
||||
InstancePtr->BaseAddress = BaseAddress;
|
||||
|
||||
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
|
||||
InstancePtr->Axi4BaseAddress = BaseAddress;
|
||||
|
||||
XLlFifo_TxReset(InstancePtr);
|
||||
XLlFifo_RxReset(InstancePtr);
|
||||
|
||||
/*
|
||||
* Reset the core and generate the external reset by writing to
|
||||
* the Local Link/AXI Streaming Reset Register.
|
||||
*/
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET,
|
||||
XLLF_RDFR_RESET_MASK);
|
||||
|
||||
XStrm_RxInitialize(&(InstancePtr->RxStreamer), FIFO_WIDTH_BYTES,
|
||||
(void *)InstancePtr,
|
||||
(XStrm_XferFnType)XLlFifo_iRead_Aligned,
|
||||
(XStrm_GetLenFnType)XLlFifo_iRxGetLen,
|
||||
(XStrm_GetOccupancyFnType)XLlFifo_iRxOccupancy);
|
||||
|
||||
XStrm_TxInitialize(&(InstancePtr->TxStreamer), FIFO_WIDTH_BYTES,
|
||||
(void *)InstancePtr,
|
||||
(XStrm_XferFnType)XLlFifo_iWrite_Aligned,
|
||||
(XStrm_SetLenFnType)XLlFifo_iTxSetLen,
|
||||
(XStrm_GetVacancyFnType)XLlFifo_iTxVacancy);
|
||||
}
|
||||
709
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.h
Normal file
709
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo.h
Normal file
|
|
@ -0,0 +1,709 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xllfifo.h
|
||||
*
|
||||
* The Xilinx Dual Channel Fifo driver component. This driver supports the
|
||||
* Virtex-5(TM) and Virtex-4(TM) XPS_ll_Fifo and the AxiFifo.
|
||||
*
|
||||
* For a full description of the bridge features, please see the HW spec. This
|
||||
* driver supports the following features:
|
||||
* - Memory mapped access to host interface registers
|
||||
* - API for polled frame transfers
|
||||
* - API for interrupt driven frame transfers
|
||||
* - Virtual memory support
|
||||
* - Full duplex operation
|
||||
*
|
||||
* <h2>Driver Description</h2>
|
||||
*
|
||||
* This driver enables higher layer software to access the XPS_llFifo core
|
||||
* using any alignment in the data buffers.
|
||||
*
|
||||
* This driver supports send and receive channels in the same instance
|
||||
* structure in the same fashion as the hardware core.
|
||||
*
|
||||
* <h2>Initialization</h2>
|
||||
*
|
||||
* An instance of this driver is initialized using a call to Initialize().
|
||||
*
|
||||
* <h2>Usage</h2>
|
||||
*
|
||||
* It is fairly simple to use the API provided by this FIFO driver. The
|
||||
* only somewhat tricky part is that the calling code must correctly call
|
||||
* a couple routines in the right sequence for receive and transmit.
|
||||
*
|
||||
* This sequence is described here. Check the routine functional
|
||||
* descriptions for information on how to use a specific API routine.
|
||||
*
|
||||
* <h3>Receive</h3>
|
||||
*
|
||||
* A frame is received by using the following sequence:<br>
|
||||
* 1) call XLlFifo_RxOccupancy() to check the occupancy count<br>
|
||||
* 2) call XLlFifo_RxGetLen() to get the length of the next incoming frame<br>
|
||||
* 3) call XLlFifo_Read() one or more times to read the number of bytes
|
||||
* reported by XLlFifo_RxGetLen().<br>
|
||||
*
|
||||
* For example:
|
||||
* <pre>
|
||||
* while (XLlFifo_RxOccupancy(&RxInstance)) {
|
||||
* frame_len = XLlFifo_RxGetLen(&RxInstance);
|
||||
* while (frame_len) {
|
||||
* unsigned bytes = min(sizeof(buffer), frame_len);
|
||||
* XLlFifo_Read(&RxInstance, buffer, bytes);
|
||||
* // ********
|
||||
* // do something with buffer here
|
||||
* // ********
|
||||
* frame_len -= bytes;
|
||||
* }
|
||||
* }
|
||||
* </pre>
|
||||
*
|
||||
* This FIFO hardware core does <b>not</b> support a sequence where the
|
||||
* calling code calls RxGetLen() twice in a row and then receive the data
|
||||
* for two frames. Each frame must be read in by calling RxGetLen() just
|
||||
* prior to reading the data.
|
||||
*
|
||||
* <h3>Transmit</h3>
|
||||
* A frame is transmittted by using the following sequence:<br>
|
||||
* 1) call XLlFifo_Write() one or more times to write all the of bytes in
|
||||
* the next frame.<br>
|
||||
* 2) call XLlFifo_TxSetLen() to begin the transmission of frame just
|
||||
* written.<br>
|
||||
*
|
||||
* For example:
|
||||
* <pre>
|
||||
* frame_left = frame_len;
|
||||
* while (frame_left) {
|
||||
* unsigned bytes = min(sizeof(buffer), frame_left);
|
||||
* XLlFifo_Write(&TxInstance, buffer, bytes);
|
||||
* // ********
|
||||
* // do something here to refill buffer
|
||||
* // ********
|
||||
* frame_left -= bytes;
|
||||
* }
|
||||
* XLlFifo_TxSetLen(&RxInstance, frame_len);
|
||||
* </pre>
|
||||
*
|
||||
* This FIFO hardware core does <b>not</b> support a sequence where the
|
||||
* calling code writes the data for two frames and then calls TxSetLen()
|
||||
* twice in a row. Each frame must be written by writting the data for one
|
||||
* frame and then calling TxSetLen().
|
||||
*
|
||||
* <h2>Interrupts</h2>
|
||||
* This driver does not handle interrupts from the FIFO hardware. The
|
||||
* software layer above may make use of the interrupts by setting up its
|
||||
* own handlers for the interrupts.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a jvb 10/12/06 First release
|
||||
* 1.01a sdm 08/22/08 Removed support for static interrupt handlers from the
|
||||
* MDD file
|
||||
* 1.02a jz 12/04/09 Hal phase 1 support
|
||||
* 2.01a asa 09/17/10 Added code for resetting Local Link/AXI Streaming
|
||||
* interface for CR574868
|
||||
* 2.02a asa 12/27/11 Changed the function XStrm_Read in xtreamer.c to reset
|
||||
* HeadIndex to zero when all bytes have been read.
|
||||
* Changed the macro XStrm_IsRxInternalEmpty in file
|
||||
* xtreamer.h to use FrmByteCnt instead of HeadIndex.
|
||||
* When FrmByteCnt is zero, this means all internal buffers
|
||||
* in streamer are empty. Earlier implementation using
|
||||
* HeadIndex was not very clear and could give improper
|
||||
* results for some cases.
|
||||
* Changed the macro XLlFifo_IsRxEmpty in file xllfifo.h
|
||||
* These changes are done to fix the CR 604650.
|
||||
* 2.03a asa 14/08/12 Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
|
||||
* defines for the new registers, and XLLF_INT_TFPF_MASK,
|
||||
* XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
|
||||
* XLLF_INT_RFPE_MASK for the new version of the
|
||||
* AXI4-Stream FIFO core (v2.01a and later)
|
||||
*
|
||||
* 3.00a adk 08/10/13 Added support for AXI4 Datainterface.Changes are
|
||||
* In Xllfifo.c file XLlFifo_RxGetWord,XLlFifo_TxPutword.
|
||||
* In XLlfifo.h file updated XLlfifo structure for
|
||||
* Axi4BaseAddress and for Datainterface type provided
|
||||
* polling and interrupt examples. XLlfifo_IsRxDone Macro
|
||||
* Is added in the XLlfifo.h file for polledmode exmaple.
|
||||
* Added Static initialzation for the driver.
|
||||
* XLlFifo_Initialize is still used to make the driver
|
||||
* backward compatible.
|
||||
* 4.0 adk 19/12/13 Updated as per the New Tcl API's
|
||||
*
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef XLLFIFO_H /* prevent circular inclusions */
|
||||
#define XLLFIFO_H /* by using preprocessor symbols */
|
||||
|
||||
/* force C linkage */
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
/* This order needs to be kept this way to avoid xstatus/xil_types conflict */
|
||||
#include "xstreamer.h"
|
||||
#include "xllfifo_hw.h"
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/**
|
||||
* This typedef defines a run-time instance of an XLlFifo device.
|
||||
*/
|
||||
typedef struct XLlFifo {
|
||||
u32 BaseAddress; /**< BaseAddress is the physical base address of the
|
||||
* device's registers
|
||||
*/
|
||||
|
||||
u32 IsReady; /**< IsReady is non-zero if the driver instance
|
||||
* has been initialized.
|
||||
*/
|
||||
|
||||
u32 Axi4BaseAddress; /**< BaseAddress if the FIFO Data interface is
|
||||
* AXI4 this address should use for FIFO
|
||||
* access
|
||||
*/
|
||||
u32 Datainterface; /**< Data interface of the FIFO. This value is zero
|
||||
* if the Datainterface is AXI4-lite.
|
||||
*/
|
||||
XStrm_RxFifoStreamer RxStreamer; /**< RxStreamer is the byte streamer
|
||||
* instance for the receive channel.
|
||||
*/
|
||||
XStrm_TxFifoStreamer TxStreamer; /**< TxStreamer is the byte streamer
|
||||
* instance for the transmit channel.
|
||||
*/
|
||||
} XLlFifo;
|
||||
|
||||
typedef struct XLlFifo_Config {
|
||||
u32 DeviceId; /**< Deviceid of the AXI FIFO */
|
||||
u32 BaseAddress; /**< Base Address of the AXI FIFO */
|
||||
u32 Axi4BaseAddress; /**< Axi4 interface Base address */
|
||||
u32 Datainterface; /**< Type of Datainterface */
|
||||
}XLlFifo_Config;
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_Reset resets both the Tx and Rx channels and the local link interface
|
||||
* the FIFO specified by <i>InstancePtr</i>. XLlFifo_TxReset resets also sends a
|
||||
* reset pulse to the downstream device (e.g. TEMAC). XLlFifo_Reset drops any
|
||||
* bytes in the FIFO not yet retrieved. XLlFifo_Reset drops any bytes in the FIFO
|
||||
* not yet transmitted.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XLlFifo_Reset(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_Reset(InstancePtr) \
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_LLR_OFFSET, \
|
||||
XLLF_LLR_RESET_MASK)
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_Status returns a bit mask of the interrupt status register (ISR)
|
||||
* for the FIFO specified by <i>InstancePtr</i>. XLlFifo_Status can be used
|
||||
* to query the status of the FIFO without having to have interrupts enabled.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_IntStatus returns a bit mask of the status conditions.
|
||||
* The mask will be a set of bitwise or'd values from the
|
||||
* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 XLlFifo_IntStatus(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_Status(InstancePtr) \
|
||||
XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_IntEnable enables the interrupts specified in <i>Mask</i> for the
|
||||
* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
|
||||
* set to 1 in <i>Mask</i>, will be enabled.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param Mask contains a bit mask of the interrupts to enable. The mask
|
||||
* can be formed using a set of bitwise or'd values from the
|
||||
* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XLlFifo_IntEnable(XLlFifo *InstancePtr, u32 Mask)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_IntEnable(InstancePtr, Mask) \
|
||||
{ \
|
||||
u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
|
||||
XLLF_IER_OFFSET); \
|
||||
Reg |= ((Mask) & XLLF_INT_ALL_MASK); \
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
|
||||
Reg); \
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_IntDisable disables the interrupts specified in <i>Mask</i> for the
|
||||
* FIFO specified by <i>InstancePtr</i>. The corresponding interrupt for each bit
|
||||
* set to 1 in <i>Mask</i>, will be disabled. In other words, XLlFifo_IntDisable
|
||||
* uses the "set a bit to clear it" scheme.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param Mask contains a bit mask of the interrupts to disable. The mask
|
||||
* can be formed using a set of bitwise or'd values from the
|
||||
* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XLlFifo_IntDisable(XLlFifo *InstancePtr, u32 Mask)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_IntDisable(InstancePtr, Mask) \
|
||||
{ \
|
||||
u32 Reg = XLlFifo_ReadReg((InstancePtr)->BaseAddress, \
|
||||
XLLF_IER_OFFSET); \
|
||||
Reg &= ~((Mask) & XLLF_INT_ALL_MASK); \
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET, \
|
||||
Reg); \
|
||||
}
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_IntPending returns a bit mask of the pending interrupts for the
|
||||
* FIFO specified by <i>InstancePtr</i>. Each bit set to 1 in the return value
|
||||
* represents a pending interrupt.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_IntPending returns a bit mask of the interrupts that are
|
||||
* pending. The mask will be a set of bitwise or'd values from the
|
||||
* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 XLlFifo_IntPending(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifdef DEBUG
|
||||
extern u32 _xllfifo_ipie_value;
|
||||
extern u32 _xllfifo_ipis_value;
|
||||
#define XLlFifo_IntPending(InstancePtr) \
|
||||
(_xllfifo_ipie_value = XLlFifo_ReadReg( \
|
||||
(InstancePtr)->BaseAddress, XLLF_IER_OFFSET), \
|
||||
_xllfifo_ipis_value = XLlFifo_ReadReg( \
|
||||
(InstancePtr)->BaseAddress, XLLF_ISR_OFFSET), \
|
||||
(_xllfifo_ipie_value & _xllfifo_ipis_value))
|
||||
#else
|
||||
#define XLlFifo_IntPending(InstancePtr) \
|
||||
(XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_IER_OFFSET) & \
|
||||
XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET))
|
||||
#endif
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_IntClear clears pending interrupts specified in <i>Mask</i> for the
|
||||
* FIFO specified by <i>InstancePtr</i>. The corresponding pending interrupt for
|
||||
* each bit set to 1 in <i>Mask</i>, will be cleared. In other words,
|
||||
* XLlFifo_IntClear uses the "set a bit to clear it" scheme.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param Mask contains a bit mask of the pending interrupts to clear. The
|
||||
* mask can be formed using a set of bitwise or'd values from the
|
||||
* <code>XLLF_INT_*_MASK</code> preprocessor symbols.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XLlFifo_IntClear(XLlFifo *InstancePtr, u32 Mask)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_IntClear(InstancePtr, Mask) \
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET, \
|
||||
((Mask) & XLLF_INT_ALL_MASK))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_RxReset resets the receive channel of the FIFO specified by
|
||||
* <i>InstancePtr</i>. XLlFifo_RxReset drops any bytes in the FIFO not yet
|
||||
* retrieved.
|
||||
*
|
||||
* The calling software may want to test for the completion of the reset by
|
||||
* reading the interrupt status (IS) register and testing for the Rx Reset
|
||||
* complete (RRC) bit.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XLlFifo_RxReset(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_RxReset(InstancePtr) \
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_RDFR_OFFSET, \
|
||||
XLLF_RDFR_RESET_MASK)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_IsRxEmpty returns true if the receive channel of the FIFO, specified
|
||||
* by <i>InstancePtr</i>, is empty.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_IsRxEmpty returns TRUE when the receive channel of the
|
||||
* FIFO is empty. Otherwise, XLlFifo_IsRxEmpty returns FALSE.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* int XLlFifo_IsRxEmpty(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_IsRxEmpty(InstancePtr) \
|
||||
((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDFO_OFFSET) == 0) \
|
||||
? TRUE : FALSE)
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_RxOccupancy returns the number of 32-bit words available (occupancy) to
|
||||
* be read from the receive channel of the FIFO, specified by <i>InstancePtr</i>.
|
||||
*
|
||||
* The xps_ll_fifo core uses the same fifo to store data values and frame length
|
||||
* values. Upon initialization, the XLlFifo_RxOccupancy will give the value of
|
||||
* 1, which means one length value (a reserved fifo location) and no data
|
||||
* values.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_RxOccupancy returns the occupancy count for the specified
|
||||
* packet FIFO.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* C Signature: u32 XLlFifo_RxOccupancy(XLlFifo *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XLlFifo_RxOccupancy(InstancePtr) \
|
||||
XStrm_RxOccupancy(&((InstancePtr)->RxStreamer))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_RxGetLen notifies the hardware that the program is ready to receive
|
||||
* the next frame from the receive channel of the FIFO, specified by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* Note that the program must first call XLlFifo_RxGetLen before pulling data
|
||||
* out of the receive channel of the FIFO with XLlFifo_Read.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_RxGetLen returns the number of bytes available in the next
|
||||
* frame.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* C Signature: u32 XLlFifo_RxGetLen(XLlFifo *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XLlFifo_RxGetLen(InstancePtr) \
|
||||
XStrm_RxGetLen(&((InstancePtr)->RxStreamer))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_Read reads <i>Bytes</i> bytes from the receive channel of the FIFO
|
||||
* referenced by <i>InstancePtr</i> to the block of memory, referenced by
|
||||
* <i>BufPtr</i>.
|
||||
*
|
||||
* Care must be taken to ensure that the number of bytes read with one or more
|
||||
* calls to XLlFifo_Read() does not exceed the number of bytes available given
|
||||
* from the last call to XLlFifo_RxGetLen().
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param BufPtr specifies the memory address to place the data read.
|
||||
*
|
||||
* @param Bytes specifies the number of bytes to read.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* Error handling is handled through hardware exceptions and interrupts.
|
||||
*
|
||||
* C Signature: void XLlFifo_Read(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XLlFifo_Read(InstancePtr, BufPtr, Bytes) \
|
||||
XStrm_Read(&((InstancePtr)->RxStreamer), (BufPtr), (Bytes))
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_TxReset resets the transmit channel of the FIFO specified by
|
||||
* <i>InstancePtr</i>. XLlFifo_TxReset drops any bytes in the FIFO not yet
|
||||
* transmitted.
|
||||
*
|
||||
* The calling software may want to test for the completion of the reset by
|
||||
* reading the interrupt status (IS) register and testing for the Tx Reset
|
||||
* complete (TRC) bit.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XLlFifo_TxReset(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_TxReset(InstancePtr) \
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDFR_OFFSET, \
|
||||
XLLF_TDFR_RESET_MASK)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_IsTxDone returns true if the transmission in the transmit channel
|
||||
* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsTxDone
|
||||
* works only if the TC bit in the IS register is cleared before sending a
|
||||
* frame.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_IsTxDone returns TRUE when the transmit channel of the
|
||||
* FIFO is complete. Otherwise, XLlFifo_IsTxDone returns FALSE.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* int XLlFifo_IsTxDone(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_IsTxDone(InstancePtr) \
|
||||
((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
|
||||
XLLF_INT_TC_MASK) \
|
||||
? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_IsRxDone returns true if the reception in the receive channel
|
||||
* of the FIFO, specified by <i>InstancePtr</i>, is complete. XLlFifo_IsRxDone
|
||||
* works only if the RC bit in the ISR register is cleared before receiving a
|
||||
* frame.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_IsRxDone returns TRUE when the receive channel of the
|
||||
* FIFO is complete. Otherwise, XLlFifo_IsRxDone returns FALSE.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* int XLlFifo_IsRxDone(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_IsRxDone(InstancePtr) \
|
||||
((XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_ISR_OFFSET) & \
|
||||
XLLF_INT_RC_MASK) \
|
||||
? TRUE : FALSE)
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_TxVacancy returns the number of unused 32 bit words available
|
||||
* (vacancy) in the send channel of the FIFO specified by <i>InstancePtr</i>.
|
||||
*
|
||||
* The xps_ll_fifo core uses tXLLF_he same fifo to store data values and frame length
|
||||
* values. Upon initialization, the XLlFifo_TxVacancy will give the value of
|
||||
* FIFO_WIDTH - 1, which means one length value used (a reserved fifo location)
|
||||
* and no data values yet present.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XLlFifo_TxVacancy returns the vacancy count in 32-bit words for
|
||||
* the specified FIFO.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 XLlFifo_TxVacancy(XLlFifo *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XLlFifo_TxVacancy(InstancePtr) \
|
||||
XStrm_TxVacancy(&((InstancePtr)->TxStreamer))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_TxSetLen begins a hardware transfer of <i>Bytes</i> bytes out of the
|
||||
* transmit channel of the FIFO specified by <i>InstancePtr</i>.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param Bytes specifies the frame length in bytes.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* C Signature: void XLlFifo_TxSetLen(XLlFifo *InstancePtr, u32 Bytes)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XLlFifo_TxSetLen(InstancePtr, Bytes) \
|
||||
XStrm_TxSetLen(&((InstancePtr)->TxStreamer), (Bytes))
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_Write writes <i>Bytes</i> bytes of the block of memory, referenced by
|
||||
* <i>BufPtr</i>, to the transmit channel of the FIFO referenced by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* Care must be taken to ensure that the number of bytes written with one or
|
||||
* more calls to XLlFifo_Write() matches the number of bytes given in the next
|
||||
* call to XLlFifo_TxSetLen().
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param BufPtr specifies the memory address of data to write.
|
||||
*
|
||||
* @param Bytes specifies the number of bytes to write.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* Error handling is handled through hardware exceptions and interrupts.
|
||||
*
|
||||
* C Signature: void XLlFifo_Write(XLlFifo *InstancePtr, void *BufPtr, unsigned Bytes)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XLlFifo_Write(InstancePtr, BufPtr, Bytes) \
|
||||
XStrm_Write(&((InstancePtr)->TxStreamer), (BufPtr), (Bytes))
|
||||
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_WriteTdr writes to the Transmit Destination Register (TDR)
|
||||
*
|
||||
* The TDR stores the destination address corresponding to the packet to be
|
||||
* transmitted. When presenting a transmit packet to the AXI4-Stream FIFO core
|
||||
* the following sequence should be followed
|
||||
* - Write the destination address into TDR first,
|
||||
* - Write the packet data to the Transmit Data FIFO next
|
||||
* - Write the length of the packet into the Transmit Length Register.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
* @param Tdest is the Transmit Destination address to be written to TDR.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note C Signature:
|
||||
* void XLlFifo_WriteTdr(XLlFifo *InstancePtr, u32 Tdest);
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XLlFifo_WriteTdr(InstancePtr, Tdest) \
|
||||
XLlFifo_WriteReg((InstancePtr)->BaseAddress, XLLF_TDR_OFFSET, \
|
||||
Tdest & 0xF)
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_ReadTdr returns the contents of the Receive Destination Register(RDR).
|
||||
*
|
||||
* The RDR contains destination address corresponding to the valid packet that
|
||||
* is received. The RDR should only be read when a receive packet is available
|
||||
* for processing (the receive occupancy is not zero).
|
||||
* Once the RDR is read, the receive packet data should be read from the receive
|
||||
* data FIFO before the RDR is read again. The RDR values are stored in the
|
||||
* receive data FIFO by the AXI4-Stream FIFO core with the data of each packet.
|
||||
* The RDR value for the subsequent packet to be processed is moved to the RDR
|
||||
* when the previous RDR value has been read.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return The Receive Destination address read from the RDR.
|
||||
*
|
||||
* @note C Signature:
|
||||
* u32 XLlFifo_ReadRdr(XLlFifo *InstancePtr)
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XLlFifo_ReadRdr(InstancePtr) \
|
||||
XLlFifo_ReadReg((InstancePtr)->BaseAddress, XLLF_RDR_OFFSET)
|
||||
|
||||
/************************** Function Prototypes ******************************/
|
||||
/*
|
||||
* Initialization functions xllfifo.c
|
||||
*/
|
||||
int XLlFifo_CfgInitialize(XLlFifo *InstancePtr,
|
||||
XLlFifo_Config *Config, u32 EffectiveAddress);
|
||||
void XLlFifo_Initialize(XLlFifo *InstancePtr, u32 BaseAddress);
|
||||
XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId);
|
||||
u32 XLlFifo_iRxOccupancy(XLlFifo *InstancePtr);
|
||||
u32 XLlFifo_iRxGetLen(XLlFifo *InstancePtr);
|
||||
u32 XLlFifo_iTxVacancy(XLlFifo *InstancePtr);
|
||||
void XLlFifo_iTxSetLen(XLlFifo *InstancePtr, u32 Bytes);
|
||||
u32 XLlFifo_RxGetWord(XLlFifo *InstancePtr);
|
||||
void XLlFifo_TxPutWord(XLlFifo *InstancePtr, u32 Word);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* XLLFIFO_H end of preprocessor protection symbols */
|
||||
66
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_g.c
Normal file
66
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_g.c
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xtrafgen_g.c
|
||||
*
|
||||
* Provide a template for user to define their own hardware settings.
|
||||
*
|
||||
* If using XPS, this file will be automatically generated.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 3.00a adk 9/10/2013 initial release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xllfifo.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
XLlFifo_Config XLlFifo_ConfigTable[] =
|
||||
{
|
||||
{
|
||||
XPAR_AXI_FIFO_MM_S_1_DEVICE_ID,
|
||||
XPAR_AXI_FIFO_MM_S_1_BASEADDR,
|
||||
XPAR_AXI_FIFO_MM_S_1_AXI4_BASEADDR,
|
||||
XPAR_AXI_FIFO_MM_S_1_DATA_INTERFACE_TYPE
|
||||
}
|
||||
};
|
||||
237
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h
Normal file
237
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_hw.h
Normal file
|
|
@ -0,0 +1,237 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xllfifo_hw.h
|
||||
*
|
||||
* This header file contains identifiers and low-level driver functions (or
|
||||
* macros) that can be used to access the xps_ll_fifo core.
|
||||
* High-level driver functions are defined in xpfifo.h.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a jvb 10/16/06 First release.
|
||||
* 1.02a jz 12/04/09 Hal phase 1 support
|
||||
* 2.00a hbm 01/20/10 Hal phase 1 support, bump up major release
|
||||
* 2.03a asa 14/08/12 Added XLLF_TDR_OFFSET, XLLF_RDR_OFFSET
|
||||
* defines for the new registers, and XLLF_INT_TFPF_MASK,
|
||||
* XLLF_INT_TFPE_MASK, XLLF_INT_RFPF_MASK and
|
||||
* XLLF_INT_RFPE_MASK for the new version of the
|
||||
* AXI4-Stream FIFO core (v2.01a and later)
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef XLLFIFO_HW_H /* prevent circular inclusions */
|
||||
#define XLLFIFO_HW_H /* by using protection macros */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xdebug.h"
|
||||
#include "xil_io.h"
|
||||
#include "xil_types.h"
|
||||
|
||||
/************************** Constant Definitions *****************************/
|
||||
|
||||
/* Register offset definitions. Unless otherwise noted, register access is
|
||||
* 32 bit.
|
||||
*/
|
||||
|
||||
/** @name Registers
|
||||
* @{
|
||||
*/
|
||||
#define XLLF_ISR_OFFSET 0x00000000 /**< Interrupt Status */
|
||||
#define XLLF_IER_OFFSET 0x00000004 /**< Interrupt Enable */
|
||||
|
||||
#define XLLF_TDFR_OFFSET 0x00000008 /**< Transmit Reset */
|
||||
#define XLLF_TDFV_OFFSET 0x0000000c /**< Transmit Vacancy */
|
||||
#define XLLF_TDFD_OFFSET 0x00000010 /**< Transmit Data */
|
||||
#define XLLF_TLF_OFFSET 0x00000014 /**< Transmit Length */
|
||||
|
||||
#define XLLF_RDFR_OFFSET 0x00000018 /**< Receive Reset */
|
||||
#define XLLF_RDFO_OFFSET 0x0000001c /**< Receive Occupancy */
|
||||
#define XLLF_RDFD_OFFSET 0x00000020 /**< Receive Data */
|
||||
#define XLLF_RLF_OFFSET 0x00000024 /**< Receive Length */
|
||||
#define XLLF_LLR_OFFSET 0x00000028 /**< Local Link Reset */
|
||||
#define XLLF_TDR_OFFSET 0x0000002C /**< Transmit Destination */
|
||||
#define XLLF_RDR_OFFSET 0x00000030 /**< Receive Destination */
|
||||
|
||||
/*@}*/
|
||||
|
||||
/* Register masks. The following constants define bit locations of various
|
||||
* control bits in the registers. Constants are not defined for those registers
|
||||
* that have a single bit field representing all 32 bits. For further
|
||||
* information on the meaning of the various bit masks, refer to the HW spec.
|
||||
*/
|
||||
|
||||
/** @name Interrupt bits
|
||||
* These bits are associated with the XLLF_IER_OFFSET and XLLF_ISR_OFFSET
|
||||
* registers.
|
||||
* @{
|
||||
*/
|
||||
#define XLLF_INT_RPURE_MASK 0x80000000 /**< Receive under-read */
|
||||
#define XLLF_INT_RPORE_MASK 0x40000000 /**< Receive over-read */
|
||||
#define XLLF_INT_RPUE_MASK 0x20000000 /**< Receive underrun (empty) */
|
||||
#define XLLF_INT_TPOE_MASK 0x10000000 /**< Transmit overrun */
|
||||
#define XLLF_INT_TC_MASK 0x08000000 /**< Transmit complete */
|
||||
#define XLLF_INT_RC_MASK 0x04000000 /**< Receive complete */
|
||||
#define XLLF_INT_TSE_MASK 0x02000000 /**< Transmit length mismatch */
|
||||
#define XLLF_INT_TRC_MASK 0x01000000 /**< Transmit reset complete */
|
||||
#define XLLF_INT_RRC_MASK 0x00800000 /**< Receive reset complete */
|
||||
#define XLLF_INT_TFPF_MASK 0x00400000 /**< Tx FIFO Programmable Full,
|
||||
* AXI FIFO MM2S Only */
|
||||
#define XLLF_INT_TFPE_MASK 0x00200000 /**< Tx FIFO Programmable Empty
|
||||
* AXI FIFO MM2S Only */
|
||||
#define XLLF_INT_RFPF_MASK 0x00100000 /**< Rx FIFO Programmable Full
|
||||
* AXI FIFO MM2S Only */
|
||||
#define XLLF_INT_RFPE_MASK 0x00080000 /**< Rx FIFO Programmable Empty
|
||||
* AXI FIFO MM2S Only */
|
||||
#define XLLF_INT_ALL_MASK 0xfff80000 /**< All the ints */
|
||||
#define XLLF_INT_ERROR_MASK 0xf2000000 /**< Error status ints */
|
||||
#define XLLF_INT_RXERROR_MASK 0xe0000000 /**< Receive Error status ints */
|
||||
#define XLLF_INT_TXERROR_MASK 0x12000000 /**< Transmit Error status ints */
|
||||
/*@}*/
|
||||
|
||||
/** @name Reset register values
|
||||
* These bits are associated with the XLLF_TDFR_OFFSET and XLLF_RDFR_OFFSET
|
||||
* reset registers.
|
||||
* @{
|
||||
*/
|
||||
#define XLLF_RDFR_RESET_MASK 0x000000a5 /**< receive reset value */
|
||||
#define XLLF_TDFR_RESET_MASK 0x000000a5 /**< Transmit reset value */
|
||||
#define XLLF_LLR_RESET_MASK 0x000000a5 /**< Local Link reset value */
|
||||
/*@}*/
|
||||
|
||||
/**************************** Type Definitions *******************************/
|
||||
|
||||
/***************** Macros (Inline Functions) Definitions *********************/
|
||||
|
||||
/**** debug macros ****/
|
||||
#define XLlFifo_reg_name(RegOffset) \
|
||||
(((RegOffset) == XLLF_ISR_OFFSET) ? "ISR": \
|
||||
((RegOffset) == XLLF_IER_OFFSET) ? "IER": \
|
||||
((RegOffset) == XLLF_TDFR_OFFSET) ? "TDFR {tx reset}": \
|
||||
((RegOffset) == XLLF_TDFV_OFFSET) ? "TDFV {tx vacancy}": \
|
||||
((RegOffset) == XLLF_TDFD_OFFSET) ? "TDFD {tx data}": \
|
||||
((RegOffset) == XLLF_TLF_OFFSET) ? "TLF {tx length}": \
|
||||
((RegOffset) == XLLF_RDFR_OFFSET) ? "RDFR {rx reset}": \
|
||||
((RegOffset) == XLLF_RDFO_OFFSET) ? "RDFO {rx occupancy}": \
|
||||
((RegOffset) == XLLF_RDFD_OFFSET) ? "RDFD {rx data}": \
|
||||
((RegOffset) == XLLF_RLF_OFFSET) ? "RLF {rx length}": \
|
||||
"unknown")
|
||||
|
||||
#define XLlFifo_print_reg_o(BaseAddress, RegOffset, Value) \
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_REG, "0x%08x -> %s(0x%08x)\n", (Value), \
|
||||
XLlFifo_reg_name(RegOffset), \
|
||||
(RegOffset) + (BaseAddress))
|
||||
|
||||
#define XLlFifo_print_reg_i(BaseAddress, RegOffset, Value) \
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_REG, "%s(0x%08x) -> 0x%08x\n", \
|
||||
XLlFifo_reg_name(RegOffset), \
|
||||
(RegOffset) + (BaseAddress), (Value))
|
||||
/**** end debug macros ****/
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_ReadReg returns the value of the register at the offet,
|
||||
* <i>RegOffset</i>, from the memory mapped base address, <i>BaseAddress</i>.
|
||||
*
|
||||
* @param BaseAddress specifies the base address of the device.
|
||||
*
|
||||
* @param RegOffset specifies the offset from BaseAddress.
|
||||
*
|
||||
* @return XLlFifo_ReadReg returns the value of the specified register.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* u32 XLlFifo_ReadReg(u32 BaseAddress, u32 RegOffset)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifdef DEBUG
|
||||
extern u32 _xllfifo_rr_value;
|
||||
#define XLlFifo_ReadReg(BaseAddress, RegOffset) \
|
||||
((((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \
|
||||
"XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \
|
||||
(RegOffset)) : 0), \
|
||||
_xllfifo_rr_value = Xil_In32((BaseAddress) + (RegOffset)), \
|
||||
XLlFifo_print_reg_i((BaseAddress), (RegOffset), _xllfifo_rr_value), \
|
||||
_xllfifo_rr_value)
|
||||
#else
|
||||
#define XLlFifo_ReadReg(BaseAddress, RegOffset) \
|
||||
(Xil_In32((BaseAddress) + (RegOffset)))
|
||||
#endif
|
||||
|
||||
/****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* XLlFifo_WriteReg writes the value, <i>Value</i>, to the register at the
|
||||
* offet, <i>RegOffset</i>, from the memory mapped base address,
|
||||
* <i>BaseAddress</i>.
|
||||
*
|
||||
* @param BaseAddress specifies the base address of the device.
|
||||
*
|
||||
* @param RegOffset specifies the offset from BaseAddress.
|
||||
*
|
||||
* @param Value is value to write to the register.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* void XLlFifo_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Value)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifdef DEBUG
|
||||
#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \
|
||||
(((RegOffset) > 0x24) ? xdbg_printf(XDBG_DEBUG_ERROR, \
|
||||
"XLlFifo_WriteReg: Woah! wrong reg addr: 0x%08x\n", \
|
||||
(RegOffset)) : 0), \
|
||||
XLlFifo_print_reg_o((BaseAddress), (RegOffset), (Value)), \
|
||||
(Xil_Out32((BaseAddress) + (RegOffset), (Value)))
|
||||
#else
|
||||
#define XLlFifo_WriteReg(BaseAddress, RegOffset, Value) \
|
||||
((Xil_Out32((BaseAddress) + (RegOffset), (Value))))
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* XLLFIFO_HW_H end of protection macro */
|
||||
85
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_sinit.c
Normal file
85
XilinxProcessorIPLib/drivers/llfifo/src/xllfifo_sinit.c
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2013 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
*
|
||||
* @file xtrafgen_sinit.c
|
||||
*
|
||||
* This file contains static initialzation functionality for Axi Streaming FIFO
|
||||
* driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 3.00a adk 9/10/2013 initial release
|
||||
* </pre>
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xparameters.h"
|
||||
#include "xllfifo.h"
|
||||
|
||||
/*****************************************************************************/
|
||||
/**
|
||||
* Look up the hardware configuration for a device instance
|
||||
*
|
||||
* @param DeviceId is the unique device ID of the device to lookup for
|
||||
*
|
||||
* @return
|
||||
* The configuration structure for the device. If the device ID is
|
||||
* not found,a NULL pointer is returned.
|
||||
*
|
||||
* @note None
|
||||
*
|
||||
******************************************************************************/
|
||||
XLlFifo_Config *XLlFfio_LookupConfig(u32 DeviceId)
|
||||
{
|
||||
extern XLlFifo_Config XLlFifo_ConfigTable[];
|
||||
XLlFifo_Config *CfgPtr;
|
||||
u32 Index;
|
||||
|
||||
CfgPtr = NULL;
|
||||
|
||||
for (Index = 0; Index < XPAR_XLLFIFO_NUM_INSTANCES; Index++) {
|
||||
if (XLlFifo_ConfigTable[Index].DeviceId == DeviceId) {
|
||||
|
||||
CfgPtr = &XLlFifo_ConfigTable[Index];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return CfgPtr;
|
||||
}
|
||||
513
XilinxProcessorIPLib/drivers/llfifo/src/xstreamer.c
Normal file
513
XilinxProcessorIPLib/drivers/llfifo/src/xstreamer.c
Normal file
|
|
@ -0,0 +1,513 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
* @file xstreamer.c
|
||||
*
|
||||
* See xtreamer.h for a description on how to use this driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a jvb 10/13/06 First release - based on Robert McGee's streaming packet
|
||||
* fifo driver.
|
||||
* 1.02a jz 12/04/09 Hal phase 1 support
|
||||
* 2.00a hbm 01/20/10 Hal phase 1 support, bump up major release
|
||||
* 2.02a asa 12/28/11 The function XStrm_Read is changed to reset HeadIndex
|
||||
* to zero when all the bytes are read.
|
||||
* </pre>
|
||||
******************************************************************************/
|
||||
|
||||
/***************************** Include Files *********************************/
|
||||
|
||||
#include "xstreamer.h"
|
||||
#include "xil_assert.h"
|
||||
|
||||
/*
|
||||
* Implementation Notes
|
||||
*
|
||||
* --- Receive ---
|
||||
*
|
||||
* The basic algorithm for receiving bytes through this byte streamer copies a
|
||||
* fifo key-hole width chunk from the fifo into a holding buffer and then doles
|
||||
* out the bytes from the holding buffer. In some cases, when the buffer given
|
||||
* happens to already be aligned in memory, this algorithm will bypass the
|
||||
* holding buffer.
|
||||
*
|
||||
* Here is a picture to depict this process:
|
||||
*
|
||||
* Initial state: holding buffer
|
||||
* +--------------+
|
||||
* | <empty> |
|
||||
* +--------------+
|
||||
* ^
|
||||
* |
|
||||
* index
|
||||
*
|
||||
* during XStrm_Read():
|
||||
* first holding buffer fill: holding buffer
|
||||
* +--------------+
|
||||
* |////<full>////|
|
||||
* +--------------+
|
||||
* ^
|
||||
* |
|
||||
* index
|
||||
*
|
||||
* first holding buffer read: holding buffer
|
||||
* read unread
|
||||
* +--------------+
|
||||
* | |///////|
|
||||
* +--------------+
|
||||
* ^
|
||||
* |
|
||||
* index
|
||||
*
|
||||
* ...
|
||||
*
|
||||
* last holding buffer read: holding buffer
|
||||
* +--------------+
|
||||
* | <empty> |
|
||||
* +--------------+
|
||||
* ^
|
||||
* |
|
||||
* index
|
||||
*
|
||||
* repeat this process ^^^
|
||||
*
|
||||
*
|
||||
* --- Transmit ---
|
||||
*
|
||||
* The basic algorithm for transmitting bytes through this byte streamer copies
|
||||
* bytes into a holding buffer and then writes the holding buffer into the fifo
|
||||
* when it is full. In some cases, when the buffer given happens to already be
|
||||
* aligned in memory, this algorithm will bypass the holding buffer.
|
||||
*
|
||||
* Here is a picture to depict this process:
|
||||
*
|
||||
* Initial state: holding buffer
|
||||
* +--------------+
|
||||
* | <empty> |
|
||||
* +--------------+
|
||||
* ^
|
||||
* |
|
||||
* index
|
||||
*
|
||||
* during XStrm_Write():
|
||||
* first holding buffer write: holding buffer
|
||||
* writen empty
|
||||
* +--------------+
|
||||
* |//////| |
|
||||
* +--------------+
|
||||
* ^
|
||||
* |
|
||||
* index
|
||||
*
|
||||
* ...
|
||||
* last holding buffer write: holding buffer
|
||||
* +--------------+
|
||||
* |////<full>////|
|
||||
* +--------------+
|
||||
* ^
|
||||
* |
|
||||
* index
|
||||
*
|
||||
* holding buffer flush: holding buffer
|
||||
* +--------------+
|
||||
* | <empty> |
|
||||
* +--------------+
|
||||
* ^
|
||||
* |
|
||||
* index
|
||||
*
|
||||
* repeat this process ^^^
|
||||
*/
|
||||
|
||||
#ifndef min
|
||||
#define min(x, y) (((x) < (y)) ? (x) : (y))
|
||||
#endif
|
||||
|
||||
xdbg_stmnt(u32 _xstrm_ro_value;)
|
||||
xdbg_stmnt(u32 _xstrm_buffered;)
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_RxInitialize initializes the XStrm_RxFifoStreamer object referenced by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* @param InstancePtr references the tx streamer on which to operate.
|
||||
*
|
||||
* @param FifoWidth specifies the FIFO keyhole size in bytes.
|
||||
*
|
||||
* @param FifoInstance references the FIFO driver instance that this streamer
|
||||
* object should use to transfer data into the the actual fifo.
|
||||
*
|
||||
* @param ReadFn specifies a routine to use to read data from the actual
|
||||
* FIFO. It is assumed that this read routine will handle only reads
|
||||
* from an aligned buffer. (Otherwise, why are we using this streamer
|
||||
* driver?)
|
||||
*
|
||||
* @param GetLenFn specifies a routine to use to initiate a receive on the
|
||||
* actual FIFO.
|
||||
*
|
||||
* @param GetOccupancyFn specifies a routine to use to retrieve the occupancy
|
||||
* in the actual FIFO. The true occupancy value needs to come through
|
||||
* this streamer driver becuase it holds some of the bytes.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
******************************************************************************/
|
||||
void XStrm_RxInitialize(XStrm_RxFifoStreamer *InstancePtr, unsigned FifoWidth,
|
||||
void *FifoInstance, XStrm_XferFnType ReadFn,
|
||||
XStrm_GetLenFnType GetLenFn,
|
||||
XStrm_GetOccupancyFnType GetOccupancyFn)
|
||||
{
|
||||
/* Verify arguments */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
|
||||
InstancePtr->HeadIndex = FifoWidth;
|
||||
InstancePtr->FifoWidth = FifoWidth;
|
||||
InstancePtr->FifoInstance = FifoInstance;
|
||||
InstancePtr->ReadFn = ReadFn;
|
||||
InstancePtr->GetLenFn = GetLenFn;
|
||||
InstancePtr->GetOccupancyFn = GetOccupancyFn;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_TxInitialize initializes the XStrm_TxFifoStreamer object referenced by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* @param InstancePtr references the tx streamer on which to operate.
|
||||
*
|
||||
* @param FifoWidth specifies the FIFO keyhole size in bytes.
|
||||
*
|
||||
* @param FifoInstance references the FIFO driver instance that this streamer
|
||||
* object should use to transfer data into the the actual fifo.
|
||||
*
|
||||
* @param WriteFn specifies a routine to use to write data into the actual
|
||||
* FIFO. It is assumed that this write routine will handle only writes
|
||||
* from an aligned buffer. (Otherwise, why are we using this streamer
|
||||
* driver?)
|
||||
*
|
||||
* @param SetLenFn specifies a routine to use to initiate a transmit on the
|
||||
* actual FIFO.
|
||||
*
|
||||
* @param GetVacancyFn specifies a routine to use to retrieve the vacancy in
|
||||
* the actual FIFO. The true vacancy value needs to come through this
|
||||
* streamer driver becuase it holds some of the bytes.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
******************************************************************************/
|
||||
void XStrm_TxInitialize(XStrm_TxFifoStreamer *InstancePtr, unsigned FifoWidth,
|
||||
void *FifoInstance, XStrm_XferFnType WriteFn,
|
||||
XStrm_SetLenFnType SetLenFn,
|
||||
XStrm_GetVacancyFnType GetVacancyFn)
|
||||
{
|
||||
/* Verify arguments */
|
||||
Xil_AssertVoid(InstancePtr != NULL);
|
||||
|
||||
InstancePtr->TailIndex = 0;
|
||||
InstancePtr->FifoWidth = FifoWidth;
|
||||
InstancePtr->FifoInstance = FifoInstance;
|
||||
InstancePtr->WriteFn = WriteFn;
|
||||
InstancePtr->SetLenFn = SetLenFn;
|
||||
InstancePtr->GetVacancyFn = GetVacancyFn;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_RxGetLen notifies the hardware that the program is ready to receive the
|
||||
* next frame from the receive channel of the FIFO, specified by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* Note that the program must first call XStrm_RxGetLen before pulling data
|
||||
* out of the receive channel of the FIFO with XStrm_Read.
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @return XStrm_RxGetLen returns the number of bytes available in the next
|
||||
* frame.
|
||||
*
|
||||
******************************************************************************/
|
||||
u32 XStrm_RxGetLen(XStrm_RxFifoStreamer *InstancePtr)
|
||||
{
|
||||
u32 len;
|
||||
|
||||
InstancePtr->HeadIndex = InstancePtr->FifoWidth;
|
||||
len = (*InstancePtr->GetLenFn)(InstancePtr->FifoInstance);
|
||||
InstancePtr->FrmByteCnt = len;
|
||||
return len;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_Read reads <i>Bytes</i> bytes from the FIFO specified by
|
||||
* <i>InstancePtr</i> to the block of memory, referenced by <i>BufPtr</i>.
|
||||
*
|
||||
* Care must be taken to ensure that the number of bytes read with one or more
|
||||
* calls to XStrm_Read() does not exceed the number of bytes available given
|
||||
* from the last call to XStrm_RxGetLen().
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param BufPtr specifies the memory address to place the data read.
|
||||
*
|
||||
* @param Bytes specifies the number of bytes to read.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
******************************************************************************/
|
||||
void XStrm_Read(XStrm_RxFifoStreamer *InstancePtr, void *BufPtr,
|
||||
unsigned Bytes)
|
||||
{
|
||||
u8 *DestPtr = (u8 *) BufPtr;
|
||||
unsigned BytesRemaining = Bytes;
|
||||
unsigned FifoWordsToXfer;
|
||||
unsigned PartialBytes;
|
||||
unsigned i;
|
||||
|
||||
while (BytesRemaining) {
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "XStrm_Read: BytesRemaining: %d\n", BytesRemaining);
|
||||
/* Case 1: There are bytes in the holding buffer
|
||||
*
|
||||
* 1) Read the bytes from the holding buffer to the target buffer.
|
||||
* 2) Loop back around and handle the rest of the transfer.
|
||||
*/
|
||||
if (InstancePtr->HeadIndex != InstancePtr->FifoWidth) {
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "XStrm_Read: Case 1: InstancePtr->HeadIndex [%d] != InstancePtr->FifoWidth [%d]\n",
|
||||
InstancePtr->HeadIndex, InstancePtr->FifoWidth);
|
||||
i = InstancePtr->HeadIndex;
|
||||
|
||||
PartialBytes = min(BytesRemaining,
|
||||
InstancePtr->FifoWidth -
|
||||
InstancePtr->HeadIndex);
|
||||
InstancePtr->HeadIndex += PartialBytes;
|
||||
BytesRemaining -= PartialBytes;
|
||||
InstancePtr->FrmByteCnt -= PartialBytes;
|
||||
while (PartialBytes--) {
|
||||
*DestPtr = InstancePtr->AlignedBuffer.bytes[i];
|
||||
i++;
|
||||
DestPtr++;
|
||||
}
|
||||
}
|
||||
/* Case 2: There are no more bytes in the holding buffer and
|
||||
* the target buffer is 32 bit aligned and
|
||||
* the number of bytes remaining to transfer is greater
|
||||
* than or equal to the fifo width.
|
||||
*
|
||||
* 1) We can go fast by reading a long string of fifo words right out
|
||||
* of the fifo into the target buffer.
|
||||
* 2) Loop back around to transfer the last few bytes.
|
||||
*/
|
||||
else if ((((unsigned)DestPtr & 3) == 0) &&
|
||||
(BytesRemaining >= InstancePtr->FifoWidth)) {
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "XStrm_Read: Case 2: DestPtr: %p, BytesRemaining: %d, InstancePtr->FifoWidth: %d\n",
|
||||
DestPtr, BytesRemaining, InstancePtr->FifoWidth);
|
||||
FifoWordsToXfer =
|
||||
BytesRemaining / InstancePtr->FifoWidth;
|
||||
|
||||
(*(InstancePtr->ReadFn)) (InstancePtr->FifoInstance,
|
||||
DestPtr, FifoWordsToXfer);
|
||||
DestPtr += FifoWordsToXfer * InstancePtr->FifoWidth;
|
||||
BytesRemaining -=
|
||||
FifoWordsToXfer * InstancePtr->FifoWidth;
|
||||
InstancePtr->FrmByteCnt -=
|
||||
FifoWordsToXfer * InstancePtr->FifoWidth;
|
||||
}
|
||||
/* Case 3: There are no more bytes in the holding buffer and
|
||||
* the number of bytes remaining to transfer is less than
|
||||
* the fifo width or
|
||||
* things just don't line up.
|
||||
*
|
||||
* 1) Fill the holding buffer.
|
||||
* 2) Loop back around and handle the rest of the transfer.
|
||||
*/
|
||||
else {
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "XStrm_Read: Case 3\n");
|
||||
/*
|
||||
* At the tail end, read one fifo word into the local holding
|
||||
* buffer and loop back around to take care of the transfer.
|
||||
*/
|
||||
(*InstancePtr->ReadFn) (InstancePtr->FifoInstance,
|
||||
&(InstancePtr->AlignedBuffer.
|
||||
bytes[0]), 1);
|
||||
InstancePtr->HeadIndex = 0;
|
||||
}
|
||||
}
|
||||
if ((InstancePtr->FrmByteCnt) == 0) {
|
||||
InstancePtr->HeadIndex = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_TxSetLen flushes to the FIFO, specified by <i>InstancePtr</i>, any
|
||||
* bytes remaining in internal buffers and begins a hardware transfer of data
|
||||
* out of the transmit channel of the FIFO. <i>Bytes</i> specifies the number
|
||||
* of bytes in the frame to transmit.
|
||||
*
|
||||
* @param InstancePtr references the FIFO Streamer on which to operate.
|
||||
*
|
||||
* @param Bytes specifies the frame length in bytes.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
******************************************************************************/
|
||||
void XStrm_TxSetLen(XStrm_TxFifoStreamer *InstancePtr, u32 Bytes)
|
||||
{
|
||||
/*
|
||||
* First flush what's in the holding buffer
|
||||
*/
|
||||
if (InstancePtr->TailIndex != 0) {
|
||||
(*InstancePtr->WriteFn) (InstancePtr->FifoInstance,
|
||||
&(InstancePtr->AlignedBuffer.bytes[0]),
|
||||
1);
|
||||
InstancePtr->TailIndex = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Kick off the hw write
|
||||
*/
|
||||
(*(InstancePtr)->SetLenFn) (InstancePtr->FifoInstance, Bytes);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_Write writes <i>Bytes</i> bytes of the block of memory, referenced by
|
||||
* <i>BufPtr</i>, to the transmit channel of the FIFO referenced by
|
||||
* <i>InstancePtr</i>.
|
||||
*
|
||||
* Care must be taken to ensure that the number of bytes written with one or
|
||||
* more calls to XStrm_Write() matches the number of bytes given in the next
|
||||
* call to XStrm_TxSetLen().
|
||||
*
|
||||
* @param InstancePtr references the FIFO on which to operate.
|
||||
*
|
||||
* @param BufPtr specifies the memory address of data to write.
|
||||
*
|
||||
* @param Bytes specifies the number of bytes to write.
|
||||
*
|
||||
* @return N/A
|
||||
*
|
||||
******************************************************************************/
|
||||
void XStrm_Write(XStrm_TxFifoStreamer *InstancePtr, void *BufPtr,
|
||||
unsigned Bytes)
|
||||
{
|
||||
u8 *SrcPtr = (u8 *) BufPtr;
|
||||
unsigned BytesRemaining = Bytes;
|
||||
unsigned FifoWordsToXfer;
|
||||
unsigned PartialBytes;
|
||||
unsigned i;
|
||||
|
||||
while (BytesRemaining) {
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_TX,
|
||||
"XStrm_Write: BytesRemaining: %d\n",
|
||||
BytesRemaining);
|
||||
/* Case 1: The holding buffer is full
|
||||
*
|
||||
* 1) Write it to the fifo.
|
||||
* 2) Fall through to transfer more bytes in this iteration.
|
||||
*/
|
||||
if (InstancePtr->TailIndex == InstancePtr->FifoWidth) {
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_TX,
|
||||
"XStrm_Write: (case 1) TailIndex: %d; FifoWidth: %d; WriteFn: %p\n",
|
||||
InstancePtr->TailIndex, InstancePtr->FifoWidth,
|
||||
InstancePtr->WriteFn);
|
||||
(*InstancePtr->WriteFn) (InstancePtr->FifoInstance,
|
||||
&(InstancePtr->AlignedBuffer.
|
||||
bytes[0]), 1);
|
||||
InstancePtr->TailIndex = 0;
|
||||
}
|
||||
/* Case 2: There are no bytes in the holding buffer and
|
||||
* the target buffer is 32 bit aligned and
|
||||
* the number of bytes remaining to transfer is greater
|
||||
* than or equal to the fifo width.
|
||||
*
|
||||
* 1) We can go fast by writing a long string of fifo words right out
|
||||
* of the source buffer into the fifo.
|
||||
* 2) Loop back around to transfer the last few bytes.
|
||||
*/
|
||||
if ((InstancePtr->TailIndex == 0) &&
|
||||
(BytesRemaining >= InstancePtr->FifoWidth) &&
|
||||
(((unsigned)SrcPtr & 3) == 0)) {
|
||||
FifoWordsToXfer =
|
||||
BytesRemaining / InstancePtr->FifoWidth;
|
||||
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_TX, "XStrm_Write: (case 2) TailIndex: %d; BytesRemaining: %d; FifoWidth: %d; SrcPtr: %p;\n InstancePtr: %p; WriteFn: %p ,\nFifoWordsToXfer: %d (BytesRemaining: %d)\n",
|
||||
InstancePtr->TailIndex, BytesRemaining,
|
||||
InstancePtr->FifoWidth, SrcPtr,
|
||||
InstancePtr, InstancePtr->WriteFn,
|
||||
FifoWordsToXfer,
|
||||
BytesRemaining);
|
||||
|
||||
(*InstancePtr->WriteFn) (InstancePtr->FifoInstance,
|
||||
SrcPtr, FifoWordsToXfer);
|
||||
SrcPtr += FifoWordsToXfer * InstancePtr->FifoWidth;
|
||||
BytesRemaining -=
|
||||
FifoWordsToXfer * InstancePtr->FifoWidth;
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_TX, "XStrm_Write: (end case 2) TailIndex: %d; BytesRemaining: %d; SrcPtr: %p\n",
|
||||
InstancePtr->TailIndex, BytesRemaining, SrcPtr);
|
||||
}
|
||||
/* Case 3: The alignment of the "galaxies" didn't occur in
|
||||
* Case 2 above, so we must pump the bytes through the
|
||||
* holding buffer.
|
||||
*
|
||||
* 1) Write bytes from the source buffer to the holding buffer
|
||||
* 2) Loop back around and handle the rest of the transfer.
|
||||
*/
|
||||
else {
|
||||
i = InstancePtr->TailIndex;
|
||||
|
||||
PartialBytes =
|
||||
min(BytesRemaining,
|
||||
InstancePtr->FifoWidth -
|
||||
InstancePtr->TailIndex);
|
||||
BytesRemaining -= PartialBytes;
|
||||
InstancePtr->TailIndex += PartialBytes;
|
||||
while (PartialBytes--) {
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_TX, "XStrm_Write: (case 3) PartialBytes: %d\n",
|
||||
PartialBytes);
|
||||
InstancePtr->AlignedBuffer.bytes[i] = *SrcPtr;
|
||||
i++;
|
||||
SrcPtr++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
330
XilinxProcessorIPLib/drivers/llfifo/src/xstreamer.h
Normal file
330
XilinxProcessorIPLib/drivers/llfifo/src/xstreamer.h
Normal file
|
|
@ -0,0 +1,330 @@
|
|||
/******************************************************************************
|
||||
*
|
||||
* Copyright (C) 2005 - 2014 Xilinx, Inc. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* Use of the Software is limited solely to applications:
|
||||
* (a) running on a Xilinx device, or
|
||||
* (b) that interact with a Xilinx device through a bus or interconnect.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
|
||||
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
* SOFTWARE.
|
||||
*
|
||||
* Except as contained in this notice, the name of the Xilinx shall not be used
|
||||
* in advertising or otherwise to promote the sale, use or other dealings in
|
||||
* this Software without prior written authorization from Xilinx.
|
||||
*
|
||||
******************************************************************************/
|
||||
/*
|
||||
*
|
||||
* @file xstreamer.h
|
||||
*
|
||||
* The Xilinx byte streamer for packet FIFOs.
|
||||
*
|
||||
* <h2>Driver Description</h2>
|
||||
*
|
||||
* This driver enables higher layer software to access a hardware FIFO using
|
||||
* any alignment in the data buffers while preserving alignment for the hardware
|
||||
* FIFO access.
|
||||
*
|
||||
* This driver treats send and receive channels separately, using different
|
||||
* types of instance objects for each.
|
||||
*
|
||||
* This driver makes use of another FIFO driver to access the specific FIFO
|
||||
* hardware through use of the routines passed into the Tx/RxInitialize
|
||||
* routines.
|
||||
*
|
||||
* <h2>Initialization</h2>
|
||||
*
|
||||
* Send and receive channels are intialized separately. The receive channel is
|
||||
* initiailzed using XStrm_RxInitialize(). The send channel is initialized
|
||||
* using XStrm_TxInitialize().
|
||||
*
|
||||
*
|
||||
* <h2>Usage</h2>
|
||||
* It is fairly simple to use the API provided by this byte streamer
|
||||
* driver. The only somewhat tricky part is that the calling code must
|
||||
* correctly call a couple routines in the right sequence for receive and
|
||||
* transmit.
|
||||
*
|
||||
* This sequence is described here. Check the routine functional
|
||||
* descriptions for information on how to use a specific API routine.
|
||||
*
|
||||
* <h3>Receive</h3>
|
||||
* A frame is received by using the following sequence:<br>
|
||||
* 1) call XStrm_RxGetLen() to get the length of the next incoming frame.<br>
|
||||
* 2) call XStrm_Read() one or more times to read the number of bytes
|
||||
* reported by XStrm_RxGetLen().<br>
|
||||
*
|
||||
* For example:
|
||||
* <pre>
|
||||
* frame_len = XStrm_RxGetLen(&RxInstance);
|
||||
* while (frame_len) {
|
||||
* unsigned bytes = min(sizeof(buffer), frame_len);
|
||||
* XStrm_Read(&RxInstance, buffer, bytes);
|
||||
* // do something with buffer here
|
||||
* frame_len -= bytes;
|
||||
* }
|
||||
* </pre>
|
||||
*
|
||||
* Other restrictions on the sequence of API calls may apply depending on
|
||||
* the specific FIFO driver used by this byte streamer driver.
|
||||
*
|
||||
* <h3>Transmit</h3>
|
||||
* A frame is transmittted by using the following sequence:<br>
|
||||
* 1) call XStrm_Write() one or more times to write all the of bytes in
|
||||
* the next frame.<br>
|
||||
* 2) call XStrm_TxSetLen() to begin the transmission of frame just
|
||||
* written.<br>
|
||||
*
|
||||
* For example:
|
||||
* <pre>
|
||||
* frame_left = frame_len;
|
||||
* while (frame_left) {
|
||||
* unsigned bytes = min(sizeof(buffer), frame_left);
|
||||
* XStrm_Write(&TxInstance, buffer, bytes);
|
||||
* // do something here to refill buffer
|
||||
* }
|
||||
* XStrm_TxSetLen(&RxInstance, frame_len);
|
||||
* </pre>
|
||||
*
|
||||
* Other restrictions on the sequence of API calls may apply depending on
|
||||
* the specific FIFO driver used by this byte streamer driver.
|
||||
*
|
||||
* <pre>
|
||||
* MODIFICATION HISTORY:
|
||||
*
|
||||
* Ver Who Date Changes
|
||||
* ----- ---- -------- -------------------------------------------------------
|
||||
* 1.00a jvb 10/12/06 First release
|
||||
* 1.02a jz 12/04/09 Hal phase 1 support
|
||||
* 2.00a hbm 01/20/10 Hal phase 1 support, bump up major release
|
||||
* 2.02a asa 12/28/11 The macro XStrm_IsRxInternalEmpty is changed to use
|
||||
* FrmByteCnt instead of HeadIndex.
|
||||
* </pre>
|
||||
*
|
||||
*****************************************************************************/
|
||||
#ifndef XSTREAMER_H /* prevent circular inclusions */
|
||||
#define XSTREAMER_H /* by using preprocessor symbols */
|
||||
|
||||
/* force C linkage */
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "xenv.h"
|
||||
#include "xdebug.h"
|
||||
#include "xil_types.h"
|
||||
|
||||
/*
|
||||
* key hole size in 32 bit words
|
||||
*/
|
||||
#define LARGEST_FIFO_KEYHOLE_SIZE_WORDS 4
|
||||
|
||||
/*
|
||||
* This union is used simply to force a 32bit alignment on the
|
||||
* buffer. Only the 'bytes' member is really used.
|
||||
*/
|
||||
union XStrm_AlignedBufferType {
|
||||
u32 _words[LARGEST_FIFO_KEYHOLE_SIZE_WORDS];
|
||||
char bytes[LARGEST_FIFO_KEYHOLE_SIZE_WORDS * 4];
|
||||
};
|
||||
|
||||
typedef int(*XStrm_XferFnType) (void *FifoInstance, void *BufPtr,
|
||||
unsigned WordCount);
|
||||
typedef u32 (*XStrm_GetLenFnType) (void *FifoInstance);
|
||||
typedef void (*XStrm_SetLenFnType) (void *FifoInstance,
|
||||
u32 ByteCount);
|
||||
typedef u32 (*XStrm_GetOccupancyFnType) (void *FifoInstance);
|
||||
typedef u32 (*XStrm_GetVacancyFnType) (void *FifoInstance);
|
||||
|
||||
/**
|
||||
* This typedef defines a run-time instance of a receive byte-streamer.
|
||||
*/
|
||||
typedef struct XStrm_RxFifoStreamer {
|
||||
union XStrm_AlignedBufferType AlignedBuffer;
|
||||
unsigned HeadIndex; /**< HeadIndex is the index to the AlignedBuffer
|
||||
* as bytes.
|
||||
*/
|
||||
unsigned FifoWidth; /**< FifoWidth is the FIFO key hole width in bytes.
|
||||
*/
|
||||
unsigned FrmByteCnt; /**< FrmByteCnt is the number of bytes in the next
|
||||
* Frame.
|
||||
*/
|
||||
void *FifoInstance; /**< FifoInstance is the FIFO driver instance to
|
||||
* pass to ReadFn, GetLenFn, and GetOccupancyFn
|
||||
* routines.
|
||||
*/
|
||||
XStrm_XferFnType ReadFn; /**< ReadFn is the routine the streamer
|
||||
* uses to receive bytes from the Fifo.
|
||||
*/
|
||||
XStrm_GetLenFnType GetLenFn; /**< GetLenFn is the routine the streamer
|
||||
* uses to initiate receive operations
|
||||
* on the FIFO.
|
||||
*/
|
||||
XStrm_GetOccupancyFnType GetOccupancyFn; /**< GetOccupancyFn is the
|
||||
* routine the streamer uses
|
||||
* to get the occupancy from
|
||||
* the FIFO.
|
||||
*/
|
||||
} XStrm_RxFifoStreamer;
|
||||
|
||||
/**
|
||||
* This typedef defines a run-time instance of a transmit byte-streamer.
|
||||
*/
|
||||
typedef struct XStrm_TxFifoStreamer {
|
||||
union XStrm_AlignedBufferType AlignedBuffer;
|
||||
unsigned TailIndex; /**< TailIndex is the index to the AlignedBuffer
|
||||
* as bytes
|
||||
*/
|
||||
unsigned FifoWidth; /**< FifoWidth is the FIFO key hole width in bytes.
|
||||
*/
|
||||
|
||||
void *FifoInstance; /**< FifoInstance is the FIFO driver instance to
|
||||
* pass to WriteFn, SetLenFn, and GetVacancyFn
|
||||
* routines.
|
||||
*/
|
||||
XStrm_XferFnType WriteFn; /**< WriteFn is the routine the streamer
|
||||
* uses to transmit bytes to the Fifo.
|
||||
*/
|
||||
XStrm_SetLenFnType SetLenFn; /**< SetLenFn is the routine the streamer
|
||||
* uses to initiate transmit operations
|
||||
* on the FIFO.
|
||||
*/
|
||||
XStrm_GetVacancyFnType GetVacancyFn; /**< GetVaccancyFn is the routine
|
||||
* the streamer uses to get the
|
||||
* vacancy from the FIFO.
|
||||
*/
|
||||
} XStrm_TxFifoStreamer;
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_TxVacancy returns the number of unused 32-bit words available (vacancy)
|
||||
* between the streamer, specified by <i>InstancePtr</i>, and the FIFO this
|
||||
* streamer is using.
|
||||
*
|
||||
* @param InstancePtr references the streamer on which to operate.
|
||||
*
|
||||
* @return XStrm_TxVacancy returns the vacancy count in number of 32 bit words.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* C Signature: u32 XStrm_TxVacancy(XStrm_TxFifoStreamer *InstancePtr)
|
||||
*
|
||||
* The amount of bytes in the holding buffer (rounded up to whole 32-bit words)
|
||||
* is subtracted from the vacancy value of FIFO this streamer is using. This is
|
||||
* to ensure the caller can write the number words given in the return value and
|
||||
* not overflow the FIFO.
|
||||
*
|
||||
******************************************************************************/
|
||||
#define XStrm_TxVacancy(InstancePtr) \
|
||||
(((*(InstancePtr)->GetVacancyFn)((InstancePtr)->FifoInstance)) - \
|
||||
(((InstancePtr)->TailIndex + 3) / 4))
|
||||
|
||||
/*****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_RxOccupancy returns the number of 32-bit words available (occupancy) to
|
||||
* be read from the streamer, specified by <i>InstancePtr</i>, and FIFO this
|
||||
* steamer is using.
|
||||
*
|
||||
* @param InstancePtr references the streamer on which to operate.
|
||||
*
|
||||
* @return XStrm_RxOccupancy returns the occupancy count in number of 32 bit
|
||||
* words.
|
||||
*
|
||||
* @note
|
||||
*
|
||||
* C Signature: u32 XStrm_RxOccupancy(XStrm_RxFifoStreamer *InstancePtr)
|
||||
*
|
||||
* The amount of bytes in the holding buffer (rounded up to whole 32-bit words)
|
||||
* is added to the occupancy value of FIFO this streamer is using. This is to
|
||||
* ensure the caller will get a little more accurate occupancy value.
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifdef DEBUG
|
||||
extern u32 _xstrm_ro_value;
|
||||
extern u32 _xstrm_buffered;
|
||||
#define XStrm_RxOccupancy(InstancePtr) \
|
||||
(_xstrm_ro_value = ((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)), \
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "reg: %d; frmbytecnt: %d\n", \
|
||||
_xstrm_ro_value, (InstancePtr)->FrmByteCnt), \
|
||||
(((InstancePtr)->FrmByteCnt) ? \
|
||||
_xstrm_buffered = ((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
|
||||
0), \
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered_bytes: %d\n", _xstrm_buffered), \
|
||||
xdbg_printf(XDBG_DEBUG_FIFO_RX, "buffered (rounded): %d\n", _xstrm_buffered), \
|
||||
(_xstrm_ro_value + _xstrm_buffered))
|
||||
#else
|
||||
#define XStrm_RxOccupancy(InstancePtr) \
|
||||
( \
|
||||
((*(InstancePtr)->GetOccupancyFn)((InstancePtr)->FifoInstance)) + \
|
||||
( \
|
||||
((InstancePtr)->FrmByteCnt) ? \
|
||||
((InstancePtr)->FifoWidth - (InstancePtr)->HeadIndex) : \
|
||||
0 \
|
||||
) \
|
||||
)
|
||||
#endif
|
||||
|
||||
/****************************************************************************/
|
||||
/*
|
||||
*
|
||||
* XStrm_IsRxInternalEmpty returns true if the streamer, specified by
|
||||
* <i>InstancePtr</i>, is not holding any bytes in it's internal buffers. Note
|
||||
* that this routine does not reflect information about the state of the
|
||||
* FIFO used by this streamer.
|
||||
*
|
||||
* @param InstancePtr references the streamer on which to operate.
|
||||
*
|
||||
* @return XStrm_IsRxInternalEmpty returns TRUE when the streamer is not
|
||||
* holding any bytes in it's internal buffers. Otherwise,
|
||||
* XStrm_IsRxInternalEmpty returns FALSE.
|
||||
*
|
||||
* @note
|
||||
* C-style signature:
|
||||
* int XStrm_IsRxInternalEmpty(XStrm_RxFifoStreamer *InstancePtr)
|
||||
*
|
||||
*****************************************************************************/
|
||||
#define XStrm_IsRxInternalEmpty(InstancePtr) \
|
||||
(((InstancePtr)->FrmByteCnt == 0) ? TRUE : FALSE)
|
||||
|
||||
void XStrm_RxInitialize(XStrm_RxFifoStreamer *InstancePtr,
|
||||
unsigned FifoWidth, void *FifoInstance,
|
||||
XStrm_XferFnType ReadFn,
|
||||
XStrm_GetLenFnType GetLenFn,
|
||||
XStrm_GetOccupancyFnType GetOccupancyFn);
|
||||
|
||||
void XStrm_TxInitialize(XStrm_TxFifoStreamer *InstancePtr,
|
||||
unsigned FifoWidth, void *FifoInstance,
|
||||
XStrm_XferFnType WriteFn,
|
||||
XStrm_SetLenFnType SetLenFn,
|
||||
XStrm_GetVacancyFnType GetVacancyFn);
|
||||
|
||||
void XStrm_TxSetLen(XStrm_TxFifoStreamer *InstancePtr, u32 Bytes);
|
||||
void XStrm_Write(XStrm_TxFifoStreamer *InstancePtr, void *BufPtr,
|
||||
unsigned bytes);
|
||||
|
||||
u32 XStrm_RxGetLen(XStrm_RxFifoStreamer *InstancePtr);
|
||||
void XStrm_Read(XStrm_RxFifoStreamer *InstancePtr, void *BufPtr,
|
||||
unsigned bytes);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* XSTREAMER_H end of preprocessor protection symbols */
|
||||
Loading…
Add table
Reference in a new issue