sw_apps:zynq_fsbl: Removed the PEEP code
Removed the unwanted PEEP code from FSBL Signed-off-by: Krishna Chaitanya <kpataka@xilinx.com> Acked-by: Nirmala Pelluri <nirmala@xilinx.com>
This commit is contained in:
Krishna Chaitanya
Jagannadha Sutradharudu Teki
parent
025250a09c
commit
8fbb1b0a90
2 changed files with 0 additions and 292 deletions
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@ -1,282 +0,0 @@
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/******************************************************************************
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*
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* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file ddr_init.c
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*
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* Initialize the DDR controller. When PCW is functioning, this would be gone.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a ecm 06/19/09 First release
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* 2.00a jz 05/11/11 Changed register to #defines, updated to peep11
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* 3.00a mb 30/05/12 included fsbl.h
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* </pre>
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xil_io.h"
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#include "fsbl.h"
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/************************** Constant Definitions *****************************/
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#define DDR_CONFIG_BASE (XPS_DDR_CTRL_BASEADDR + 0x000)
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#define DDR_MSTR_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x000)
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#define DDR_TWORANKPHY_REG (XPS_DDR_CTRL_BASEADDR + 0x004)
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#define DDR_HPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x008)
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#define DDR_LPR_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x00C)
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#define DDR_W_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x010)
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#define DDR_DRAM_PARAMS_1_REG (XPS_DDR_CTRL_BASEADDR + 0x014)
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#define DDR_DRAM_PARAMS_2_REG (XPS_DDR_CTRL_BASEADDR + 0x018)
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#define DDR_DRAM_PARAMS_3_REG (XPS_DDR_CTRL_BASEADDR + 0x01C)
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#define DDR_DRAM_PARAMS_4_REG (XPS_DDR_CTRL_BASEADDR + 0x020)
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#define DDR_DRAM_PARAMS_5_REG (XPS_DDR_CTRL_BASEADDR + 0x024)
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#define DDR_DRAM_INIT_PARAMS_REG (XPS_DDR_CTRL_BASEADDR + 0x028)
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#define DDR_DRAM_MODE_1_REG (XPS_DDR_CTRL_BASEADDR + 0x02C)
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#define DDR_DRAM_MODE_2_REG (XPS_DDR_CTRL_BASEADDR + 0x030)
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#define DDR_DRAM_BURST8_REG (XPS_DDR_CTRL_BASEADDR + 0x034)
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#define DDR_DEBUG_REG (XPS_DDR_CTRL_BASEADDR + 0x038)
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#define DDR_ADDR_MAP_1_REG (XPS_DDR_CTRL_BASEADDR + 0x03C)
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#define DDR_ADDR_MAP_2_REG (XPS_DDR_CTRL_BASEADDR + 0x040)
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#define DDR_ADDR_MAP_3_REG (XPS_DDR_CTRL_BASEADDR + 0x044)
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#define DDR_ODT_RD_WR_REG (XPS_DDR_CTRL_BASEADDR + 0x048)
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#define DDR_PHY_RDC_FIFO_CTRL_REG (XPS_DDR_CTRL_BASEADDR + 0x04C)
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#define DDR_REG_PHY_RDC_FIFO_CTRL (XPS_DDR_CTRL_BASEADDR + 0x050)
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#define DDR_STATUS_REG (XPS_DDR_CTRL_BASEADDR + 0x054)
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#define DDR_DLL_CALIB_REG (XPS_DDR_CTRL_BASEADDR + 0x058)
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#define DDR_ODT_REG (XPS_DDR_CTRL_BASEADDR + 0x05C)
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#define DDR_MISC_1_REG (XPS_DDR_CTRL_BASEADDR + 0x060)
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#define DDR_MISC_2_REG (XPS_DDR_CTRL_BASEADDR + 0x064)
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#define DDR_WR_DLL_FORCE (XPS_DDR_CTRL_BASEADDR + 0x068)
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#define DDR_RD_DLL_FORCE0_REG (XPS_DDR_CTRL_BASEADDR + 0x06C)
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#define DDR_RD_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x070)
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#define DDR_WR_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x074)
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#define DDR_RD_RATIO_REG (XPS_DDR_CTRL_BASEADDR + 0x078)
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#define DDR_MSTR_DLL_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x07C)
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#define DDR_RD_SLAVE_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x080)
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#define DDR_RD_SLAVE_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x084)
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#define DDR_OF_STATUS0_REG (XPS_DDR_CTRL_BASEADDR + 0x088)
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#define DDR_OF_STATUS1_REG (XPS_DDR_CTRL_BASEADDR + 0x08C)
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#define DDR_OF_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x090)
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#define DDR_OF_STATUS3_REG (XPS_DDR_CTRL_BASEADDR + 0x094)
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#define DDR_MSTR_DLL_STATUS2_REG (XPS_DDR_CTRL_BASEADDR + 0x098)
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#define DDR_Wr_DLL_FORCE1_REG (XPS_DDR_CTRL_BASEADDR + 0x09C)
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#define DDR_REFRESH_TIMER01_REG (XPS_DDR_CTRL_BASEADDR + 0x0A0)
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#define DDR_T_ZQ_REG (XPS_DDR_CTRL_BASEADDR + 0x0A4)
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#define DDR_T_ZQ_SHORT_INTERVAL_REG (XPS_DDR_CTRL_BASEADDR + 0x0A8)
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#define DDR_STATUS_DATA_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0AC)
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#define DDR_STATUS_DATA_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B0)
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#define DDR_STATUS_DQS_SL_DLL_01_REG (XPS_DDR_CTRL_BASEADDR + 0x0B4)
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#define DDR_STATUS_DQS_SL_DLL_23_REG (XPS_DDR_CTRL_BASEADDR + 0x0B8)
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#define DDR_WR_DATA_SLV0_REG (XPS_DDR_CTRL_BASEADDR + 0x17c)
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#define DDR_WR_DATA_SLV1_REG (XPS_DDR_CTRL_BASEADDR + 0x180)
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#define DDR_WR_DATA_SLV2_REG (XPS_DDR_CTRL_BASEADDR + 0x184)
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#define DDR_WR_DATA_SLV3_REG (XPS_DDR_CTRL_BASEADDR + 0x188)
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#define DDR_ID_REG (XPS_DDR_CTRL_BASEADDR + 0x200)
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#define DDR_DDR_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x204)
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#define DDR_PRIO_WR_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x208)
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#define DDR_PRIO_WR_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x20C)
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#define DDR_PRIO_WR_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x210)
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#define DDR_PRIO_WR_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x214)
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#define DDR_PRIO_RD_PORT00_REG (XPS_DDR_CTRL_BASEADDR + 0x218)
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#define DDR_PRIO_RD_PORT01_REG (XPS_DDR_CTRL_BASEADDR + 0x21C)
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#define DDR_PRIO_RD_PORT02_REG (XPS_DDR_CTRL_BASEADDR + 0x220)
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#define DDR_PRIO_RD_PORT03_REG (XPS_DDR_CTRL_BASEADDR + 0x224)
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#define DDR_PERF_MON_1_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x228)
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#define DDR_PERF_MON_1_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x22C)
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#define DDR_PERF_MON_1_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x230)
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#define DDR_PERF_MON_1_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x234)
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#define DDR_PERF_MON_2_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x238)
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#define DDR_PERF_MON_2_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x23C)
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#define DDR_PERF_MON_2_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x240)
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#define DDR_PERF_MON_2_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x244)
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#define DDR_PERF_MON_3_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x248)
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#define DDR_PERF_MON_3_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x24C)
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#define DDR_PERF_MON_3_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x250)
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#define DDR_PERF_MON_3_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x254)
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#define DDR_TRUSTED_MEM_CFG_REG (XPS_DDR_CTRL_BASEADDR + 0x258)
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#define DDR_EXCLACC_CFG_PORT0_REG (XPS_DDR_CTRL_BASEADDR + 0x25C)
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#define DDR_EXCLACC_CFG_PORT1_REG (XPS_DDR_CTRL_BASEADDR + 0x260)
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#define DDR_EXCLACC_CFG_PORT2_REG (XPS_DDR_CTRL_BASEADDR + 0x264)
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#define DDR_EXCLACC_CFG_PORT3_REG (XPS_DDR_CTRL_BASEADDR + 0x268)
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/* Trust zone configuration register */
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#define SLCR_LOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x4)
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#define SLCR_UNLOCK_REG (XPS_SYS_CTRL_BASEADDR + 0x8)
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#define TZ_DDR_RAM_REG (XPS_SYS_CTRL_BASEADDR + 0x430)
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/* Mask defines */
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#define DDR_OUT_RESET_MASK 0x1
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define DDRIn32 Xil_In32
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#define DDROut32 Xil_Out32
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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void init_ddr(void);
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#define DDRIn32 Xil_In32
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#define DDROut32 Xil_Out32
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static int verify = 0;
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static void NewDDROut32(u32 Address, u32 Value)
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{
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u32 Data;
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if (verify) {
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Data = DDRIn32(Address);
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if (Data != Value) fsbl_printf(DEBUG_INFO,"Verify failed, Address = %08X, \
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Data = %08X, Expected = %08X\n\r", Address, Data, Value);
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} else
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DDROut32(Address, Value);
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}
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#undef DDROut32
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#define DDROut32 NewDDROut32
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void init_ddr(void)
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{
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u32 RegValue;
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RegValue = DDRIn32(DDR_MSTR_CTRL_REG);
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/* If DDR is being taking out of reset, then it has been configured
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*/
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if (RegValue & DDR_OUT_RESET_MASK)
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verify = 1;
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/* Configure DDR */
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DDROut32(DDR_MSTR_CTRL_REG, 0x00000200);
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/* direct rip of the DDR init tcl for the PEEP startup */
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DDROut32(DDR_TWORANKPHY_REG, 0x000C1061); /* # 0 */
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DDROut32(DDR_LPR_PARAMS_REG, 0x03001001); //;#3
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DDROut32(DDR_W_PARAMS_REG, 0x00014001); //;#4
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DDROut32(DDR_DRAM_PARAMS_1_REG, 0x0004e020); //; #5
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#ifdef PEEP_CODE
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DDROut32(DDR_DRAM_PARAMS_2_REG, 0x36264ccf); //; #6
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#else
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DDROut32(DDR_DRAM_PARAMS_2_REG, 0x349B48CD); //; #6
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#endif
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DDROut32(DDR_DRAM_PARAMS_3_REG, 0x820158a4); //; #7
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DDROut32(DDR_DRAM_PARAMS_4_REG, 0x250882c4); //; #8
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DDROut32(DDR_DRAM_INIT_PARAMS_REG, 0x00809004); //; #10
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DDROut32(DDR_DRAM_MODE_1_REG, 0x0); //; #11
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DDROut32(DDR_DRAM_MODE_2_REG, 0x00040952); //; #12
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DDROut32(DDR_DRAM_BURST8_REG, 0x00020022); //; #13
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#ifdef PEEP_CODE
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DDROut32(DDR_ADDR_MAP_1_REG, 0xF88); //; #15
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#endif
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#ifdef PALLADIUM
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DDROut32(DDR_ADDR_MAP_1_REG, 0x777); //; #15
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#endif
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DDROut32(DDR_ADDR_MAP_2_REG, 0xFF000000); //; #16
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DDROut32(DDR_ADDR_MAP_3_REG, 0x0FF66666); //; #17
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DDROut32(DDR_REG_PHY_RDC_FIFO_CTRL, 0x256); //; #20
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DDROut32(DDR_ODT_REG, 0x2223); //; #23
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DDROut32(DDR_MISC_2_REG, 0x00020FE0); //; #25
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DDROut32(DDR_T_ZQ_REG, 0x10200800); //; #41
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DDROut32(DDR_STATUS_DQS_SL_DLL_23_REG, 0x200065); //; #46
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DDROut32(DDR_WR_DATA_SLV0_REG, 0x50); //; #95
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DDROut32(DDR_WR_DATA_SLV1_REG, 0x50); //; #96
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DDROut32(DDR_WR_DATA_SLV2_REG, 0x50); //; #97
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DDROut32(DDR_WR_DATA_SLV3_REG, 0x50); //; #98
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DDROut32(DDR_ID_REG, 0x0); //; #128
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/* Enable ddr controller by taking the controller out of reset */
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DDROut32(DDR_MSTR_CTRL_REG,
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DDRIn32(DDR_MSTR_CTRL_REG) | DDR_OUT_RESET_MASK);
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#ifdef PALLADIUM
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/* Workaround for early palladium, to be removed for 4.61 */
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DDROut32(SLCR_UNLOCK_REG, 0xDF0D);
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DDROut32(TZ_DDR_RAM_REG, 0xffffffff);
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DDROut32(SLCR_LOCK_REG, 0x767B);
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#endif /* PALLADIUM*/
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}
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@ -159,9 +159,6 @@ extern char* getPS7MessageInfo(unsigned key);
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#ifdef PS7_POST_CONFIG
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extern int ps7_post_config();
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#endif
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#ifdef PEEP_CODE
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extern void init_ddr(void);
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#endif
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static void Update_MultiBootRegister(void);
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/* Exception handlers */
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@ -230,12 +227,6 @@ int main(void)
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u32 HandoffAddress = 0;
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u32 Status = XST_SUCCESS;
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#ifdef PEEP_CODE
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/*
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* PEEP DDR initialization
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*/
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init_ddr();
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#else
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/*
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* PCW initialization for MIO,PLL,CLK and DDR
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*/
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@ -250,7 +241,6 @@ int main(void)
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*/
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FsblHookFallback();
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}
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#endif
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/*
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* Unlock SLCR for SLCR register write
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