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dptx: Clean-up and commenting.

Browse source 
- General clean-up and commenting.
- Added comment documentation to the examples, as well as some general
information in xdptx.h.
- Examples now identify the CPU architecture using the existence of
XPAR_INTC_0_DEVICE_ID from the xparameters.h instead of the __MICROBLAZE__
macro.
- Added and renamed some files for improved integration into SDK.
- Cleaned-up documentation and code for readability.
- No longer returning XST_INVALID_PARAMETER in lieu of asserts.
- Renamed TxConfig member of the XDptx structure to Config.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2014-07-22 20:52:35 -07:00 • committed by Jagannadha Sutradharudu Teki
parent b94a087ad1
commit 94cf07d9a9
19 changed files with 1616 additions and 1120 deletions
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0
XilinxProcessorIPLib/drivers/dptx/data/dptx_0.mdd → XilinxProcessorIPLib/drivers/dptx/data/dptx.mdd
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0
XilinxProcessorIPLib/drivers/dptx/data/dptx_0.tcl → XilinxProcessorIPLib/drivers/dptx/data/dptx.tcl
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20
XilinxProcessorIPLib/drivers/dptx/examples/index.html Executable file
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@ -0,0 +1,20 @@
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2 Final//EN">
<html>
<head>
<meta http-equiv="Content-Language" content="en-us">
<meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
<title>Driver example applications</title>
<link rel="stylesheet" type="text/css" href="../help.css">
</head>
<body bgcolor="#FFFFFF">
<h1> Example applications for the dptx driver. </h1>
<HR>
<ul>
<li>xdptx_intr_example.c <a href="xdptx_intr_example.c">(source)</a> </li>
<li>xdptx_poll_example.c <a href="xdptx_poll_example.c">(source)</a> </li>
<li>xdptx_selftest_example.c <a href="xdptx_selftest_example.c">(source)</a> </li>
<li>xdptx_timer_example.c <a href="xdptx_timer_example.c">(source)</a> </li>
</ul>
<p><font face="Times New Roman" color="#800000">Copyright © 1995-2014 Xilinx, Inc. All rights reserved.</font></p>
</body>
</html>

41
XilinxProcessorIPLib/drivers/dptx/examples/readme.txt Normal file
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@ -0,0 +1,41 @@
There are 4 examples included in this directory:
1) xdptx_intr_example.c : This interrupt example shows how to set up the
interrupt system and specify the interrupt handlers for when a DisplayPort
interrupt event occurs. An interrupt controller with a connection to the
DisplayPort interrupt signal needs to exist in the hardware system.
2) xdptx_poll_example.c : This interrupt example shows how to poll the
DisplayPort TX instance's registers for DisplayPort interrupt events.
3) xdptx_timer_example.c : This timer example shows how to override the default
sleep/delay functionality for MicroBlaze. A timer needs to exist in the
hardware system and will be used for sleep/delay functionality inside of a
callback function. The default behavior in MicroBlaze for sleep/delay is to
call MB_Sleep from microblaze_sleep.h, which has only millisecond accuracy.
For ARM/Zynq SoC systems, the supplied callback function will be ignored -
the usleep function will be called since the SoC has a timer built-in.
4) xdptx_selftest_example.c : This self test example will perform a sanity check
on the state of the DisplayPort TX instance. It may be called prior to usage
of the core or after a reset to ensure that (a subset of) the registers hold
the default values.
Each of these examples are meant to be used in conjunction with
xdptx_example_common.[ch] which holds common functionality for all examples.
After importing the examples, these files will need to be manually copied into
the example src/ directory.
This code shows how to train the main link and set up the
Additionally, in order to be able to use the interrupt, polling, and timer
examples, the user will need to implement and link the following functions:
1) Dptx_InitPlatform : This function needs to do all hardware system
initialization. This function is invoked when calling
2) Dptx_ConfigureStreamSrc : This function needs to configure the source of the
stream (pattern generators, video input, etc.) such that a video stream, with
timings and video attributes that correspond to the main stream attributes
(MSA) configuration, is received by the DisplayPort Tx. The examples call
this function from the Dptx_Run->Dptx_StartVideoStream functions in
xdptx_example_common.c.
Note: All example functions start with Dptx_*, while all driver functions start
with XDptx_*.

152
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.c
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@ -38,7 +38,11 @@
* the DisplayPort TX core by training the main link at the maximum common
* capabilities between the TX and RX and checking the lane status.
*
* @note The DisplayPort TX core does not work alone. Some platform
* @note The DisplayPort TX core does not work alone - video/audio
* sources need to be set up in the system correctly, as well as
* setting up the output path (for example, configuring the
* hardware system with the DisplayPort TX core output to an FMC
* card with DisplayPort output capabilities. Some platform
* initialization will need to happen prior to calling XDptx driver
* functions. See XAPP1178 as a reference.
*
@ -59,26 +63,60 @@
/**************************** Function Prototypes *****************************/
static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate);
static u32 Dptx_StartLink(XDptx *InstancePtr);
static void Dptx_StartVideoStream(XDptx *InstancePtr);
/**************************** Function Definitions ****************************/
u32 Dptx_Run(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate)
/******************************************************************************/
/**
* This function will configure and establish a link with the receiver device,
* afterwards, a video stream will start to be sent over the main link.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param LaneCount is the number of lanes to use over the main link.
* @param LinkRate is the link rate to use over the main link.
*
* @return - XST_SUCCESS if main link was successfully established.
* - XST_FAILURE otherwise.
*
* @note None.
*
*******************************************************************************/
u32 Dptx_Run(XDptx *InstancePtr)
{
u32 Status;
Status = Dptx_StartLink(InstancePtr, LaneCount, LinkRate);
/* Configure and establish a link. */
Status = Dptx_StartLink(InstancePtr);
if (Status == XST_SUCCESS) {
/* Start the video stream. */
Dptx_StartVideoStream(InstancePtr);
} else {
xil_printf("<-- Failed to train.\n");
xil_printf("<-- Failed to establish/train the link.\n");
return XST_FAILURE;
}
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function will setup and initialize the DisplayPort TX core. The core's
* configuration parameters will be retrieved based on the configuration
* to the DisplayPort TX core instance with the specified device ID.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
*
* @return - XST_SUCCESS if the device configuration was found and obtained
* and if the main link was successfully established.
* - XST_FAILURE otherwise.
*
* @note None.
*
*******************************************************************************/
u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId)
{
XDptx_Config *ConfigPtr;
@ -89,6 +127,8 @@ u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId)
if (!ConfigPtr) {
return XST_FAILURE;
}
/* Copy the device configuration into the InstancePtr's Config
* structure. */
XDptx_CfgInitialize(InstancePtr, ConfigPtr, ConfigPtr->BaseAddr);
/* Initialize the DisplayPort TX core. */
@ -100,28 +140,54 @@ u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId)
return XST_SUCCESS;
}
static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate)
/******************************************************************************/
/**
* This function will configure and establish a link with the receiver device.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return - XST_SUCCESS the if main link was successfully established.
* - XST_FAILURE otherwise.
*
* @note None.
*
*******************************************************************************/
static u32 Dptx_StartLink(XDptx *InstancePtr)
{
u32 VsLevelTx;
u32 PeLevelTx;
u32 Status;
u8 LaneCount;
u8 LinkRate;
/* Obtain the capabilities of the sink by reading the monitor's DPCD. */
Status = XDptx_GetSinkCapabilities(InstancePtr);
/* Obtain the capabilities of the RX device by reading the monitor's
* DPCD. */
Status = XDptx_GetRxCapabilities(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#if defined(USE_MAX_LINK)
Status = XDptx_CheckLinkStatus(InstancePtr,
InstancePtr->LinkConfig.MaxLaneCount);
#if (TRAIN_USE_MAX_LINK == 1)
LaneCount = InstancePtr->LinkConfig.MaxLaneCount;
LinkRate = InstancePtr->LinkConfig.MaxLinkRate;
#else
Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount);
LaneCount = TRAIN_USE_LANE_COUNT;
LinkRate = TRAIN_USE_LINK_RATE;
#endif
/* Check if the link is already trained */
Status = XDptx_CheckLinkStatus(InstancePtr, LaneCount);
if (Status == XST_SUCCESS) {
xil_printf("-> Does not need training.\n");
if (XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
XDPTX_LINK_BW_SET) == LinkRate) {
xil_printf("-> Link is already trained on %d lanes.\n",
LaneCount);
if (XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_LINK_BW_SET) == LinkRate) {
xil_printf("-> Link needs to be re-trained %d Mbps.\n",
(270 * LinkRate));
}
else {
xil_printf("-> Link is already trained on %d Mbps.\n",
(270 * LinkRate));
return XST_SUCCESS;
}
}
@ -129,13 +195,18 @@ static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate)
xil_printf("-> Needs training.\n");
}
else {
/* Either a connection does not exist or the supplied lane count
* is invalid. */
xil_printf("-> Error checking link status.\n");
return XST_FAILURE;
}
#if defined(USE_MAX_LINK)
/* Configure the main link based on the common capabilities of the
* transmitter core and the sink monitor. */
XDptx_SetEnhancedFrameMode(InstancePtr, 1);
XDptx_SetDownspread(InstancePtr, 0);
#if (TRAIN_USE_MAX_LINK == 1)
/* Configure the main link based on the maximum common capabilities of
* the DisplayPort TX core and the receiver device. */
Status = XDptx_CfgMainLinkMax(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
@ -143,10 +214,9 @@ static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate)
#else
XDptx_SetLinkRate(InstancePtr, LinkRate);
XDptx_SetLaneCount(InstancePtr, LaneCount);
XDptx_SetEnhancedFrameMode(InstancePtr, 1);
XDptx_SetDownspread(InstancePtr, 0);
#endif
/* Train the link. */
xil_printf("******************************************\n");
Status = XDptx_EstablishLink(InstancePtr);
if (Status != XST_SUCCESS) {
@ -154,11 +224,11 @@ static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate)
xil_printf("******************************************\n");
return XST_FAILURE;
}
VsLevelTx = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
XDPTX_PHY_VOLTAGE_DIFF_LANE_0);
PeLevelTx = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
XDPTX_PHY_POSTCURSOR_LANE_0);
VsLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_PHY_VOLTAGE_DIFF_LANE_0);
PeLevelTx = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_PHY_POSTCURSOR_LANE_0);
xil_printf("!!! Training passed at LR:0x%02lx LC:%d !!!\n",
InstancePtr->LinkConfig.LinkRate,
InstancePtr->LinkConfig.LaneCount);
@ -170,6 +240,27 @@ static u32 Dptx_StartLink(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate)
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function will start sending a video stream over the main link. The
* settings to be used are as follows:
* - 8 bits per color.
* - Video timing and screen resolution used:
* - The connected monitor's preferred timing is used to determine the
* video resolution (and associated timings) for the stream.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note Dptx_ConfigureStreamSrc is intentionally left for the user to
* implement since configuration of the stream source is
* application-specific.
* @note The Extended Display Identification Data (EDID) is read in order
* to obtain the video resolution and timings. If this read fails,
* a resolution of 640x480 is used at a refresh rate of 60Hz.
*
*******************************************************************************/
static void Dptx_StartVideoStream(XDptx *InstancePtr)
{
u32 Status;
@ -186,7 +277,7 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr)
* 2) Use a standard video timing mode (see mode_table.h):
* XDptx_CfgMsaUseStandardVideoMode(InstancePtr, XDPTX_VM_640x480_60_P);
*
* 3) Use a custom configuration for the main stream attributes:
* 3) Use a custom configuration for the main stream attributes (MSA):
* XDptx_MainStreamAttributes MsaConfigCustom;
* MsaConfigCustom.MVid = 108000;
* MsaConfigCustom.HSyncPolarity = 0;
@ -204,8 +295,6 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr)
Status = XDptx_GetEdid(InstancePtr);
if (Status == XST_SUCCESS) {
XDptx_CfgMsaUseEdidPreferredTiming(InstancePtr);
XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
XDPTX_VM_640x480_60_P);
}
else {
XDptx_CfgMsaUseStandardVideoMode(InstancePtr,
@ -215,21 +304,20 @@ static void Dptx_StartVideoStream(XDptx *InstancePtr)
/* Disable MST for this example. */
AuxData[0] = 0;
XDptx_AuxWrite(InstancePtr, XDPTX_DPCD_MSTM_CTRL, 1, AuxData);
XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_TX_MST_CONFIG,
0x0);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_TX_MST_CONFIG, 0x0);
/* Disable main stream to force sending of IDLE patterns. */
XDptx_DisableMainLink(InstancePtr);
/* Reset the transmitter. */
XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SOFT_RESET,
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET,
XDPTX_SOFT_RESET_VIDEO_STREAM_ALL_MASK);
XDptx_WriteReg(InstancePtr->TxConfig.BaseAddr, XDPTX_SOFT_RESET, 0x0);
XDptx_WriteReg(InstancePtr->Config.BaseAddr, XDPTX_SOFT_RESET, 0x0);
/* Configure video stream source or generator here. This function needs
* to be implemented in order for video to be displayed and is hardware
* system specific. It is up to the user to implement this function. */
Dptx_ConfigureVidgen(InstancePtr);
Dptx_ConfigureStreamSrc(InstancePtr);
/*********************************/
XDptx_EnableMainLink(InstancePtr);

58
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_example_common.h
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@ -38,7 +38,11 @@
* the DisplayPort TX core by training the main link at the maximum common
* capabilities between the TX and RX and checking the lane status.
*
* @note The DisplayPort TX core does not work alone. Some platform
* @note The DisplayPort TX core does not work alone - video/audio
* sources need to be set up in the system correctly, as well as
* setting up the output path (for example, configuring the
* hardware system with the DisplayPort TX core output to an FMC
* card with DisplayPort output capabilities. Some platform
* initialization will need to happen prior to calling XDptx driver
* functions. See XAPP1178 as a reference.
*
@ -62,19 +66,61 @@
/**************************** Constant Definitions ****************************/
/* The unique device ID of the DisplayPort TX core instance to be used with the
* examples.*/
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
/* If set to 1, the link training process will continue training despite failing
* by attempting training at a reduced link rate. It will also continue
* attempting to train the link at a reduced lane count if needed. With this
* option enabled, link training will return failure only when all link rate and
* lane count combinations have been exhausted - that is, training fails using
* 1-lane and a 1.62Gbps link rate.
* If set to 0, link training will return failure if the training failed using
* the current lane count and link rate settings.
* TRAIN_ADAPTIVE is used by the examples as input to the
* XDptx_EnableTrainAdaptive driver function. */
#define TRAIN_ADAPTIVE 1
/* A value of 1 is used to indicate that the DisplayPort output path has a
* redriver on the board that adjusts the voltage swing and pre-emphasis levels
* that are outputted from the FPGA. If this is the case, the voltage swing and
* pre-emphasis values supplied to the DisplayPort TX core will be evenly
* distributed among the available levels as specified in the IP documentation.
* Otherwise, a value of 0 is used to indicate that no redriver is present. In
* order to meet the necessary voltage swing and pre-emphasis levels required by
* a DisplayPort RX device, the level values specified to the DisplayPort TX
* core will require some compensation.
* TRAIN_HAS_REDRIVER is used by the examples as input to the
* XDptx_SetHasRedriverInPath driver function.
* Note: There are 16 possible voltage swing levels and 32 possible pre-emphasis
* levels in the DisplayPort TX core that will be mapped to 4 possible
* voltage swing and 4 possible pre-emphasis levels in the RX device. */
#define TRAIN_HAS_REDRIVER 1
#define USE_MAX_LINK 1
#define USE_LINK_RATE XDPTX_LINK_BW_SET_540GBPS
#define USE_LANE_COUNT 4
/* The link rate setting to begin link training with. Valid values are:
* XDPTX_LINK_BW_SET_540GBPS, XDPTX_LINK_BW_SET_270GBPS, and
* XDPTX_LINK_BW_SET_162GBPS. */
#define TRAIN_USE_LINK_RATE XDPTX_LINK_BW_SET_540GBPS
/* The lane count setting to begin link training with. Valid values are:
* XDPTX_LANE_COUNT_SET_4, XDPTX_LANE_COUNT_SET_2, and
* XDPTX_LANE_COUNT_SET_1. */
#define TRAIN_USE_LANE_COUNT XDPTX_LANE_COUNT_SET_4
/* If set to 1, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will be ignored.
* Instead, the maximum common link capabilities between the DisplayPort TX core
* and the RX device will be used when establishing a link.
* If set to 0, TRAIN_USE_LINK_RATE and TRAIN_USE_LANE_COUNT will determine the
* link rate and lane count settings that the link training process will begin
* with. */
#define TRAIN_USE_MAX_LINK 1
/**************************** Function Prototypes *****************************/
extern u32 Dptx_PlatformInit(void);
extern u32 Dptx_ConfigureVidgen(XDptx *InstancePtr);
extern u32 Dptx_ConfigureStreamSrc(XDptx *InstancePtr);
u32 Dptx_SetupExample(XDptx *InstancePtr, u16 DeviceId);
u32 Dptx_Run(XDptx *InstancePtr, u8 LaneCount, u8 LinkRate);
u32 Dptx_Run(XDptx *InstancePtr);
/*************************** Variable Declarations ****************************/

272
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_example.c
View file

@ -34,17 +34,19 @@
*
* @file xdptx_intr_example.c
*
* Contains a design example using the XDptx driver with interrupts. Upon hot-
* plug-detect (DisplayPort cable is plugged/unplugged or the monitor is turned
* on/off), the main link will be trained.
* Contains a design example using the XDptx driver with interrupts. Upon Hot-
* Plug-Detect (HPD - DisplayPort cable is plugged/unplugged or the monitor is
* turned on/off), the main link will be trained.
*
* @note This example requires an interrupt controller connected to the
* processor and the DisplayPort TX core in the system.
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureVidgen - called in xdptx_example_common.c).
* See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
*
@ -65,44 +67,113 @@
#include "xil_printf.h"
#include "xparameters.h"
#include "xstatus.h"
#if defined(__MICROBLAZE__)
#ifdef XPAR_INTC_0_DEVICE_ID
/* For MicroBlaze systems. */
#include "xintc.h"
#elif defined(__arm__)
#include "xscugic.h"
#else
#error "Unknown processor type."
#endif
/* For ARM/Zynq SoC systems. */
#include "xscugic.h"
#endif /* XPAR_INTC_0_DEVICE_ID */
/**************************** Constant Definitions ****************************/
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
#if defined(__MICROBLAZE__)
/* The following constants map to the XPAR parameters created in the
* xparameters.h file. */
#ifdef XPAR_INTC_0_DEVICE_ID
#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#elif defined(__arm__)
#else
#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#endif
#endif /* XPAR_INTC_0_DEVICE_ID */
/****************************** Type Definitions ******************************/
/* Depending on whether the system is a MicroBlaze or ARM/Zynq SoC system,
* different drivers and associated types will be used. */
#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC XIntc
#define INTC_HANDLER XIntc_InterruptHandler
#else
#define INTC XScuGic
#define INTC_HANDLER XScuGic_InterruptHandler
#endif /* XPAR_INTC_0_DEVICE_ID */
/**************************** Function Prototypes *****************************/
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr,
void *IntrHandler, u32 IntrId);
static void Dptx_InterruptHandler(XDptx *InstancePtr);
u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler);
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler);
static void Dptx_HpdEventHandler(void *InstancePtr);
static void Dptx_HpdPulseHandler(void *InstancePtr);
/**************************** Variable Definitions ****************************/
#if defined(__MICROBLAZE__)
static XIntc IntcInstance;
#elif defined(__arm__)
static XScuGic IntcInstance;
#endif
INTC IntcInstance; /* The interrupt controller instance. */
/**************************** Function Definitions ****************************/
/******************************************************************************/
/**
* This function is the main function of the XDptx interrupt example. If the
* DptxIntrExample function, which sets up the system succeeds, this function
* will wait for interrupts. Once a connection event or pulse is detected, link
* training will commence (if needed) and a video stream will start being sent
* over the main link.
*
* @param None.
*
* @return - XST_FAILURE if the interrupt example was unsuccessful - system
* setup failed.
*
* @note Unless setup failed, main will never return since
* DptxIntrExample is blocking (it is waiting on interrupts for
* Hot-Plug-Detect (HPD) events.
*
*******************************************************************************/
int main(void)
{
/* Run the XDptx interrupt example. */
Dptx_IntrExample(&DptxInstance, DPTX_DEVICE_ID,
&IntcInstance, INTC_DEVICE_ID, DP_INTERRUPT_ID,
&Dptx_HpdEventHandler, &Dptx_HpdPulseHandler);
return XST_FAILURE;
}
/******************************************************************************/
/**
* The main entry point for the interrupt example using the XDptx driver. This
* function will set up the system with interrupts and set up the Hot-Plug-Event
* (HPD) handlers.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param IntcPtr is a pointer to the interrupt instance.
* @param IntrId is the unique device ID of the interrupt controller.
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
* the interrupt controller.
* @param HpdEventHandler is a pointer to the handler called when an HPD
* event occurs.
* @param HpdPulseHandler is a pointer to the handler called when an HPD
* pulse occurs.
*
* @return - XST_FAILURE if the system setup failed.
* - XST_SUCCESS should never return since this function, if setup
* was successful, is blocking.
*
* @note If system setup was successful, this function is blocking in
* order to illustrate interrupt handling taking place for HPD
* events.
*
*******************************************************************************/
u32 Dptx_IntrExample(XDptx *InstancePtr, u16 DeviceId, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler)
{
u32 Status;
@ -111,135 +182,168 @@ int main(void)
Dptx_PlatformInit();
/******************/
Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID);
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#if defined(TRAIN_ADAPTIVE)
XDptx_EnableTrainAdaptive(&DptxInstance, 1);
#else
XDptx_EnableTrainAdaptive(&DptxInstance, 0);
#endif
#if defined(TRAIN_HAS_REDRIVER)
XDptx_SetHasRedriverInPath(&DptxInstance, 1);
#else
XDptx_SetHasRedriverInPath(&DptxInstance, 0);
#endif
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
/* Setup interrupt handling in the system. */
Status = Dptx_SetupInterruptHandler(&DptxInstance,
&Dptx_InterruptHandler, DP_INTERRUPT_ID);
Status = Dptx_SetupInterruptHandler(InstancePtr, IntcPtr, IntrId,
DpIntrId, HpdEventHandler, HpdPulseHandler);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Do not return in order to allow interrupt handling to run. */
/* Do not return in order to allow interrupt handling to run. HPD events
* (connect, disconnect, and pulse) will be detected and handled. */
while (1);
return XST_SUCCESS;
}
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr,
void *IntrHandler, u32 IntrId)
/******************************************************************************/
/**
* This function sets up the interrupt system such that interrupts caused by
* Hot-Plug-Detect (HPD) events and pulses are handled. This function is
* application-specific for systems that have an interrupt controller connected
* to the processor. The user should modify this function to fit the
* application.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param IntcPtr is a pointer to the interrupt instance.
* @param IntrId is the unique device ID of the interrupt controller.
* @param DpIntrId is the interrupt ID of the DisplayPort TX connection to
* the interrupt controller.
* @param HpdEventHandler is a pointer to the handler called when an HPD
* event occurs.
* @param HpdPulseHandler is a pointer to the handler called when an HPD
* pulse occurs.
*
* @return - XST_SUCCESS if the interrupt system was successfully set up.
* - XST_FAILURE otherwise.
*
* @note An interrupt controller must be present in the system, connected
* to the processor and the DisplayPort TX core.
*
*******************************************************************************/
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr, INTC *IntcPtr,
u16 IntrId, u16 DpIntrId, XDptx_HpdEventHandler HpdEventHandler,
XDptx_HpdPulseHandler HpdPulseHandler)
{
u32 Status;
#if defined(__arm__)
XScuGic_Config *IntcConfig;
#endif
/* Set the HPD interrupt handlers. */
XDptx_SetHpdEventHandler(InstancePtr, &Dptx_HpdEventHandler,
InstancePtr);
XDptx_SetHpdPulseHandler(InstancePtr, &Dptx_HpdPulseHandler,
InstancePtr);
XDptx_SetHpdEventHandler(InstancePtr, HpdEventHandler, InstancePtr);
XDptx_SetHpdPulseHandler(InstancePtr, HpdPulseHandler, InstancePtr);
/* Initialize interrupt controller driver. */
#if defined(__MICROBLAZE__)
Status = XIntc_Initialize(&IntcInstance, INTC_DEVICE_ID);
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Initialize(IntcPtr, IntrId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#elif defined(__arm__)
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
Status = XScuGic_CfgInitialize(&IntcInstance, IntcConfig,
#else
XScuGic_Config *IntcConfig;
IntcConfig = XScuGic_LookupConfig(IntrId);
Status = XScuGic_CfgInitialize(IntcPtr, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(&IntcInstance, IntrId, 0xA0, 0x1);
#endif
XScuGic_SetPriorityTriggerType(IntcPtr, DpIntrId, 0xA0, 0x1);
#endif /* XPAR_INTC_0_DEVICE_ID */
/* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device. */
#if defined(__MICROBLAZE__)
Status = XIntc_Connect(&IntcInstance, IntrId,
(XInterruptHandler)IntrHandler, InstancePtr);
#elif defined(__arm__)
Status = XScuGic_Connect(&IntcInstance, IntrId,
(Xil_InterruptHandler)IntrHandler, InstancePtr);
#endif
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Connect(IntcPtr, DpIntrId,
(XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#else
Status = XScuGic_Connect(IntcPtr, DpIntrId,
(Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#endif /* XPAR_INTC_0_DEVICE_ID */
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Start the interrupt controller. */
#if defined(__MICROBLAZE__)
Status = XIntc_Start(&IntcInstance, XIN_REAL_MODE);
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Start(IntcPtr, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIntc_Enable(&IntcInstance, IntrId);
#elif defined(__arm__)
XScuGic_Enable(&IntcInstance, IntrId);
#endif
XIntc_Enable(IntcPtr, DpIntrId);
#else
XScuGic_Enable(IntcPtr, DpIntrId);
#endif /* XPAR_INTC_0_DEVICE_ID */
/* Initialize the exception table. */
Xil_ExceptionInit();
/* Register the interrupt controller handler with the exception table. */
#if defined(__MICROBLAZE__)
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_InterruptHandler, &IntcInstance);
#elif defined(__arm__)
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler, &IntcInstance);
#endif
(Xil_ExceptionHandler)INTC_HANDLER, IntcPtr);
/* Enable exceptions. */
Xil_ExceptionEnable();
#if defined(__MICROBLAZE__)
/* Enable interrupts in the MicroBlaze processor. */
microblaze_enable_interrupts();
#endif
return XST_SUCCESS;
}
static void Dptx_InterruptHandler(XDptx *InstancePtr)
{
XDptx_HpdInterruptHandler(InstancePtr);
}
/******************************************************************************/
/**
* This function is called when a Hot-Plug-Detect (HPD) event is received by the
* DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK bit of the
* core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
* occurred.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note Use the XDptx_SetHpdEventHandler driver function to set this
* function as the handler for HPD pulses.
*
*******************************************************************************/
static void Dptx_HpdEventHandler(void *InstancePtr)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
if (XDptx_IsConnected(XDptx_InstancePtr)) {
xil_printf("+===> HPD connection event detected.\n");
Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE);
Dptx_Run(XDptx_InstancePtr);
}
else {
xil_printf("+===> HPD disconnection event detected.\n\n");
}
}
/******************************************************************************/
/**
* This function is called when a Hot-Plug-Detect (HPD) pulse is received by the
* DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit
* of the core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
* occurred.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note Use the XDptx_SetHpdPulseHandler driver function to set this
* function as the handler for HPD pulses.
*
*******************************************************************************/
static void Dptx_HpdPulseHandler(void *InstancePtr)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
xil_printf("===> HPD pulse detected.\n");
Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE);
Dptx_Run(XDptx_InstancePtr);
}

205
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_intr_timer_example.c
View file

@ -34,10 +34,13 @@
*
* @file xdptx_intr_timer_example.c
*
* Contains a design example using the XDptx driver with interrupts. Upon hot-
* plug-detect (DisplayPort cable is plugged/unplugged or the monitor is turned
* on/off), the main link will be trained.
* Contains a design example using the XDptx driver with interrupts and. Upon Hot-
* Plug-Detect (HPD - DisplayPort cable is plugged/unplugged or the monitor is
* turned on/off), the main link will be trained.
*
* @note This example requires an interrupt controller connected to the
* processor and the DisplayPort TX core in the system.
* @note This example requires an AXI timer in the system.
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
@ -66,30 +69,41 @@
#include "xparameters.h"
#include "xstatus.h"
#include "xtmrctr.h"
#if defined(__MICROBLAZE__)
#ifdef XPAR_INTC_0_DEVICE_ID
/* For MicroBlaze systems. */
#include "xintc.h"
#elif defined(__arm__)
#include "xscugic.h"
#else
#error "Unknown processor type."
#endif
/* For ARM/Zynq SoC systems. */
#include "xscugic.h"
#endif /* XPAR_INTC_0_DEVICE_ID */
/**************************** Constant Definitions ****************************/
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
#if defined(__MICROBLAZE__)
/* The following constants map to the XPAR parameters created in the
* xparameters.h file. */
#ifdef XPAR_INTC_0_DEVICE_ID
#define DP_INTERRUPT_ID XPAR_AXI_INTC_1_DISPLAYPORT_0_AXI_INT_INTR
#define INTC_DEVICE_ID XPAR_INTC_0_DEVICE_ID
#elif defined(__arm__)
#else
#define DP_INTERRUPT_ID XPAR_FABRIC_DISPLAYPORT_0_AXI_INT_INTR
#define INTC_DEVICE_ID XPAR_SCUGIC_SINGLE_DEVICE_ID
#endif
#endif /* XPAR_INTC_0_DEVICE_ID */
/****************************** Type Definitions ******************************/
/* Depending on whether the system is a MicroBlaze or ARM/Zynq SoC system,
* different drivers and associated types will be used. */
#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC XIntc
#define INTC_HANDLER XIntc_InterruptHandler
#else
#define INTC XScuGic
#define INTC_HANDLER XScuGic_InterruptHandler
#endif /* XPAR_INTC_0_DEVICE_ID */
/**************************** Function Prototypes *****************************/
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr,
void *IntrHandler, u32 IntrId);
static void Dptx_InterruptHandler(XDptx *InstancePtr);
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr);
static void Dptx_HpdEventHandler(void *InstancePtr);
static void Dptx_HpdPulseHandler(void *InstancePtr);
@ -97,12 +111,8 @@ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds);
/**************************** Variable Definitions ****************************/
#if defined(__MICROBLAZE__)
XIntc IntcInstance;
#elif defined(__arm__)
XScuGic IntcInstance;
#endif
XTmrCtr TimerCounterInst;
INTC IntcInstance; /* The interrupt controller instance. */
XTmrCtr TimerCounterInst; /* The timer counter instance. */
/**************************** Function Definitions ****************************/
@ -115,8 +125,12 @@ int main(void)
Dptx_PlatformInit();
/******************/
/* Set a custom timer handler for improved delay accuracy.
* Note: This only has an affect for MicroBlaze systems. */
/* Set a custom timer handler for improved delay accuracy on MicroBlaze
* systems since the driver does not assume/have a dependency on the
* system having a timer in the FPGA.
* Note: This only has an affect for MicroBlaze systems since the Zynq
* SoC contains a timer, which is used when the driver calls the sleep
* function. */
XDptx_SetUserTimerHandler(&DptxInstance, &Dptx_CustomWaitUs,
&TimerCounterInst);
@ -125,20 +139,11 @@ int main(void)
return XST_FAILURE;
}
#if defined(TRAIN_ADAPTIVE)
XDptx_EnableTrainAdaptive(&DptxInstance, 1);
#else
XDptx_EnableTrainAdaptive(&DptxInstance, 0);
#endif
#if defined(TRAIN_HAS_REDRIVER)
XDptx_SetHasRedriverInPath(&DptxInstance, 1);
#else
XDptx_SetHasRedriverInPath(&DptxInstance, 0);
#endif
XDptx_EnableTrainAdaptive(&DptxInstance, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(&DptxInstance, TRAIN_HAS_REDRIVER);
/* Setup interrupt handling in the system. */
Status = Dptx_SetupInterruptHandler(&DptxInstance,
&Dptx_InterruptHandler, DP_INTERRUPT_ID);
Status = Dptx_SetupInterruptHandler(&DptxInstance);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
@ -148,13 +153,26 @@ int main(void)
return XST_SUCCESS;
}
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr,
void *IntrHandler, u32 IntrId)
/******************************************************************************/
/**
* This function sets up the interrupt system such that interrupts caused by
* Hot-Plug-Detect (HPD) events and pulses are handled. This function is
* application-specific for systems that have an interrupt controller connected
* to the processor. The user should modify this function to fit the
* application.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return - XST_SUCCESS if the interrupt system was successfully set up.
* - XST_FAILURE otherwise.
*
* @note An interrupt controller must be present in the system, connected
* to the processor and the DisplayPort TX core.
*
*******************************************************************************/
static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr)
{
u32 Status;
#if defined(__arm__)
XScuGic_Config *IntcConfig;
#endif
/* Set the HPD interrupt handlers. */
XDptx_SetHpdEventHandler(InstancePtr, &Dptx_HpdEventHandler,
@ -163,96 +181,133 @@ static u32 Dptx_SetupInterruptHandler(XDptx *InstancePtr,
InstancePtr);
/* Initialize interrupt controller driver. */
#if defined(__MICROBLAZE__)
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Initialize(&IntcInstance, INTC_DEVICE_ID);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#elif defined(__arm__)
#else
XScuGic_Config *IntcConfig;
IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
Status = XScuGic_CfgInitialize(&IntcInstance, IntcConfig,
IntcConfig->CpuBaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XScuGic_SetPriorityTriggerType(&IntcInstance, IntrId, 0xA0, 0x1);
#endif
XScuGic_SetPriorityTriggerType(&IntcInstance, DP_INTERRUPT_ID,
0xA0, 0x1);
#endif /* XPAR_INTC_0_DEVICE_ID */
/* Connect the device driver handler that will be called when an
* interrupt for the device occurs, the handler defined above performs
* the specific interrupt processing for the device. */
#if defined(__MICROBLAZE__)
Status = XIntc_Connect(&IntcInstance, IntrId,
(XInterruptHandler)IntrHandler, InstancePtr);
#elif defined(__arm__)
Status = XScuGic_Connect(&IntcInstance, IntrId,
(Xil_InterruptHandler)IntrHandler, InstancePtr);
#endif
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Connect(&IntcInstance, DP_INTERRUPT_ID,
(XInterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#else
Status = XScuGic_Connect(&IntcInstance, DP_INTERRUPT_ID,
(Xil_InterruptHandler)XDptx_HpdInterruptHandler, InstancePtr);
#endif /* XPAR_INTC_0_DEVICE_ID */
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Start the interrupt controller. */
#if defined(__MICROBLAZE__)
#ifdef XPAR_INTC_0_DEVICE_ID
Status = XIntc_Start(&IntcInstance, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIntc_Enable(&IntcInstance, IntrId);
#elif defined(__arm__)
XScuGic_Enable(&IntcInstance, IntrId);
#endif
XIntc_Enable(&IntcInstance, DP_INTERRUPT_ID);
#else
XScuGic_Enable(&IntcInstance, DP_INTERRUPT_ID);
#endif /* XPAR_INTC_0_DEVICE_ID */
/* Initialize the exception table. */
Xil_ExceptionInit();
/* Register the interrupt controller handler with the exception table. */
#if defined(__MICROBLAZE__)
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_InterruptHandler, &IntcInstance);
#elif defined(__arm__)
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
(Xil_ExceptionHandler)XScuGic_InterruptHandler, &IntcInstance);
#endif
(Xil_ExceptionHandler)INTC_HANDLER, &IntcInstance);
/* Enable exceptions. */
Xil_ExceptionEnable();
#if defined(__MICROBLAZE__)
/* Enable interrupts in the MicroBlaze processor. */
microblaze_enable_interrupts();
#endif
return XST_SUCCESS;
}
static void Dptx_InterruptHandler(XDptx *InstancePtr)
{
XDptx_HpdInterruptHandler(InstancePtr);
}
/******************************************************************************/
/**
* This function is called when a Hot-Plug-Detect (HPD) event is received by the
* DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK bit of the
* core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
* occurred.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note Use the XDptx_SetHpdEventHandler driver function to set this
* function as the handler for HPD pulses.
*
*******************************************************************************/
static void Dptx_HpdEventHandler(void *InstancePtr)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
if (XDptx_IsConnected(XDptx_InstancePtr)) {
xil_printf("+===> HPD connection event detected.\n");
Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE);
Dptx_Run(XDptx_InstancePtr);
}
else {
xil_printf("+===> HPD disconnection event detected.\n\n");
}
}
/******************************************************************************/
/**
* This function is called when a Hot-Plug-Detect (HPD) pulse is received by the
* DisplayPort TX core. The XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit
* of the core's XDPTX_INTERRUPT_STATUS register indicates that an HPD event has
* occurred.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note Use the XDptx_SetHpdPulseHandler driver function to set this
* function as the handler for HPD pulses.
*
*******************************************************************************/
static void Dptx_HpdPulseHandler(void *InstancePtr)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
xil_printf("===> HPD pulse detected.\n");
Dptx_Run(XDptx_InstancePtr, USE_LANE_COUNT, USE_LINK_RATE);
Dptx_Run(XDptx_InstancePtr);
}
/******************************************************************************/
/**
* This function is used to override the driver's default sleep functionality.
* For MicroBlaze systems, the XDptx_WaitUs driver function's default behavior
* is to use the MB_Sleep function from microblaze_sleep.h, which is implemented
* in software and only has millisecond accuracy. For this reason, using a
* hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is
* used - XDptx_WaitUs will ignore this custom timer handler.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note Use the XDptx_SetUserTimerHandler driver function to set this
* function as the handler for when the XDptx_WaitUs driver
* function is called.
*
*******************************************************************************/
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
@ -265,7 +320,7 @@ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds)
TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0);
}
while (TimerVal < (MicroSeconds *
(XDptx_InstancePtr->TxConfig.SAxiClkHz / 1000000)));
(XDptx_InstancePtr->Config.SAxiClkHz / 1000000)));
XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0);
}

100
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_poll_example.c
View file

@ -35,16 +35,16 @@
* @file xdptx_poll_example.c
*
* Contains a design example using the XDptx driver with polling. Once the
* polling detects a hot-plug-detect event (DisplayPort cable is plugged/
* polling detects a Hot-Plug-Detect event (HPD - DisplayPort cable is plugged/
* unplugged or the monitor is turned on/off), the main link will be trained.
*
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureVidgen - called in xdptx_example_common.c).
* See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
*
@ -62,20 +62,60 @@
#include "xdptx.h"
#include "xdptx_example_common.h"
#include "xil_printf.h"
#include "xparameters.h"
#include "xstatus.h"
/**************************** Constant Definitions ****************************/
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
/**************************** Function Prototypes *****************************/
u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId);
static void Dptx_HpdPoll(XDptx *InstancePtr);
/**************************** Function Definitions ****************************/
/******************************************************************************/
/**
* This function is the main function of the XDptx polling example.
*
* @param None.
*
* @return - XST_FAILURE if the polling example was unsuccessful - system
* setup failed.
*
* @note Unless setup failed, main will never return since
* Dptx_PollExample is blocking (it is continuously polling for
* Hot-Plug-Detect (HPD) events.
*
*******************************************************************************/
int main(void)
{
/* Run the XDptx polling example. */
Dptx_PollExample(&DptxInstance, DPTX_DEVICE_ID);
return XST_FAILURE;
}
/******************************************************************************/
/**
* The main entry point for the polling example using the XDptx driver. This
* function will set up the system. If this is successful, this example will
* begin polling the Hot-Plug-Detect (HPD) status registers for HPD events. Once
* a connection event or a pulse is detected, link training will commence (if
* needed) and a video stream will start being sent over the main link.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
*
* @return - XST_FAILURE if the system setup failed.
* - XST_SUCCESS should never return since this function, if setup
* was successful, is blocking.
*
* @note If system setup was successful, this function is blocking in
* order to illustrate polling taking place for HPD events.
*
*******************************************************************************/
u32 Dptx_PollExample(XDptx *InstancePtr, u16 DeviceId)
{
u32 Status;
@ -84,31 +124,36 @@ int main(void)
Dptx_PlatformInit();
/******************/
Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID);
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#if defined(TRAIN_ADAPTIVE)
XDptx_EnableTrainAdaptive(&DptxInstance, 1);
#else
XDptx_EnableTrainAdaptive(&DptxInstance, 0);
#endif
#if defined(TRAIN_HAS_REDRIVER)
XDptx_SetHasRedriverInPath(&DptxInstance, 1);
#else
XDptx_SetHasRedriverInPath(&DptxInstance, 0);
#endif
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
/* A receiver must be connected at this point. */
/* Continuously poll for HPD events. */
while (1) {
/* Continuously poll for HPD events. */
Dptx_HpdPoll(&DptxInstance);
Dptx_HpdPoll(InstancePtr);
}
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function polls the XDPTX_INTERRUPT_SIG_STATE and XDPTX_INTERRUPT_STATUS
* registers for Hot-Plug-Detect (HPD) events and handles them accordingly. If a
* connection or pulse event is detected, link training will begin (if required)
* and a video stream will be initiated.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
static void Dptx_HpdPoll(XDptx *InstancePtr)
{
u32 InterruptSignalState;
@ -119,9 +164,9 @@ static void Dptx_HpdPoll(XDptx *InstancePtr)
u32 HpdDuration;
/* Read interrupt registers. */
InterruptSignalState = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
InterruptSignalState = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_SIG_STATE);
InterruptStatus = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
InterruptStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_STATUS);
/* Check for HPD events. */
@ -131,7 +176,8 @@ static void Dptx_HpdPoll(XDptx *InstancePtr)
HpdPulseDetected = InterruptStatus &
XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK;
if (HpdPulseDetected) {
HpdDuration = XDptx_ReadReg(InstancePtr, XDPTX_HPD_DURATION);
HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_HPD_DURATION);
}
/* HPD event handling. */
@ -139,13 +185,13 @@ static void Dptx_HpdPoll(XDptx *InstancePtr)
xil_printf("+===> HPD connection event detected.\n");
/* Initiate link training. */
Dptx_Run(&DptxInstance, USE_LANE_COUNT, USE_LINK_RATE);
Dptx_Run(InstancePtr);
}
else if (HpdState && HpdPulseDetected && (HpdDuration >= 250)) {
xil_printf("===> HPD pulse detected.\n");
/* Re-train if needed. */
Dptx_Run(InstancePtr, USE_LANE_COUNT, USE_LINK_RATE);
Dptx_Run(InstancePtr);
}
else if (!HpdState && HpdEvent) {
xil_printf("+===> HPD disconnection event detected.\n\n");

20
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_selftest_example.c
View file

@ -56,13 +56,9 @@
#include "xparameters.h"
#include "xstatus.h"
/**************************** Constant Definitions ****************************/
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
/**************************** Function Prototypes *****************************/
static u32 Dptx_SelfTestExample(u16 DeviceId);
u32 Dptx_SelfTestExample(u16 DeviceId);
/**************************** Function Definitions ****************************/
@ -79,7 +75,7 @@ int main(void)
return Status;
}
static u32 Dptx_SelfTestExample(u16 DeviceId)
u32 Dptx_SelfTestExample(u16 DeviceId)
{
u32 Status;
@ -88,16 +84,8 @@ static u32 Dptx_SelfTestExample(u16 DeviceId)
return XST_FAILURE;
}
#if defined(TRAIN_ADAPTIVE)
XDptx_EnableTrainAdaptive(&DptxInstance, 1);
#else
XDptx_EnableTrainAdaptive(&DptxInstance, 0);
#endif
#if defined(TRAIN_HAS_REDRIVER)
XDptx_SetHasRedriverInPath(&DptxInstance, 1);
#else
XDptx_SetHasRedriverInPath(&DptxInstance, 0);
#endif
XDptx_EnableTrainAdaptive(&DptxInstance, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(&DptxInstance, TRAIN_HAS_REDRIVER);
/* Run the self test. */
Status = XDptx_SelfTest(&DptxInstance);

118
XilinxProcessorIPLib/drivers/dptx/examples/xdptx_timer_example.c
View file

@ -40,13 +40,14 @@
* the user may override the default MicroBlaze sleep with a function that will
* use the hardware timer.
*
* @note This example requires an AXI timer in the system.
* @note For this example to display output, the user will need to
* implement initialization of the system (Dptx_PlatformInit) and,
* after training is complete, implement configuration of the video
* stream source in order to provide the DisplayPort core with
* input (Dptx_ConfigureVidgen - called in xdptx_example_common.c).
* See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureVidgen are
* input (Dptx_ConfigureStreamSrc - called in
* xdptx_example_common.c). See XAPP1178 for reference.
* @note The functions Dptx_PlatformInit and Dptx_ConfigureStreamSrc are
* declared extern in xdptx_example_common.h and are left up to the
* user to implement.
*
@ -64,25 +65,71 @@
#include "xdptx.h"
#include "xdptx_example_common.h"
#include "xil_printf.h"
#include "xparameters.h"
#include "xstatus.h"
#include "xtmrctr.h"
/**************************** Constant Definitions ****************************/
#define DPTX_DEVICE_ID XPAR_DISPLAYPORT_0_DEVICE_ID
/**************************** Function Prototypes *****************************/
u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc);
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds);
/*************************** Variable Declarations ****************************/
XTmrCtr TimerCounterInst;
XTmrCtr TimerCounterInst; /* The timer counter instance. */
/**************************** Function Definitions ****************************/
/******************************************************************************/
/**
* This function is the main function of the XDptx timer example.
*
* @param None.
*
* @return - XST_SUCCESS if the timer example finished successfully.
* - XST_FAILURE otherwise.
*
* @note None.
*
*******************************************************************************/
int main(void)
{
int Status;
/* Run the XDptx timer example. */
Status = Dptx_TimerExample(&DptxInstance, DPTX_DEVICE_ID,
&TimerCounterInst, &Dptx_CustomWaitUs);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;
}
/******************************************************************************/
/**
* The main entry point for the timer example using the XDptx driver. This
* function will set up the system and the custom sleep handler. If this is
* successful, link training will commence and a video stream will start being
* sent over the main link.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param DeviceId is the unique device ID of the DisplayPort TX core
* instance.
* @param TimerCounterPtr is a pointer to the timer instance.
* @param UserSleepFunc is a pointer to the custom handler for sleep.
*
* @return - XST_SUCCESS if the system was set up correctly and link
* training was successful.
* - XST_FAILURE otherwise.
*
* @note None.
*
*******************************************************************************/
u32 Dptx_TimerExample(XDptx *InstancePtr, u16 DeviceId,
XTmrCtr *TimerCounterPtr, XDptx_TimerHandler UserSleepFunc)
{
u32 Status;
@ -91,35 +138,50 @@ int main(void)
Dptx_PlatformInit();
/*******************/
/* Set a custom timer handler for improved delay accuracy.
* Note: This only has an affect for MicroBlaze systems. */
XDptx_SetUserTimerHandler(&DptxInstance, &Dptx_CustomWaitUs,
&TimerCounterInst);
/* Set a custom timer handler for improved delay accuracy on MicroBlaze
* systems since the driver does not assume/have a dependency on the
* system having a timer in the FPGA.
* Note: This only has an affect for MicroBlaze systems since the Zynq
* ARM SoC contains a timer, which is used when the driver calls the
* delay function. */
XDptx_SetUserTimerHandler(InstancePtr, UserSleepFunc, TimerCounterPtr);
Status = Dptx_SetupExample(&DptxInstance, DPTX_DEVICE_ID);
Status = Dptx_SetupExample(InstancePtr, DeviceId);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
#if defined(TRAIN_ADAPTIVE)
XDptx_EnableTrainAdaptive(&DptxInstance, 1);
#else
XDptx_EnableTrainAdaptive(&DptxInstance, 0);
#endif
#if defined(TRAIN_HAS_REDRIVER)
XDptx_SetHasRedriverInPath(&DptxInstance, 1);
#else
XDptx_SetHasRedriverInPath(&DptxInstance, 0);
#endif
XDptx_EnableTrainAdaptive(InstancePtr, TRAIN_ADAPTIVE);
XDptx_SetHasRedriverInPath(InstancePtr, TRAIN_HAS_REDRIVER);
/* A receiver must be connected at this point. */
Dptx_Run(&DptxInstance, USE_LANE_COUNT, USE_LINK_RATE);
/* A sink monitor must be connected at this point. See the polling or
* interrupt examples for how to wait for a connection event. */
Status = Dptx_Run(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/* Do not return in order to keep the program running. */
while (1);
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function is used to override the driver's default sleep functionality.
* For MicroBlaze systems, the XDptx_WaitUs driver function's default behavior
* is to use the MB_Sleep function from microblaze_sleep.h, which is implemented
* in software and only has millisecond accuracy. For this reason, using a
* hardware timer is preferrable. For ARM/Zynq SoC systems, the SoC's timer is
* used - XDptx_WaitUs will ignore this custom timer handler.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note Use the XDptx_SetUserTimerHandler driver function to set this
* function as the handler for when the XDptx_WaitUs driver
* function is called.
*
*******************************************************************************/
static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds)
{
XDptx *XDptx_InstancePtr = (XDptx *)InstancePtr;
@ -132,7 +194,7 @@ static void Dptx_CustomWaitUs(void *InstancePtr, u32 MicroSeconds)
TimerVal = XTmrCtr_GetValue(XDptx_InstancePtr->UserTimerPtr, 0);
}
while (TimerVal < (MicroSeconds *
(XDptx_InstancePtr->TxConfig.SAxiClkHz / 1000000)));
(XDptx_InstancePtr->Config.SAxiClkHz / 1000000)));
XTmrCtr_Stop(XDptx_InstancePtr->UserTimerPtr, 0);
}

915
XilinxProcessorIPLib/drivers/dptx/src/xdptx.c
View file

File diff suppressed because it is too large Load diff

187
XilinxProcessorIPLib/drivers/dptx/src/xdptx.h
View file

@ -34,10 +34,121 @@
*
* @file xdptx.h
*
* The Xilinx DisplayPort transmitter (TX) driver.
* The Xilinx DisplayPort transmitter (DPTX) driver. This driver supports the
* Xilinx DisplayPort soft IP core in source (TX) mode.
*
* The Xilinx DisplayPort soft IP supports the following features:
* - 1, 2, or 4 lanes.
* - A link rate of 1.62, 2.70, or 5.40Gbps per lane.
* - 1, 2, or 4 pixel-wide video interfaces.
* - RGB and YCbCr color space.
* - Up to 16 bits per component.
* - Up to 4Kx2K monitor resolution.
* - Auto lane rate and width negotiation.
* - I2C over a 1Mb/s AUX channel.
* - Secondary channel audio support (2 channels).
* - 4 independent video multi-streams.
*
* The Xilinx DisplayPort soft IP does not support the following features:
* - The automated test feature.
* - Audio (3-8 channel).
* - FAUX.
* - Bridging function.
* - MST audio.
* - eDP optional features.
* - iDP.
* - GTC.
*
* <b>DisplayPort overview</b>
*
* A DisplayPort link consists of:
* - A unidirectional main link which is used to transport isochronous data
* streams such as video and audio. The main link may use 1, 2, or 4
* lanes at a link rate of 1.62, 2.70, or 5.40Gbps per lane. The link
* needs to be trained prior to sending streams.
* - An auxiliary (AUX) channel is a 1MBps bidirectional channel used for
* link training, link management, and device control.
* - A hot-plug-detect (HPD) signal line is used to determine whether a
* DisplayPort connection exists between the DisplayPort TX connector and
* an RX device. It is serves as an interrupt request by the RX device.
*
* <b>Driver description</b>
*
* The device driver enables higher-level software (e.g., an application) to
* configure and control a DisplayPort TX soft IP, communicate and control an
* RX device/sink monitor over the AUX channel, and to initialize and transmit
* data streams over the main link.
*
* This driver implements link layer functionality: a Link Policy Maker (LPM)
* and a Stream Policy Maker (SPM) as per the DisplayPort 1.2a specification.
* - The LPM manages the main link and is responsible for keeping the link
* synchronized. It will establish a link with a downstream RX device by
* undergoing a link training sequence which consists of:
* - Clock recovery: The clock needs to be recovered and PLLs need to be
* locked for all lanes.
* - Channel equalization: All lanes need to achieve channel equalization
* and and symbol lock, as well as for interlane alignment to take place.
* - The SPM manages transportation of an isochronous stream. That is, it will
* initialize and maintain a video stream, establish a virtual channel to a
* sink monitor, and transmit the stream.
*
* Using AUX transactions to read/write from/to the sink's DisplayPort
* Configuration Data (DPCD) address space, the LPM obtains the link
* capabilities, obtains link configuration and link and sink status, and
* configures and controls the link and sink. The main link is trained this way.
*
* I2C-over-AUX transactions are used to obtain the sink's Extended Display
* Identification Data (EDID) which give information on the display capabilities
* of the monitor. The SPM may use this information to determine what available
* screen resolutions and video timing are possible.
*
* <b>Device configuration</b>
*
* The device can be configured in various ways during the FPGA implementation
* process. Configuration parameters are stored in the xdptx_g.c file which is
* generated when compiling the board support package (BSP). A table is defined
* where each entry contains configuration information for the DisplayPort
* instances present in the system. This information includes parameters that
* are defined in the driver's data/dptx.tcl file such as the base address of
* the memory-mapped device and the maximum number of lanes, maximum link rate,
* and video interface that the DisplayPort instance supports, among others.
*
* <b>Interrupt processing</b>
*
* DisplayPort interrupts occur on the HPD signal line when the DisplayPort
* cable is connected/disconnected or when the RX device sends a pulse. The user
* hardware design must contain an interrupt controller which the DisplayPort
* TX instance's interrupt signal is connected to. The user application must
* enable interrupts in the system and set up the interrupt controller such that
* the XDptx_HpdInterruptHandler handler will service DisplayPort interrupts.
* When the XDptx_HpdInterruptHandler function is invoked, the handler will
* identify what type of DisplayPort interrupt has occurred, and will call
* either the HPD event handler function or the HPD pulse handler function,
* depending on whether a an HPD event on an HPD pulse event occurred.
*
* The DisplayPort Tx's XDPTX_INTERRUPT_STATUS register indicates the type of
* interrupt that has occured, and the XDptx_HpdInterruptHandler will use this
* information to decide which handler to call. An HPD event is identified if
* bit XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK is set, and an HPD pulse is
* identified from the XDPTX_INTERRUPT_STATUS_HPD_PULSE_DETECTED_MASK bit.
*
* The HPD event handler may be set up by using the XDptx_SetHpdEventHandler
* function and, for the HPD pulse handler, the XDptx_SetHpdPulseHandler
* function.
*
* <b>Asserts</b>
*
* Asserts are used within all Xilinx drivers to enforce constraints on argument
* values. Asserts can be turned off on a system-wide basis by defining, at
* compile time, the NDEBUG identifier. By default, asserts are turned on and
* it is recommended that application developers leave asserts on during
* development.
*
* The driver currently supports single-stream transport (SST) functionality.
*
* @note For a 5.4Gbps link rate, a high performance 7 series FPGA is
* required with a speed grade of -2 or -3.
*
* <pre>
* MODIFICATION HISTORY:
*
@ -61,12 +172,11 @@
/******************************************************************************/
/**
* This macro checks if there is a connected sink.
* This macro checks if there is a connected RX device.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return
* - TRUE if there is a connection.
* @return - TRUE if there is a connection.
* - FALSE if there is no connection.
*
* @note C-style signature:
@ -74,7 +184,7 @@
*
*******************************************************************************/
#define XDptx_IsConnected(InstancePtr) \
(XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr, \
(XDptx_ReadReg(InstancePtr->Config.BaseAddr, \
XDPTX_INTERRUPT_SIG_STATE) & XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK)
/****************************** Type Definitions ******************************/
@ -227,23 +337,27 @@ typedef struct {
} XDptx_Config;
/**
* This typedef contains configuration information about the sink.
* This typedef contains configuration information about the RX device.
*/
typedef struct {
u8 DpcdRxCapsField[XDPTX_DPCD_RECEIVER_CAP_FIELD_SIZE];
/**< The raw capabilities field
of the sink's DPCD. */
u8 Edid[XDPTX_EDID_SIZE]; /**< The sink's raw EDID. */
u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the receiver
DPCD's status registers. The
first 4 bytes correspond to the
lane status from the receiver's
DPCD associated with clock
recovery, channel equalization,
symbol lock, and interlane
alignment. The 2 remaining bytes
represent the adjustments
requested by the DPCD. */
of the RX device's DisplayPort
Configuration Data (DPCD). */
u8 Edid[XDPTX_EDID_SIZE]; /**< The RX device's raw Extended
Display Identification Data
(EDID). */
u8 LaneStatusAdjReqs[6]; /**< This is a raw read of the
RX device's status registers.
The first 4 bytes correspond to
the lane status associated with
clock recovery, channel
equalization, symbol lock, and
interlane alignment. The
remaining 2 bytes represent the
pre-emphasis and voltage swing
level adjustments requested by
the RX device. */
} XDptx_SinkConfig;
/**
@ -260,14 +374,14 @@ typedef struct {
use over the main link. */
u8 DownspreadControl; /**< Downspread control is currently in
use over the main link. */
u8 MaxLaneCount; /**< The maximum lane count of the
source-sink main link. */
u8 MaxLinkRate; /**< The maximum link rate of the
source-sink main link. */
u8 MaxLaneCount; /**< The maximum lane count of the main
link. */
u8 MaxLinkRate; /**< The maximum link rate of the main
link. */
u8 SupportEnhancedFramingMode; /**< Enhanced frame mode is supported by
the receiver. */
the RX device. */
u8 SupportDownspreadControl; /**< Downspread control is supported by
the receiver. */
the RX device. */
u8 VsLevel; /**< The current voltage swing level for
each lane. */
u8 PeLevel; /**< The current pre-emphasis/cursor
@ -334,7 +448,7 @@ typedef void (*XDptx_TimerHandler)(void *InstancePtr, u32 MicroSeconds);
/******************************************************************************/
/**
* Callback type which represents the handler for a hot-plug-detect event
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) event
* interrupt.
*
* @param InstancePtr is a pointer to the XDptx instance.
@ -344,7 +458,7 @@ typedef void (*XDptx_HpdEventHandler)(void *InstancePtr);
/******************************************************************************/
/**
* Callback type which represents the handler for a hot-plug-detect pulse
* Callback type which represents the handler for a Hot-Plug-Detect (HPD) pulse
* interrupt.
*
* @param InstancePtr is a pointer to the XDptx instance.
@ -366,10 +480,11 @@ typedef struct {
u8 HasRedriverInPath; /**< Redriver in path requires
different voltage swing
and pre-emphasis. */
XDptx_Config TxConfig; /**< Configuration structure for
the core. */
XDptx_Config Config; /**< Configuration structure for
the DisplayPort TX
core. */
XDptx_SinkConfig RxConfig; /**< Configuration structure for
the sink. */
the RX device. */
XDptx_LinkConfig LinkConfig; /**< Configuration structure for
the main link. */
XDptx_MainStreamAttributes MsaConfig; /**< Configuration structure for
@ -380,14 +495,14 @@ typedef struct {
void *UserTimerPtr; /**< Pointer to a timer instance
used by the custom user
delay/sleep function. */
XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for hot-
plug-detect event
XDptx_HpdEventHandler HpdEventHandler; /**< Callback function for Hot-
Plug-Detect (HPD) event
interrupts. */
void *HpdEventCallbackRef; /**< A pointer to the user data
passed to the HPD event
callback function.*/
XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for hot-
plug-detect pulse
XDptx_HpdPulseHandler HpdPulseHandler; /**< Callback function for Hot-
Plug-Detect (HPD) pulse
interrupts. */
void *HpdPulseCallbackRef; /**< A pointer to the user data
passed to the HPD pulse
@ -400,7 +515,7 @@ typedef struct {
u32 XDptx_InitializeTx(XDptx *InstancePtr);
void XDptx_CfgInitialize(XDptx *InstancePtr, XDptx_Config *ConfigPtr,
u32 EffectiveAddr);
u32 XDptx_GetSinkCapabilities(XDptx *InstancePtr);
u32 XDptx_GetRxCapabilities(XDptx *InstancePtr);
u32 XDptx_GetEdid(XDptx *InstancePtr);
/* xdptx.c: Link policy maker functions. */
@ -435,12 +550,12 @@ void XDptx_SetUserTimerHandler(XDptx *InstancePtr,
/* xdptx_spm.c: Stream policy maker functions. */
void XDptx_CfgMsaRecalculate(XDptx *InstancePtr);
u32 XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
XDptx_VideoMode VideoMode);
void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr);
void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
XDptx_MainStreamAttributes *MsaConfigCustom, u8 Recalculate);
u32 XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor);
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor);
void XDptx_SetVideoMode(XDptx *InstancePtr);
/* xdptx_intr.c: Interrupt handling functions. */

338
XilinxProcessorIPLib/drivers/dptx/src/xdptx_hw.h
View file

@ -60,7 +60,7 @@
/******************************************************************************/
/**
* Address mapping for the DPTX core.
* Address mapping for the DisplayPort TX core.
*
*******************************************************************************/
/** @name DPTX core registers: Link configuration field.
@ -86,9 +86,9 @@
* @{
*/
#define XDPTX_ENABLE 0x0080 /**< Enable the basic operations
of the transmitter or
output stuffing symbols
if disabled. */
of the DisplayPort TX
core or output stuffing
symbols if disabled. */
#define XDPTX_ENABLE_MAIN_STREAM 0x0084 /**< Enable transmission of main
link video info. */
#define XDPTX_ENABLE_SEC_STREAM 0x0088 /**< Enable the transmission of
@ -143,6 +143,8 @@
/** @name DPTX core registers: Main stream attributes for SST / MST STREAM1.
* @{
*/
#define XDPTX_STREAM1_MSA_START 0x0180 /**< Start of the MSA registers
for stream 1. */
#define XDPTX_MAIN_STREAM_HTOTAL 0x0180 /**< Total number of clocks in
the horizontal framing
period. */
@ -279,223 +281,45 @@
CEA 861-C info frame. */
#define XDPTX_TX_AUDIO_MAUD 0x0328 /**< M value of audio stream
as computed by the
transmitter when audio
clock and link clock are
synchronous. */
DisplayPort TX core when
audio and link clocks
are synchronous. */
#define XDPTX_TX_AUDIO_NAUD 0x032C /**< N value of audio stream
as computed by the
transmitter when audio
clock and link clock are
synchronous. */
DisplayPort TX core when
audio and link clocks
are synchronous. */
#define XDPTX_TX_AUDIO_EXT_DATA 0x0330 /**< Word formatted as per
extension packet. */
/* @} */
/** @name DPTX core registers: Main stream attributes for MST STREAM2.
/** @name DPTX core registers: Main stream attributes for MST STREAM2, 3, and 4.
* @{
*/
#define XDPTX_MAIN_STREAM2_HTOTAL 0x0500 /**< Total number of clocks in
the horizontal framing
period. */
#define XDPTX_MAIN_STREAM2_VTOTAL 0x0504 /**< Total number of lines in
the video frame. */
#define XDPTX_MAIN_STREAM2_POLARITY 0x0508 /**< Polarity for the video sync
signals. */
#define XDPTX_MAIN_STREAM2_HSWIDTH 0x050C /**< Width of the horizontal
sync pulse. */
#define XDPTX_MAIN_STREAM2_VSWIDTH 0x0510 /**< Width of the vertical sync
pulse. */
#define XDPTX_MAIN_STREAM2_HRES 0x0514 /**< Number of active pixels per
line (the horizontal
resolution). */
#define XDPTX_MAIN_STREAM2_VRES 0x0518 /**< Number of active lines (the
vertical resolution). */
#define XDPTX_MAIN_STREAM2_HSTART 0x051C /**< Number of clocks between
the leading edge of the
horizontal sync and the
start of active data. */
#define XDPTX_MAIN_STREAM2_VSTART 0x0520 /**< Number of lines between the
leading edge of the
vertical sync and the
first line of active
data. */
#define XDPTX_MAIN_STREAM2_MISC0 0x0524 /**< Miscellaneous stream
attributes. */
#define XDPTX_MAIN_STREAM2_MISC1 0x0528 /**< Miscellaneous stream
attributes. */
#define XDPTX_M_VID_STREAM2 0x052C /**< M value for the video
stream as computed by
the source core in
asynchronous clock mode.
Must be written in
synchronous mode. */
#define XDPTX_TU_SIZE_STREAM2 0x0530 /**< Size of a transfer unit in
the framing logic. */
#define XDPTX_N_VID_STREAM2 0x0534 /**< N value for the video
stream as computed by
the source core in
asynchronous clock mode.
Must be written in
synchronous mode. */
#define XDPTX_USER_PIXEL_WIDTH_STREAM2 0x0538 /**< Selects the width of the
user data input port. */
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM2 \
0x053C /**< Used to translate the
number of pixels per
line to the native
internal 16-bit
datapath. */
#define XDPTX_MAIN_STREAM2_INTERLACED 0x0540 /**< Video is interlaced. */
#define XDPTX_MIN_BYTES_PER_TU_STREAM2 0x0544 /**< The minimum number of bytes
per transfer unit. */
#define XDPTX_FRAC_BYTES_PER_TU_STREAM2 0x0548 /**< The fractional component
when calculated the
XDPTX_MIN_BYTES_PER_TU
register value. */
#define XDPTX_INIT_WAIT_STREAM2 0x054C /**< Number of initial wait
cycles at the start of a
new line by the framing
logic, allowing enough
data to be buffered in
the input FIFO. */
/* @} */
/** @name DPTX core registers: Main stream attributes for MST STREAM3.
* @{
*/
#define XDPTX_MAIN_STREAM3_HTOTAL 0x0550 /**< Total number of clocks in
the horizontal framing
period. */
#define XDPTX_MAIN_STREAM3_VTOTAL 0x0554 /**< Total number of lines in
the video frame. */
#define XDPTX_MAIN_STREAM3_POLARITY 0x0558 /**< Polarity for the video sync
signals. */
#define XDPTX_MAIN_STREAM3_HSWIDTH 0x055C /**< Width of the horizontal
sync pulse. */
#define XDPTX_MAIN_STREAM3_VSWIDTH 0x0560 /**< Width of the vertical sync
pulse. */
#define XDPTX_MAIN_STREAM3_HRES 0x0564 /**< Number of active pixels per
line (the horizontal
resolution). */
#define XDPTX_MAIN_STREAM3_VRES 0x0568 /**< Number of active lines (the
vertical resolution). */
#define XDPTX_MAIN_STREAM3_HSTART 0x056C /**< Number of clocks between
the leading edge of the
horizontal sync and the
start of active data. */
#define XDPTX_MAIN_STREAM3_VSTART 0x0570 /**< Number of lines between the
leading edge of the
vertical sync and the
first line of active
data. */
#define XDPTX_MAIN_STREAM3_MISC0 0x0574 /**< Miscellaneous stream
attributes. */
#define XDPTX_MAIN_STREAM3_MISC1 0x0578 /**< Miscellaneous stream
attributes. */
#define XDPTX_M_VID_STREAM3 0x057C /**< M value for the video
stream as computed by
the source core in
asynchronous clock mode.
Must be written in
synchronous mode. */
#define XDPTX_TU_SIZE_STREAM3 0x0580 /**< Size of a transfer unit in
the framing logic. */
#define XDPTX_N_VID_STREAM3 0x0584 /**< N value for the video
stream as computed by
the source core in
asynchronous clock mode.
Must be written in
synchronous mode. */
#define XDPTX_USER_PIXEL_WIDTH_STREAM3 0x0588 /**< Selects the width of the
user data input port. */
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM3 \
0x058C /**< Used to translate the
number of pixels per
line to the native
internal 16-bit
datapath. */
#define XDPTX_MAIN_STREAM3_INTERLACED 0x0590 /**< Video is interlaced. */
#define XDPTX_MIN_BYTES_PER_TU_STREAM3 0x0594 /**< The minimum number of bytes
per transfer unit. */
#define XDPTX_FRAC_BYTES_PER_TU_STREAM3 0x0598 /**< The fractional component
when calculated the
XDPTX_MIN_BYTES_PER_TU
register value. */
#define XDPTX_INIT_WAIT_STREAM3 0x059C /**< Number of initial wait
cycles at the start of a
new line by the framing
logic, allowing enough
data to be buffered in
the input FIFO. */
/* @} */
/** @name DPTX core registers: Main stream attributes for MST STREAM4.
* @{
*/
#define XDPTX_MAIN_STREAM4_HTOTAL 0x05A0 /**< Total number of clocks in
the horizontal framing
period. */
#define XDPTX_MAIN_STREAM4_VTOTAL 0x05A4 /**< Total number of lines in
the video frame. */
#define XDPTX_MAIN_STREAM4_POLARITY 0x05A8 /**< Polarity for the video sync
signals. */
#define XDPTX_MAIN_STREAM4_HSWIDTH 0x05AC /**< Width of the horizontal
sync pulse. */
#define XDPTX_MAIN_STREAM4_VSWIDTH 0x05B0 /**< Width of the vertical sync
pulse. */
#define XDPTX_MAIN_STREAM4_HRES 0x05B4 /**< Number of active pixels per
line (the horizontal
resolution). */
#define XDPTX_MAIN_STREAM4_VRES 0x05B8 /**< Number of active lines (the
vertical resolution). */
#define XDPTX_MAIN_STREAM4_HSTART 0x05BC /**< Number of clocks between
the leading edge of the
horizontal sync and the
start of active data. */
#define XDPTX_MAIN_STREAM4_VSTART 0x05C0 /**< Number of lines between the
leading edge of the
vertical sync and the
first line of active
data. */
#define XDPTX_MAIN_STREAM4_MISC0 0x05C4 /**< Miscellaneous stream
attributes. */
#define XDPTX_MAIN_STREAM4_MISC1 0x05C8 /**< Miscellaneous stream
attributes. */
#define XDPTX_M_VID_STREAM4 0x05CC /**< M value for the video
stream as computed by
the source core in
asynchronous clock mode.
Must be written in
synchronous mode. */
#define XDPTX_TU_SIZE_STREAM4 0x05D0 /**< Size of a transfer unit in
the framing logic. */
#define XDPTX_N_VID_STREAM4 0x05D4 /**< N value for the video
stream as computed by
the source core in
asynchronous clock mode.
Must be written in
synchronous mode. */
#define XDPTX_USER_PIXEL_WIDTH_STREAM4 0x05D8 /**< Selects the width of the
user data input port. */
#define XDPTX_USER_DATA_COUNT_PER_LANE_STREAM4 \
0x05DC /**< Used to translate the
number of pixels per
line to the native
internal 16-bit
datapath. */
#define XDPTX_MAIN_STREAM4_INTERLACED 0x05E0 /**< Video is interlaced. */
#define XDPTX_MIN_BYTES_PER_TU_STREAM4 0x05E4 /**< The minimum number of bytes
per transfer unit. */
#define XDPTX_FRAC_BYTES_PER_TU_STREAM4 0x05E8 /**< The fractional component
when calculated the
XDPTX_MIN_BYTES_PER_TU
register value. */
#define XDPTX_INIT_WAIT_STREAM4 0x05EC /**< Number of initial wait
cycles at the start of a
new line by the framing
logic, allowing enough
data to be buffered in
the input FIFO. */
#define XDPTX_STREAM2_MSA_START 0x0500 /**< Start of the MSA registers
for stream 2. */
#define XDPTX_STREAM2_MSA_START_OFFSET (XDPTX_STREAM2_MSA_START - \
XDPTX_STREAM1_MSA_START) /**< The MSA registers for
stream 2 are at an
offset from the
corresponding registers
of stream 1. */
#define XDPTX_STREAM3_MSA_START 0x0550 /**< Start of the MSA registers
for stream 3. */
#define XDPTX_STREAM3_MSA_START_OFFSET (XDPTX_STREAM3_MSA_START - \
XDPTX_STREAM1_MSA_START) /**< The MSA registers for
stream 2 are at an
offset from the
corresponding registers
of stream 1. */
#define XDPTX_STREAM4_MSA_START 0x05A0 /**< Start of the MSA registers
for stream 4. */
#define XDPTX_STREAM4_MSA_START_OFFSET (XDPTX_STREAM4_MSA_START - \
XDPTX_STREAM1_MSA_START) /**< The MSA registers for
stream 2 are at an
offset from the
corresponding registers
of stream 1. */
/* @} */
#define XDPTX_VC_PAYLOAD_BUFFER_ADDR 0x0800 /**< Virtual channel payload
@ -510,6 +334,10 @@
#define XDPTX_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */
#define XDPTX_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */
#define XDPTX_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */
/* 0x001: LANE_COUNT_SET */
#define XDPTX_LANE_COUNT_SET_1 0x01 /**< Lane count of 1. */
#define XDPTX_LANE_COUNT_SET_2 0x02 /**< Lane count of 2. */
#define XDPTX_LANE_COUNT_SET_4 0x04 /**< Lane count of 4. */
/* 0x00C: TRAINING_PATTERN_SET */
#define XDPTX_TRAINING_PATTERN_SET_OFF 0x0 /**< Training off. */
#define XDPTX_TRAINING_PATTERN_SET_TP1 0x1 /**< Training pattern 1 used for
@ -722,7 +550,7 @@
4 /**< Shift bits for the internal
AUX reply state machine
status. */
/* 0x188, 0x508, 0x558, 0x5A8: MAIN_STREAM[0-4]_POLARITY */
/* 0x188, 0x508, 0x558, 0x5A8: MAIN_STREAM[1-4]_POLARITY */
#define XDPTX_MAIN_STREAMX_POLARITY_HSYNC_POL_MASK \
0x00000001 /**< Polarity of the horizontal
sync pulse. */
@ -733,7 +561,7 @@
1 /**< Shift bits for polarity of
the vertical sync
pulse. */
/* 0x1A4, 0x524, 0x578, 0x5C8: MAIN_STREAM[0-4]_MISC0 */
/* 0x1A4, 0x524, 0x574, 0x5C4: MAIN_STREAM[1-4]_MISC0 */
#define XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK \
0x00000001 /**< Synchronous clock. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_MASK \
@ -741,6 +569,15 @@
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT \
1 /**< Shift bits for component
format. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_RGB \
0x0 /**< Stream's component format
is RGB. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422 \
0x1 /**< Stream's component format
is YcbCr 4:2:2. */
#define XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR444 \
0x2 /**< Stream's component format
is YcbCr 4:4:4. */
#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_MASK \
0x00000008 /**< Dynamic range. */
#define XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT \
@ -756,7 +593,17 @@
component (BDC). */
#define XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT \
5 /**< Shift bits for BDC.*/
/* 0x1A8, 0x528, 0x5C8: MAIN_STREAM[0-4]_MISC1 */
#define XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC \
0x0 /**< 6 bits per component.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC \
0x1 /**< 8 bits per component.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC \
0x2 /**< 10 bits per component.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC \
0x3 /**< 12 bits per component.*/
#define XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC \
0x4 /**< 16 bits per component.*/
/* 0x1A8, 0x528, 0x578, 0x5C8: MAIN_STREAM[1-4]_MISC1 */
#define XDPTX_MAIN_STREAMX_MISC1_INTERLACED_VTOTAL_GIVEN_MASK \
0x00000001 /**< Interlaced vertical total
even. */
@ -877,11 +724,12 @@
/******************************************************************************/
/**
* Address mapping for the DPCD of the downstream device.
* Address mapping for the DisplayPort Configuration Data (DPCD) of the
* downstream device.
*
*******************************************************************************/
/** @name DPCD: Receiver capability field.
*
/** @name DisplayPort Configuration Data: Receiver capability field.
* @{
*/
#define XDPTX_DPCD_REV 0x00000
#define XDPTX_DPCD_MAX_LINK_RATE 0x00001
@ -930,8 +778,8 @@
#define XDPTX_DPCD_DOWNSP_3_DET_CAP 0x0008C
/* @} */
/** @name DPCD: Link configuration field.
*
/** @name DisplayPort Configuration Data: Link configuration field.
* @{
*/
#define XDPTX_DPCD_LINK_BW_SET 0x00100
#define XDPTX_DPCD_LANE_COUNT_SET 0x00101
@ -973,8 +821,8 @@
#define XDPTX_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2
/* @} */
/** @name DPCD: Link/sink status field.
*
/** @name DisplayPort Configuration Data: Link/sink status field.
* @{
*/
#define XDPTX_DPCD_SINK_COUNT 0x00200
#define XDPTX_DPCD_DEVICE_SERVICE_IRQ 0x00201
@ -996,7 +844,7 @@
#define XDPTX_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x00216
/* @} */
/** @name DPCD: Automated testing sub-field.
/** @name DisplayPort Configuration Data: Automated testing sub-field.
* @{
*/
#define XDPTX_DPCD_FAUX_FORWARD_CH_STATUS 0x00280
@ -1007,13 +855,13 @@
(XDPTX_DPCD_PAYLOAD_TABLE_UPDATE_STATUS + SlotNum)
/* @} */
/** @name DPCD: Sink control field.
/** @name DisplayPort Configuration Data: Sink control field.
* @{
*/
#define XDPTX_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600
/* @} */
/** @name DPCD: Sideband MSG buffers.
/** @name DisplayPort Configuration Data: Sideband message buffers.
* @{
*/
#define XDPTX_DPCD_DOWN_REQ 0x01000
@ -1022,7 +870,7 @@
#define XDPTX_DPCD_UP_REQ 0x01600
/* @} */
/** @name DPCD: Event status indicator field.
/** @name DisplayPort Configuration Data: Event status indicator field.
* @{
*/
#define XDPTX_DPCD_SINK_COUNT_ESI 0x02002
@ -1035,7 +883,7 @@
#define XDPTX_DPCD_SINK_STATUS_ESI 0x0200F
/* @} */
/** @name DPCD: Field addresses and sizes.
/** @name DisplayPort Configuration Data: Field addresses and sizes.
* @{
*/
#define XDPTX_DPCD_RECEIVER_CAP_FIELD_START XDPTX_DPCD_REV
@ -1048,8 +896,9 @@
/******************************************************************************/
/** @name DPCD: Receiver capability field masks, shifts, and register values.
*
/** @name DisplayPort Configuration Data: Receiver capability field masks,
* shifts, and register values.
* @{
*/
/* 0x00000: DPCD_REV */
#define XDPTX_DPCD_REV_MNR_MASK 0x0F
@ -1061,6 +910,9 @@
#define XDPTX_DPCD_MAX_LINK_RATE_540GBPS 0x14
/* 0x00002: MAX_LANE_COUNT */
#define XDPTX_DPCD_MAX_LANE_COUNT_MASK 0x1F
#define XDPTX_DPCD_MAX_LANE_COUNT_1 0x01
#define XDPTX_DPCD_MAX_LANE_COUNT_2 0x02
#define XDPTX_DPCD_MAX_LANE_COUNT_4 0x04
#define XDPTX_DPCD_TPS3_SUPPORT_MASK 0x40
#define XDPTX_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80
/* 0x00003: MAX_DOWNSPREAD */
@ -1132,8 +984,9 @@
#define XDPTX_DPCD_DOWNSP_X_DCAP_DVI_HCD_MASK 0x04
/* @} */
/** @name DPCD: Link configuration field masks, shifts, and register values.
*
/** @name DisplayPort Configuration Data: Link configuration field masks,
* shifts, and register values.
* @{
*/
/* 0x00100: XDPTX_DPCD_LINK_BW_SET */
#define XDPTX_DPCD_LINK_BW_SET_162GBPS 0x06
@ -1141,6 +994,9 @@
#define XDPTX_DPCD_LINK_BW_SET_540GBPS 0x14
/* 0x00101: LANE_COUNT_SET */
#define XDPTX_DPCD_LANE_COUNT_SET_MASK 0x1F
#define XDPTX_DPCD_LANE_COUNT_SET_1 0x01
#define XDPTX_DPCD_LANE_COUNT_SET_2 0x02
#define XDPTX_DPCD_LANE_COUNT_SET_4 0x04
#define XDPTX_DPCD_ENHANCED_FRAME_EN_MASK 0x80
/* 0x00102: TP_SET */
#define XDPTX_DPCD_TP_SEL_MASK 0x03
@ -1184,8 +1040,9 @@
#define XDPTX_DPCD_UP_IS_SRC_MASK 0x03
/* @} */
/** @name DPCD: Link/sink status field masks, shifts, and register values.
*
/** @name DisplayPort Configuration Data: Link/sink status field masks, shifts,
* and register values.
* @{
*/
/* 0x00202: STATUS_LANE_0_1 */
#define XDPTX_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01
@ -1234,10 +1091,11 @@
/******************************************************************************/
/**
* Address mapping for the EDID of the downstream device.
* Address mapping for the Extended Display Identification Data (EDID) of the
* downstream device.
*
*******************************************************************************/
/** @name EDID: Field addresses and sizes.
/** @name Extended Display Identification Data: Field addresses and sizes.
* @{
*/
#define XDPTX_EDID_ADDR 0x50
@ -1246,7 +1104,8 @@
#define XDPTX_EDID_PTM XDPTX_EDID_DTD_DD(0)
/* @} */
/** @name EDID: Register offsets for the DTD (detailed timing descriptor).
/** @name Extended Display Identification Data: Register offsets for the
* Detailed Timing Descriptor (DTD).
* @{
*/
#define XDPTX_EDID_DTD_PIXEL_CLK_KHZ_LSB 0x00
@ -1268,7 +1127,8 @@
#define XDPTX_EDID_DTD_VBORDER 0x10
#define XDPTX_EDID_DTD_SIGNAL 0x11
/** @name EDID: Masks, shifts, and register values.
/** @name Extended Display Identification Data: Masks, shifts, and register
* values.
* @{
*/
#define XDPTX_EDID_DTD_XRES_XBLANK_U4_XBLANK_MASK 0x0F
@ -1326,6 +1186,8 @@
* @param RegOffset is the register offset to write to.
* @param Data is the 32-bit data to write to the specified register.
*
* @return None.
*
* @note C-style signature:
* void XDptx_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
*

20
XilinxProcessorIPLib/drivers/dptx/src/xdptx_intr.c
View file

@ -36,6 +36,8 @@
*
* This file contains functions related to XDptx interrupt handling.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
@ -62,6 +64,10 @@
* @param CallbackRef is the user data item that will be passed to the
* callback function when it is invoked.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
XDptx_HpdEventHandler CallbackFunc, void *CallbackRef)
@ -85,6 +91,10 @@ void XDptx_SetHpdEventHandler(XDptx *InstancePtr,
* @param CallbackRef is the user data item that will be passed to the
* callback function when it is invoked.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
XDptx_HpdPulseHandler CallbackFunc, void *CallbackRef)
@ -107,6 +117,10 @@ void XDptx_SetHpdPulseHandler(XDptx *InstancePtr,
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
{
@ -120,9 +134,9 @@ void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
/* Determine what kind of interrupt occurred.
* Note: XDPTX_INTERRUPT_STATUS is an RC (read-clear) register. */
IntrStatus = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
IntrStatus = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_STATUS);
IntrStatus &= ~XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
IntrStatus &= ~XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_INTERRUPT_MASK);
HpdEventDetected = IntrStatus & XDPTX_INTERRUPT_STATUS_HPD_EVENT_MASK;
@ -136,7 +150,7 @@ void XDptx_HpdInterruptHandler(XDptx *InstancePtr)
if (HpdPulseDetected) {
/* The source device must debounce the incoming HPD signal by
* sampling the value at an interval greater than 250 ms. */
HpdDuration = XDptx_ReadReg(InstancePtr->TxConfig.BaseAddr,
HpdDuration = XDptx_ReadReg(InstancePtr->Config.BaseAddr,
XDPTX_HPD_DURATION);
if (HpdDuration >= 250) {
InstancePtr->HpdPulseHandler(

16
XilinxProcessorIPLib/drivers/dptx/src/xdptx_selftest.c
View file

@ -36,6 +36,8 @@
*
* This file contains a diagnostic self-test function for the XDptx driver.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
@ -57,16 +59,17 @@
/**
* This function runs a self-test on the XDptx driver/device. The test attempts
* to intialize the DisplayPort TX core, train the main link at the highest
* common capabilities between the core and the sink, and checks the status
* common capabilities between the core and the RX device, and checks the status
* of the link after training.
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return
* - XST_SUCCESS if the self-test passed. The main link has been
* @return - XST_SUCCESS if the self-test passed. The main link has been
* trained and established successfully.
* - XST_FAILURE otherwise.
*
* @note None.
*
*******************************************************************************/
u32 XDptx_SelfTest(XDptx *InstancePtr)
{
@ -77,8 +80,9 @@ u32 XDptx_SelfTest(XDptx *InstancePtr)
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
/* Obtain the capabilities of the sink by reading the DPCD. */
Status = XDptx_GetSinkCapabilities(InstancePtr);
/* Obtain the capabilities of the RX device by reading the DisplayPort
* Configuration Data (DPCD). */
Status = XDptx_GetRxCapabilities(InstancePtr);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
@ -90,7 +94,7 @@ u32 XDptx_SelfTest(XDptx *InstancePtr)
}
/* Attempt to establish a link at the maximum common capabilities
* between the DisplayPort TX core and the sink. */
* between the DisplayPort TX core and the RX device. */
XDptx_EstablishLink(InstancePtr);
/* Return whether or not the link has been successfully trained. */

4
XilinxProcessorIPLib/drivers/dptx/src/xdptx_sinit.c
View file

@ -36,6 +36,8 @@
*
* This file contains static initialization methods for the XDptx driver.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
@ -72,6 +74,8 @@ extern XDptx_Config XDptx_ConfigTable[XPAR_XDPTX_NUM_INSTANCES];
* @return A pointer to the configuration table entry corresponding to the
* given device ID, or NULL if no match is found.
*
* @note None.
*
*******************************************************************************/
XDptx_Config *XDptx_LookupConfig(u16 DeviceId)
{

268
XilinxProcessorIPLib/drivers/dptx/src/xdptx_spm.c
View file

@ -38,6 +38,8 @@
* These functions set up the DisplayPort TX core's main stream attributes that
* determine how a video stream will be displayed.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*
@ -64,7 +66,7 @@ static void XDptx_SetMsaValues(XDptx *InstancePtr,
/******************************************************************************/
/**
* This function calculates the following main stream attributes:
* This function calculates the following Main Stream Attributes (MSA):
* - Transfer unit size
* - User pixel width
* - NVid
@ -93,6 +95,8 @@ static void XDptx_SetMsaValues(XDptx *InstancePtr,
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note The MsaConfig structure is modified with the new, calculated
* values. The main stream attributes that were used to derive the
* calculated values are untouched in the MsaConfig structure.
@ -107,16 +111,35 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((LinkConfig->LinkRate == XDPTX_LINK_BW_SET_162GBPS) ||
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ||
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS));
Xil_AssertVoid((LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_1) ||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_2) ||
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4));
Xil_AssertVoid((LinkConfig->SynchronousClockMode == 0) ||
(LinkConfig->SynchronousClockMode == 1));
Xil_AssertVoid((LinkConfig->DynamicRange == 0) ||
(LinkConfig->DynamicRange == 1));
Xil_AssertVoid((LinkConfig->YCbCrColorimetry == 0) ||
(LinkConfig->YCbCrColorimetry == 1));
Xil_AssertVoid((MsaConfig->BitsPerColor == 6) ||
(MsaConfig->BitsPerColor == 8) ||
(MsaConfig->BitsPerColor == 10) ||
(MsaConfig->BitsPerColor == 12) ||
(MsaConfig->BitsPerColor == 16));
/* For SST. */
/* Fixed transfer unit size. */
MsaConfig->TransferUnitSize = 64;
/* Set the user pixel width to handle clocks that exceed the
* capabilities of the DisplayPort TX core. */
if ((MsaConfig->MVid > 150000) && (LinkConfig->LaneCount == 4)) {
if ((MsaConfig->MVid > 300000) &&
(LinkConfig->LaneCount == XDPTX_LANE_COUNT_SET_4)) {
MsaConfig->UserPixelWidth = 4;
}
else if ((MsaConfig->MVid > 80000) && (LinkConfig->LaneCount == 2)) {
else if ((MsaConfig->MVid > 75000) &&
(LinkConfig->LaneCount != XDPTX_LANE_COUNT_SET_1)) {
MsaConfig->UserPixelWidth = 2;
}
else {
@ -124,11 +147,7 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
}
/* Compute the rest of the MSA values. */
MsaConfig->NVid = (LinkConfig->LinkRate == XDPTX_LINK_BW_SET_540GBPS) ?
540000 :
(LinkConfig->LinkRate == XDPTX_LINK_BW_SET_270GBPS) ?
270000 :
162000;
MsaConfig->NVid = 27 * 1000 * LinkConfig->LinkRate;
MsaConfig->HStart = MsaConfig->HSyncPulseWidth + MsaConfig->HBackPorch;
MsaConfig->VStart = MsaConfig->VSyncPulseWidth + MsaConfig->VBackPorch;
MsaConfig->HClkTotal = (MsaConfig->HSyncPulseWidth +
@ -137,32 +156,51 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
MsaConfig->VClkTotal = (MsaConfig->VSyncPulseWidth +
MsaConfig->VBackPorch + MsaConfig->VFrontPorch +
MsaConfig->VResolution);
MsaConfig->Misc0 = (MsaConfig->BitsPerColor == 6) ? 0x00 :
(MsaConfig->BitsPerColor == 8) ? 0x01 :
(MsaConfig->BitsPerColor == 10) ? 0x02 :
(MsaConfig->BitsPerColor == 12) ? 0x03 :
(MsaConfig->BitsPerColor == 16) ? 0x04 :
0x00;
MsaConfig->Misc0 = MsaConfig->Misc0 <<
XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT;
MsaConfig->Misc0 = MsaConfig->Misc0 | (LinkConfig->ComponentFormat <<
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
(LinkConfig->DynamicRange <<
XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
/* Miscellaneous attributes. */
if (MsaConfig->BitsPerColor == 6) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_6BPC;
}
else if (MsaConfig->BitsPerColor == 8) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_8BPC;
}
else if (MsaConfig->BitsPerColor == 10) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_10BPC;
}
else if (MsaConfig->BitsPerColor == 12) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_12BPC;
}
else if (MsaConfig->BitsPerColor == 16) {
MsaConfig->Misc0 = XDPTX_MAIN_STREAMX_MISC0_BDC_16BPC;
}
MsaConfig->Misc0 = (MsaConfig->Misc0 <<
XDPTX_MAIN_STREAMX_MISC0_BDC_SHIFT) |
(LinkConfig->YCbCrColorimetry <<
XDPTX_MAIN_STREAMX_MISC0_YCBCR_COLORIMETRY_SHIFT) |
(LinkConfig->SynchronousClockMode &
XDPTX_MAIN_STREAMX_MISC0_SYNC_CLK_MASK);
(LinkConfig->DynamicRange <<
XDPTX_MAIN_STREAMX_MISC0_DYNAMIC_RANGE_SHIFT) |
(LinkConfig->ComponentFormat <<
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_SHIFT) |
(LinkConfig->SynchronousClockMode);
MsaConfig->Misc1 = 0;
MsaConfig->DataPerLane = (MsaConfig->HResolution *
MsaConfig->BitsPerColor * 3 / 16) - LinkConfig->LaneCount;
/* If RGB | YCbCr444, * 3 ; If YCbCr422, * 2 ; If YOnly, * 1. */
BitsPerPixel = (LinkConfig->ComponentFormat == 1) ?
MsaConfig->BitsPerColor * 2 :
MsaConfig->BitsPerColor * 3;
VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8;
/* Determine the number of bits per pixel for the specified color
* component format. */
if (LinkConfig->ComponentFormat ==
XDPTX_MAIN_STREAMX_MISC0_COMPONENT_FORMAT_YCBCR422) {
/* YCbCr422 color component format. */
BitsPerPixel = MsaConfig->BitsPerColor * 2;
}
else {
/* RGB or YCbCr 4:4:4 color component format. */
BitsPerPixel = MsaConfig->BitsPerColor * 3;
}
/* Calculate the transfer unit size. */
VideoBw = (MsaConfig->MVid * BitsPerPixel) / 8;
MsaConfig->AvgBytesPerTU = (VideoBw * MsaConfig->TransferUnitSize) /
(LinkConfig->LaneCount * (MsaConfig->NVid / 1000));
@ -184,39 +222,32 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr)
/******************************************************************************/
/**
* This function sets the main stream attribute values in the configuration
* structure to match one of the standard display mode timings from the
* XDptx_DmtModes[] table. THe XDptx_VideoMode enumeration in xdptx.h lists
* the available video modes.
* This function sets the Main Stream Attribute (MSA) values in the
* configuration structure to match one of the standard display mode timings
* from the XDptx_DmtModes[] standard Display Monitor Timing (DMT) table. The
* XDptx_VideoMode enumeration in xdptx.h lists the available video modes.
*
* @param InstancePtr is a pointer to the XDptx instance.
* @param VideoMode is one of the enumerated standard video modes that is
* used to determine the main stream attributes to be used.
* used to determine the MSA values to be used.
*
* @return
* - XST_INVALID_PARAM if the supplied video mode isn't in the DMT
* table.
* - XST_SUCCESS otherwise.
* @return None.
*
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* main stream attribute values associated to the specified video
* mode.
* MSA values associated to the specified video mode.
*
*******************************************************************************/
u32 XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
void XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
XDptx_VideoMode VideoMode)
{
XDptx_MainStreamAttributes *MsaConfig = &InstancePtr->MsaConfig;
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(VideoMode <= XDPTX_VM_LAST);
if (VideoMode > XDPTX_VM_LAST) {
return XST_INVALID_PARAM;
}
/* Configure the main stream attribute values from the display monitor
* timing (DMT) table. */
/* Configure the MSA values from the display monitor DMT table. */
MsaConfig->MVid = XDptx_DmtModes[VideoMode].PixelClkKhz;
MsaConfig->HSyncPolarity = XDptx_DmtModes[VideoMode].HSyncPolarity;
MsaConfig->VSyncPolarity = XDptx_DmtModes[VideoMode].VSyncPolarity;
@ -231,19 +262,19 @@ u32 XDptx_CfgMsaUseStandardVideoMode(XDptx *InstancePtr,
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
return XST_SUCCESS;
}
/******************************************************************************/
/**
* This function sets the main stream attribute values in the configuration
* structure to match the preferred timing of the sink monitor. This preferred
* timing information is stored in the sink's extended display identification
* data (EDID).
* structure to match the preferred timing of the sink monitor. This Preferred
* Timing Mode (PTM) information is stored in the sink's Extended Display
* Identification Data (EDID).
*
* @param InstancePtr is a pointer to the XDptx instance
*
* @return None.
*
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* main stream attribute values associated to the preferred timing
* of the sink monitor.
@ -256,9 +287,11 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr)
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(Ptm != NULL);
/* Configure the MSA values with the preferred timing mode (PTM) as
* specified by the preferred detailed timing descriptor of the
/* Configure the MSA values with the PTM information as
* specified by the preferred Detailed Timing Descriptor (DTD) of the
* monitor's EDID.
* Note, the PTM is only required for EDID versions 1.3 a newer. Earlier
* versions may not contain this information. */
@ -351,6 +384,8 @@ void XDptx_CfgMsaUseEdidPreferredTiming(XDptx *InstancePtr)
* @param Recalculate is a boolean enable that determines whether or not
* the main stream attributes should be recalculated.
*
* @return None.
*
* @note The InstancePtr-> MsaConfig structure is modified with the new
* values.
*
@ -362,6 +397,7 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
Xil_AssertVoid(MsaConfigCustom != NULL);
/* Copy the MSA values from the user configuration structure. */
@ -406,38 +442,25 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr,
* @param InstancePtr is a pointer to the XDptx instance
* @param BitsPerColor is the new number of bits per color to use.
*
* @return None.
*
* @note The InstancePtr->MsaConfig structure is modified to reflect the
* new main stream attributes associated with a new bits per color
* value.
*
* @return
* - XST_INVALID_PARAM if the supplied bits per color value is not
* either 6, 8, 10, 12, or 16.
* - XST_SUCCESS otherwise.
*
*******************************************************************************/
u32 XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
void XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
switch (BitsPerColor) {
case 6:
case 8:
case 10:
case 12:
case 16:
break;
default:
return XST_INVALID_PARAM;
}
Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
(BitsPerColor == 10) || (BitsPerColor == 12) ||
(BitsPerColor == 16));
InstancePtr->MsaConfig.BitsPerColor = BitsPerColor;
/* Calculate the rest of the MSA values. */
XDptx_CfgMsaRecalculate(InstancePtr);
return XST_SUCCESS;
}
/******************************************************************************/
@ -448,11 +471,17 @@ u32 XDptx_CfgMsaSetBpc(XDptx *InstancePtr, u8 BitsPerColor)
*
* @param InstancePtr is a pointer to the XDptx instance
*
* @return None.
*
* @note None.
*
*******************************************************************************/
void XDptx_SetVideoMode(XDptx *InstancePtr)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(&InstancePtr->MsaConfig != NULL);
XDptx_ClearMsaValues(InstancePtr);
XDptx_SetMsaValues(InstancePtr, &InstancePtr->MsaConfig);
@ -465,33 +494,34 @@ void XDptx_SetVideoMode(XDptx *InstancePtr)
*
* @param InstancePtr is a pointer to the XDptx instance.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
static void XDptx_ClearMsaValues(XDptx *InstancePtr)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
XDptx_Config *Config = &InstancePtr->Config;
XDptx_Config *TxConfig = &InstancePtr->TxConfig;
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_POLARITY, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HRES, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VRES, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSTART, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSTART, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC0, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC1, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_TU_SIZE, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_PIXEL_WIDTH, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_M_VID, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_N_VID, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MIN_BYTES_PER_TU, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_FRAC_BYTES_PER_TU, 0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_INIT_WAIT, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU, 0);
XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT, 0);
}
/******************************************************************************/
@ -504,58 +534,58 @@ static void XDptx_ClearMsaValues(XDptx *InstancePtr)
* @param MsaConfig is a pointer to the main stream attributes
* configuration structure.
*
* @return None.
*
* @note None.
*
*******************************************************************************/
static void XDptx_SetMsaValues(XDptx *InstancePtr,
XDptx_MainStreamAttributes *MsaConfig)
{
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(MsaConfig != NULL);
XDptx_Config *TxConfig = &InstancePtr->TxConfig;
XDptx_Config *Config = &InstancePtr->Config;
/* Set the main stream attributes to the associated DisplayPort TX core
* registers. */
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL,
MsaConfig->HClkTotal);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL,
MsaConfig->VClkTotal);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_POLARITY,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY,
MsaConfig->HSyncPolarity | (MsaConfig->VSyncPolarity <<
XDPTX_MAIN_STREAMX_POLARITY_VSYNC_POL_SHIFT));
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSWIDTH,
MsaConfig->HSyncPulseWidth);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSWIDTH,
MsaConfig->VSyncPulseWidth);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HRES,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HRES,
MsaConfig->HResolution);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VRES,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VRES,
MsaConfig->VResolution);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_HSTART,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HSTART,
MsaConfig->HStart);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_VSTART,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VSTART,
MsaConfig->VStart);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC0,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC0,
MsaConfig->Misc0);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MAIN_STREAM_MISC1,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_MISC1,
MsaConfig->Misc1);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_M_VID,
XDptx_WriteReg(Config->BaseAddr, XDPTX_M_VID,
MsaConfig->MVid);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_N_VID,
XDptx_WriteReg(Config->BaseAddr, XDPTX_N_VID,
MsaConfig->NVid);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_PIXEL_WIDTH,
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_PIXEL_WIDTH,
MsaConfig->UserPixelWidth);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE,
XDptx_WriteReg(Config->BaseAddr, XDPTX_USER_DATA_COUNT_PER_LANE,
MsaConfig->DataPerLane);
/* Set the transfer unit values to the associated DisplayPort TX core
* registers. */
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_TU_SIZE,
XDptx_WriteReg(Config->BaseAddr, XDPTX_TU_SIZE,
MsaConfig->TransferUnitSize);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_MIN_BYTES_PER_TU,
XDptx_WriteReg(Config->BaseAddr, XDPTX_MIN_BYTES_PER_TU,
MsaConfig->AvgBytesPerTU / 1000);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_FRAC_BYTES_PER_TU,
XDptx_WriteReg(Config->BaseAddr, XDPTX_FRAC_BYTES_PER_TU,
MsaConfig->AvgBytesPerTU % 1000);
XDptx_WriteReg(TxConfig->BaseAddr, XDPTX_INIT_WAIT,
XDptx_WriteReg(Config->BaseAddr, XDPTX_INIT_WAIT,
MsaConfig->InitWait);
}

2
XilinxProcessorIPLib/drivers/dptx/src/xdptx_vidmodetable.c
View file

@ -36,6 +36,8 @@
*
* Contains display monitor timing (DMT) modes for various standard resolutions.
*
* @note None.
*
* <pre>
* MODIFICATION HISTORY:
*