stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

qspipsu_v1_1: Modified the tcl file and related c files.

Browse source 
This patch updated the .tcl file to import bus width and
updated the driver instance.

Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This commit is contained in:
P L Sai Krishna 2015-05-06 15:58:44 +05:30 • committed by Nava kishore Manne
parent dcf79611f8
commit 97f9e315c6
3 changed files with 6 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

7
XilinxProcessorIPLib/drivers/qspipsu_v1_1/data/qspipsu.tcl
View file

@ -36,16 +36,17 @@
# Ver Who Date Changes
# ----- ---- -------- -----------------------------------------------
# 1.0 hk 08/21/14 First release
# 1.1 sk 05/06/15 Imported Bus Width Parameter.
#
##############################################################################
#uses "xillib.tcl"
proc generate {drv_handle} {
::hsi::utils::define_zynq_include_file $drv_handle "xparameters.h" "XQspiPsu" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE"
::hsi::utils::define_zynq_include_file $drv_handle "xparameters.h" "XQspiPsu" "NUM_INSTANCES" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE" "C_QSPI_BUS_WIDTH"
::hsi::utils::define_zynq_config_file $drv_handle "xqspipsu_g.c" "XQspiPsu" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE"
::hsi::utils::define_zynq_config_file $drv_handle "xqspipsu_g.c" "XQspiPsu" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE" "C_QSPI_BUS_WIDTH"
::hsi::utils::define_zynq_canonical_xpars $drv_handle "xparameters.h" "XQspiPsu" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE"
::hsi::utils::define_zynq_canonical_xpars $drv_handle "xparameters.h" "XQspiPsu" "DEVICE_ID" "C_S_AXI_BASEADDR" "C_S_AXI_HIGHADDR" "C_QSPI_CLK_FREQ_HZ" "C_QSPI_MODE" "C_QSPI_BUS_WIDTH"
}

1
XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu.c
View file

@ -132,6 +132,7 @@ s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
InstancePtr->Config.BaseAddress = EffectiveAddr + XQSPIPSU_OFFSET;
InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
InstancePtr->StatusHandler = StubStatusHandler;
InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
/* Other instance variable initializations */
InstancePtr->SendBufferPtr = NULL;

1
XilinxProcessorIPLib/drivers/qspipsu_v1_1/src/xqspipsu_g.c
View file

@ -77,5 +77,6 @@ XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES] = {
XPAR_XQSPIPSU_0_BASEADDR, /* Device base address */
XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ,
XPAR_XQSPIPSU_0_QSPI_MODE
XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH
},
};