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bsp: a53: added support for 64bit addressing mode

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This patch modifies Xil_DCacheFlushRange, Xil_DCacheInvalidateRange
and Xil_ICacheInvalidateRange API to add support for addresses higher
than 4GB by not truncating the addresses to 32bit

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-06-10 17:27:22 +05:30 • committed by Nava kishore Manne
parent c4df8f0dd2
commit 99a46157eb
2 changed files with 15 additions and 15 deletions
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24
lib/bsp/standalone/src/cortexa53/64bit/xil_cache.c
View file

@ -265,12 +265,12 @@ void Xil_DCacheInvalidateLine(INTPTR adr)
* @note None.
*
****************************************************************************/
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len)
{
const u32 cacheline = 64U;
u32 end;
u32 tempadr = adr;
u32 tempend;
INTPTR end;
INTPTR tempadr = adr;
INTPTR tempend;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
@ -456,12 +456,12 @@ void Xil_DCacheFlushLine(INTPTR adr)
*
****************************************************************************/
void Xil_DCacheFlushRange(INTPTR adr, u32 len)
void Xil_DCacheFlushRange(INTPTR adr, INTPTR len)
{
const u32 cacheline = 64U;
u32 end;
u32 tempadr = adr;
u32 tempend;
INTPTR end;
INTPTR tempadr = adr;
INTPTR tempend;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);
@ -618,12 +618,12 @@ void Xil_ICacheInvalidateLine(INTPTR adr)
* @note None.
*
****************************************************************************/
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len)
{
const u32 cacheline = 64U;
u32 end;
u32 tempadr = adr;
u32 tempend;
INTPTR end;
INTPTR tempadr = adr;
INTPTR tempend;
u32 currmask;
currmask = mfcpsr();
mtcpsr(currmask | IRQ_FIQ_MASK);

6
lib/bsp/standalone/src/cortexa53/64bit/xil_cache.h
View file

@ -57,16 +57,16 @@ extern "C" {
void Xil_DCacheEnable(void);
void Xil_DCacheDisable(void);
void Xil_DCacheInvalidate(void);
void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
void Xil_DCacheInvalidateRange(INTPTR adr, INTPTR len);
void Xil_DCacheInvalidateLine(INTPTR adr);
void Xil_DCacheFlush(void);
void Xil_DCacheFlushRange(INTPTR adr, u32 len);
void Xil_DCacheFlushRange(INTPTR adr, INTPTR len);
void Xil_DCacheFlushLine(INTPTR adr);
void Xil_ICacheEnable(void);
void Xil_ICacheDisable(void);
void Xil_ICacheInvalidate(void);
void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
void Xil_ICacheInvalidateRange(INTPTR adr, INTPTR len);
void Xil_ICacheInvalidateLine(INTPTR adr);
#ifdef __cplusplus
}