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emacps: Enable the 64 bit address for A53

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Enable the 64 bit address bus for A53

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
This commit is contained in:
Punnaiah Choudary Kalluri 2015-02-02 19:45:16 +05:30 • committed by Suneel Garapati
parent e0f2230210
commit a116cc9f3b
2 changed files with 4 additions and 0 deletions
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3
XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
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@ -339,6 +339,9 @@ void XEmacPs_Reset(XEmacPs *InstancePtr)
if (InstancePtr->Version > 2) {
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) |
#ifdef __aarch64__
(u32)XEMACPS_DMACR_ADDR_WIDTH_64 |
#endif
(u32)XEMACPS_DMACR_INCR4_AHB_BURST));
}
#if EXTENDED_DESC_MODE

1
XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
View file

@ -386,6 +386,7 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
/** @name DMA control register bit definitions
* @{
*/
#define XEMACPS_DMACR_ADDR_WIDTH_64 0x40000000U /**< 64 bit address bus */
#define XEMACPS_DMACR_TXEXTEND_MASK 0x20000000U /**< Tx Extended desc mode */
#define XEMACPS_DMACR_RXEXTEND_MASK 0x10000000U /**< Rx Extended desc mode */
#define XEMACPS_DMACR_RXBUF_MASK 0x00FF0000U /**< Mask bit for RX buffer