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dp: tx: Removed duplicate horizontal and vertical total entries.

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Part of the video mode table.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-01-13 14:38:42 -08:00 • committed by Nava kishore Manne
parent 2d7f2abf8a
commit a8370240c4
2 changed files with 3 additions and 15 deletions
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3
XilinxProcessorIPLib/drivers/dp/src/xdptx.h
View file

@ -290,9 +290,6 @@ typedef struct {
XVid_VideoTimingMode Vtm; /**< The video timing. */ XVid_VideoTimingMode Vtm; /**< The video timing. */
u32 PixelClockHz; /**< The pixel clock of the stream (in u32 PixelClockHz; /**< The pixel clock of the stream (in
Hz). */ Hz). */
u32 HClkTotal; /**< Horizontal total time (in
pixels). */
u32 VClkTotal; /**< Vertical total time (in pixels). */
u32 HStart; /**< Horizontal blank start (in u32 HStart; /**< Horizontal blank start (in
pixels). */ pixels). */
u32 VStart; /**< Vertical blank start (in lines). */ u32 VStart; /**< Vertical blank start (in lines). */

15
XilinxProcessorIPLib/drivers/dp/src/xdptx_spm.c
View file

@ -163,14 +163,6 @@ void XDptx_CfgMsaRecalculate(XDptx *InstancePtr, u8 Stream)
MsaConfig->Vtm.Timing.HBackPorch; MsaConfig->Vtm.Timing.HBackPorch;
MsaConfig->VStart = MsaConfig->Vtm.Timing.F0PVSyncWidth + MsaConfig->VStart = MsaConfig->Vtm.Timing.F0PVSyncWidth +
MsaConfig->Vtm.Timing.F0PVBackPorch; MsaConfig->Vtm.Timing.F0PVBackPorch;
MsaConfig->HClkTotal = (MsaConfig->Vtm.Timing.HSyncWidth +
MsaConfig->Vtm.Timing.HBackPorch +
MsaConfig->Vtm.Timing.HFrontPorch +
MsaConfig->Vtm.Timing.HActive);
MsaConfig->VClkTotal = (MsaConfig->Vtm.Timing.F0PVSyncWidth +
MsaConfig->Vtm.Timing.F0PVBackPorch +
MsaConfig->Vtm.Timing.F0PVFrontPorch +
MsaConfig->Vtm.Timing.VActive);
/* Miscellaneous attributes. */ /* Miscellaneous attributes. */
if (MsaConfig->BitsPerColor == 6) { if (MsaConfig->BitsPerColor == 6) {
@ -548,8 +540,6 @@ void XDptx_CfgMsaUseCustom(XDptx *InstancePtr, u8 Stream,
MsaConfig->NVid = MsaConfigCustom->NVid; MsaConfig->NVid = MsaConfigCustom->NVid;
MsaConfig->HStart = MsaConfigCustom->HStart; MsaConfig->HStart = MsaConfigCustom->HStart;
MsaConfig->VStart = MsaConfigCustom->VStart; MsaConfig->VStart = MsaConfigCustom->VStart;
MsaConfig->HClkTotal = MsaConfigCustom->HClkTotal;
MsaConfig->VClkTotal = MsaConfigCustom->VClkTotal;
MsaConfig->Misc0 = MsaConfigCustom->Misc0; MsaConfig->Misc0 = MsaConfigCustom->Misc0;
MsaConfig->Misc1 = MsaConfigCustom->Misc1; MsaConfig->Misc1 = MsaConfigCustom->Misc1;
MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane; MsaConfig->DataPerLane = MsaConfigCustom->DataPerLane;
@ -761,9 +751,10 @@ void XDptx_SetMsaValues(XDptx *InstancePtr, u8 Stream)
/* Set the main stream attributes to the associated DisplayPort TX core /* Set the main stream attributes to the associated DisplayPort TX core
* registers. */ * registers. */
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL + XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_HTOTAL +
StreamOffset[Stream - 1], MsaConfig->HClkTotal); StreamOffset[Stream - 1], MsaConfig->Vtm.Timing.HTotal);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL + XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_VTOTAL +
StreamOffset[Stream - 1], MsaConfig->VClkTotal); StreamOffset[Stream - 1],
MsaConfig->Vtm.Timing.F0PVTotal);
XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY + XDptx_WriteReg(Config->BaseAddr, XDPTX_MAIN_STREAM_POLARITY +
StreamOffset[Stream - 1], StreamOffset[Stream - 1],
MsaConfig->Vtm.Timing.HSyncPolarity | MsaConfig->Vtm.Timing.HSyncPolarity |