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v_csc: Updated driver to align with hip flow

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This patch supports HIP based video processing subsystem

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Reviewed-by: Andrei Simion <andreis@xilinx.com>
This commit is contained in:
Rohit Consul 2015-07-16 17:04:55 -07:00 • committed by Nava kishore Manne
parent 0f6fa4e9cd
commit a9babe3f16
9 changed files with 245 additions and 149 deletions
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2
XilinxProcessorIPLib/drivers/v_csc/data/v_csc.mdd Normal file → Executable file
View file

@ -9,7 +9,7 @@ OPTION psf_version = 2.1;
BEGIN driver v_csc
OPTION supported_peripherals = (v_csc_v1_0 );
OPTION supported_peripherals = (v_csc_v1_0);
OPTION driver_state = ACTIVE;
OPTION DEPENDS = (video_common_v1_1);
OPTION copyfiles = all;

59
XilinxProcessorIPLib/drivers/v_csc/data/v_csc.tcl Normal file → Executable file
View file

@ -1,9 +1,33 @@
# ==============================================================
# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
# Version: 2015.1
# Copyright (C) 2015 Xilinx Inc. All rights reserved.
##############################################################################
#
# ==============================================================
# Copyright (C) 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"),to deal
# in the Software without restriction, including without limitation the rights
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
# copies of the Software, and to permit persons to whom the Software is
# furnished to do so, subject to the following conditions:
#
# The above copyright notice and this permission notice shall be included in
# all copies or substantial portions of the Software.
#
# Use of the Software is limited solely to applications:
# (a) running on a Xilinx device, or
# (b) that interact with a Xilinx device through a bus or interconnect.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
# XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
# SOFTWARE.
#
# Except as contained in this notice, the name of the Xilinx shall not be used
# in advertising or otherwise to promote the sale, use or other dealings in
# this Software without prior written authorization from Xilinx.
###############################################################################
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "XV_csc" \
@ -11,26 +35,25 @@ proc generate {drv_handle} {
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"C_S_AXI_CTRL_HIGHADDR" \
"SAMPLES_PER_CLOCK" \
"V_CSC_MAX_WIDTH" \
"V_CSC_MAX_HEIGHT" \
"MAX_DATA_WIDTH"
"SAMPLES_PER_CLOCK" \
"V_CSC_MAX_WIDTH" \
"V_CSC_MAX_HEIGHT" \
"MAX_DATA_WIDTH"
xdefine_config_file $drv_handle "xv_csc_g.c" "XV_csc" \
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"SAMPLES_PER_CLOCK" \
"V_CSC_MAX_WIDTH" \
"V_CSC_MAX_HEIGHT" \
"MAX_DATA_WIDTH"
"SAMPLES_PER_CLOCK" \
"V_CSC_MAX_WIDTH" \
"V_CSC_MAX_HEIGHT" \
"MAX_DATA_WIDTH"
xdefine_canonical_xpars $drv_handle "xparameters.h" "XV_csc" \
"DEVICE_ID" \
"C_S_AXI_CTRL_BASEADDR" \
"C_S_AXI_CTRL_HIGHADDR" \
"SAMPLES_PER_CLOCK" \
"V_CSC_MAX_WIDTH" \
"V_CSC_MAX_HEIGHT" \
"MAX_DATA_WIDTH"
"SAMPLES_PER_CLOCK" \
"V_CSC_MAX_WIDTH" \
"V_CSC_MAX_HEIGHT" \
"MAX_DATA_WIDTH"
}

193
XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.c
View file

@ -11,16 +11,21 @@
/************************** Function Implementation *************************/
#ifndef __linux__
int XV_csc_CfgInitialize(XV_csc *InstancePtr, XV_csc_Config *ConfigPtr) {
int XV_csc_CfgInitialize(XV_csc *InstancePtr,
XV_csc_Config *ConfigPtr,
u32 EffectiveAddr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(ConfigPtr != NULL);
Xil_AssertNonvoid(EffectiveAddr != (u32)0x0);
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XV_csc));
(void)memcpy((void *)&(InstancePtr->Config), (const void *)ConfigPtr,
sizeof(XV_csc_Config));
/* Setup the instance */
(void)memset((void *)InstancePtr, 0, sizeof(XV_csc));
(void)memcpy((void *)&(InstancePtr->Config), (const void *)ConfigPtr,
sizeof(XV_csc_Config));
InstancePtr->Ctrl_BaseAddress = ConfigPtr->Ctrl_BaseAddress;
InstancePtr->Config.BaseAddress = EffectiveAddr;
/* Set the flag to indicate the driver is ready */
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
return XST_SUCCESS;
@ -33,8 +38,8 @@ void XV_csc_Start(XV_csc *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL) & 0x80;
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, Data | 0x01);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL) & 0x80;
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, Data | 0x01);
}
u32 XV_csc_IsDone(XV_csc *InstancePtr) {
@ -43,7 +48,7 @@ u32 XV_csc_IsDone(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
return (Data >> 1) & 0x1;
}
@ -53,7 +58,7 @@ u32 XV_csc_IsIdle(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
return (Data >> 2) & 0x1;
}
@ -63,7 +68,7 @@ u32 XV_csc_IsReady(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
// check ap_start to see if the pcore is ready for next input
return !(Data & 0x1);
}
@ -72,21 +77,21 @@ void XV_csc_EnableAutoRestart(XV_csc *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, 0x80);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, 0x80);
}
void XV_csc_DisableAutoRestart(XV_csc *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, 0);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL, 0);
}
void XV_csc_Set_HwReg_InVideoFormat(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA, Data);
}
u32 XV_csc_Get_HwReg_InVideoFormat(XV_csc *InstancePtr) {
@ -95,7 +100,7 @@ u32 XV_csc_Get_HwReg_InVideoFormat(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_INVIDEOFORMAT_DATA);
return Data;
}
@ -103,7 +108,7 @@ void XV_csc_Set_HwReg_OutVideoFormat(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA, Data);
}
u32 XV_csc_Get_HwReg_OutVideoFormat(XV_csc *InstancePtr) {
@ -112,7 +117,7 @@ u32 XV_csc_Get_HwReg_OutVideoFormat(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_OUTVIDEOFORMAT_DATA);
return Data;
}
@ -120,7 +125,7 @@ void XV_csc_Set_HwReg_width(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA, Data);
}
u32 XV_csc_Get_HwReg_width(XV_csc *InstancePtr) {
@ -129,7 +134,7 @@ u32 XV_csc_Get_HwReg_width(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_WIDTH_DATA);
return Data;
}
@ -137,7 +142,7 @@ void XV_csc_Set_HwReg_height(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA, Data);
}
u32 XV_csc_Get_HwReg_height(XV_csc *InstancePtr) {
@ -146,7 +151,7 @@ u32 XV_csc_Get_HwReg_height(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_HEIGHT_DATA);
return Data;
}
@ -154,7 +159,7 @@ void XV_csc_Set_HwReg_ColStart(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA, Data);
}
u32 XV_csc_Get_HwReg_ColStart(XV_csc *InstancePtr) {
@ -163,7 +168,7 @@ u32 XV_csc_Get_HwReg_ColStart(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLSTART_DATA);
return Data;
}
@ -171,7 +176,7 @@ void XV_csc_Set_HwReg_ColEnd(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA, Data);
}
u32 XV_csc_Get_HwReg_ColEnd(XV_csc *InstancePtr) {
@ -180,7 +185,7 @@ u32 XV_csc_Get_HwReg_ColEnd(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_COLEND_DATA);
return Data;
}
@ -188,7 +193,7 @@ void XV_csc_Set_HwReg_RowStart(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA, Data);
}
u32 XV_csc_Get_HwReg_RowStart(XV_csc *InstancePtr) {
@ -197,7 +202,7 @@ u32 XV_csc_Get_HwReg_RowStart(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWSTART_DATA);
return Data;
}
@ -205,7 +210,7 @@ void XV_csc_Set_HwReg_RowEnd(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA, Data);
}
u32 XV_csc_Get_HwReg_RowEnd(XV_csc *InstancePtr) {
@ -214,7 +219,7 @@ u32 XV_csc_Get_HwReg_RowEnd(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROWEND_DATA);
return Data;
}
@ -222,7 +227,7 @@ void XV_csc_Set_HwReg_K11(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_DATA, Data);
}
u32 XV_csc_Get_HwReg_K11(XV_csc *InstancePtr) {
@ -231,7 +236,7 @@ u32 XV_csc_Get_HwReg_K11(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_DATA);
return Data;
}
@ -239,7 +244,7 @@ void XV_csc_Set_HwReg_K12(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_DATA, Data);
}
u32 XV_csc_Get_HwReg_K12(XV_csc *InstancePtr) {
@ -248,7 +253,7 @@ u32 XV_csc_Get_HwReg_K12(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_DATA);
return Data;
}
@ -256,7 +261,7 @@ void XV_csc_Set_HwReg_K13(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_DATA, Data);
}
u32 XV_csc_Get_HwReg_K13(XV_csc *InstancePtr) {
@ -265,7 +270,7 @@ u32 XV_csc_Get_HwReg_K13(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_DATA);
return Data;
}
@ -273,7 +278,7 @@ void XV_csc_Set_HwReg_K21(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_DATA, Data);
}
u32 XV_csc_Get_HwReg_K21(XV_csc *InstancePtr) {
@ -282,7 +287,7 @@ u32 XV_csc_Get_HwReg_K21(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_DATA);
return Data;
}
@ -290,7 +295,7 @@ void XV_csc_Set_HwReg_K22(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_DATA, Data);
}
u32 XV_csc_Get_HwReg_K22(XV_csc *InstancePtr) {
@ -299,7 +304,7 @@ u32 XV_csc_Get_HwReg_K22(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_DATA);
return Data;
}
@ -307,7 +312,7 @@ void XV_csc_Set_HwReg_K23(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_DATA, Data);
}
u32 XV_csc_Get_HwReg_K23(XV_csc *InstancePtr) {
@ -316,7 +321,7 @@ u32 XV_csc_Get_HwReg_K23(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_DATA);
return Data;
}
@ -324,7 +329,7 @@ void XV_csc_Set_HwReg_K31(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_DATA, Data);
}
u32 XV_csc_Get_HwReg_K31(XV_csc *InstancePtr) {
@ -333,7 +338,7 @@ u32 XV_csc_Get_HwReg_K31(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_DATA);
return Data;
}
@ -341,7 +346,7 @@ void XV_csc_Set_HwReg_K32(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_DATA, Data);
}
u32 XV_csc_Get_HwReg_K32(XV_csc *InstancePtr) {
@ -350,7 +355,7 @@ u32 XV_csc_Get_HwReg_K32(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_DATA);
return Data;
}
@ -358,7 +363,7 @@ void XV_csc_Set_HwReg_K33(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_DATA, Data);
}
u32 XV_csc_Get_HwReg_K33(XV_csc *InstancePtr) {
@ -367,7 +372,7 @@ u32 XV_csc_Get_HwReg_K33(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_DATA);
return Data;
}
@ -375,7 +380,7 @@ void XV_csc_Set_HwReg_ROffset_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_ROffset_V(XV_csc *InstancePtr) {
@ -384,7 +389,7 @@ u32 XV_csc_Get_HwReg_ROffset_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_V_DATA);
return Data;
}
@ -392,7 +397,7 @@ void XV_csc_Set_HwReg_GOffset_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_GOffset_V(XV_csc *InstancePtr) {
@ -401,7 +406,7 @@ u32 XV_csc_Get_HwReg_GOffset_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_V_DATA);
return Data;
}
@ -409,7 +414,7 @@ void XV_csc_Set_HwReg_BOffset_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_BOffset_V(XV_csc *InstancePtr) {
@ -418,7 +423,7 @@ u32 XV_csc_Get_HwReg_BOffset_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_V_DATA);
return Data;
}
@ -426,7 +431,7 @@ void XV_csc_Set_HwReg_ClampMin_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_ClampMin_V(XV_csc *InstancePtr) {
@ -435,7 +440,7 @@ u32 XV_csc_Get_HwReg_ClampMin_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_V_DATA);
return Data;
}
@ -443,7 +448,7 @@ void XV_csc_Set_HwReg_ClipMax_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_ClipMax_V(XV_csc *InstancePtr) {
@ -452,7 +457,7 @@ u32 XV_csc_Get_HwReg_ClipMax_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_V_DATA);
return Data;
}
@ -460,7 +465,7 @@ void XV_csc_Set_HwReg_K11_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K11_2(XV_csc *InstancePtr) {
@ -469,7 +474,7 @@ u32 XV_csc_Get_HwReg_K11_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K11_2_DATA);
return Data;
}
@ -477,7 +482,7 @@ void XV_csc_Set_HwReg_K12_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K12_2(XV_csc *InstancePtr) {
@ -486,7 +491,7 @@ u32 XV_csc_Get_HwReg_K12_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K12_2_DATA);
return Data;
}
@ -494,7 +499,7 @@ void XV_csc_Set_HwReg_K13_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K13_2(XV_csc *InstancePtr) {
@ -503,7 +508,7 @@ u32 XV_csc_Get_HwReg_K13_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K13_2_DATA);
return Data;
}
@ -511,7 +516,7 @@ void XV_csc_Set_HwReg_K21_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K21_2(XV_csc *InstancePtr) {
@ -520,7 +525,7 @@ u32 XV_csc_Get_HwReg_K21_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K21_2_DATA);
return Data;
}
@ -528,7 +533,7 @@ void XV_csc_Set_HwReg_K22_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K22_2(XV_csc *InstancePtr) {
@ -537,7 +542,7 @@ u32 XV_csc_Get_HwReg_K22_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K22_2_DATA);
return Data;
}
@ -545,7 +550,7 @@ void XV_csc_Set_HwReg_K23_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K23_2(XV_csc *InstancePtr) {
@ -554,7 +559,7 @@ u32 XV_csc_Get_HwReg_K23_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K23_2_DATA);
return Data;
}
@ -562,7 +567,7 @@ void XV_csc_Set_HwReg_K31_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K31_2(XV_csc *InstancePtr) {
@ -571,7 +576,7 @@ u32 XV_csc_Get_HwReg_K31_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K31_2_DATA);
return Data;
}
@ -579,7 +584,7 @@ void XV_csc_Set_HwReg_K32_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K32_2(XV_csc *InstancePtr) {
@ -588,7 +593,7 @@ u32 XV_csc_Get_HwReg_K32_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K32_2_DATA);
return Data;
}
@ -596,7 +601,7 @@ void XV_csc_Set_HwReg_K33_2(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA, Data);
}
u32 XV_csc_Get_HwReg_K33_2(XV_csc *InstancePtr) {
@ -605,7 +610,7 @@ u32 XV_csc_Get_HwReg_K33_2(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_K33_2_DATA);
return Data;
}
@ -613,7 +618,7 @@ void XV_csc_Set_HwReg_ROffset_2_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_ROffset_2_V(XV_csc *InstancePtr) {
@ -622,7 +627,7 @@ u32 XV_csc_Get_HwReg_ROffset_2_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_ROFFSET_2_V_DATA);
return Data;
}
@ -630,7 +635,7 @@ void XV_csc_Set_HwReg_GOffset_2_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_GOffset_2_V(XV_csc *InstancePtr) {
@ -639,7 +644,7 @@ u32 XV_csc_Get_HwReg_GOffset_2_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_GOFFSET_2_V_DATA);
return Data;
}
@ -647,7 +652,7 @@ void XV_csc_Set_HwReg_BOffset_2_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_BOffset_2_V(XV_csc *InstancePtr) {
@ -656,7 +661,7 @@ u32 XV_csc_Get_HwReg_BOffset_2_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_BOFFSET_2_V_DATA);
return Data;
}
@ -664,7 +669,7 @@ void XV_csc_Set_HwReg_ClampMin_2_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_ClampMin_2_V(XV_csc *InstancePtr) {
@ -673,7 +678,7 @@ u32 XV_csc_Get_HwReg_ClampMin_2_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLAMPMIN_2_V_DATA);
return Data;
}
@ -681,7 +686,7 @@ void XV_csc_Set_HwReg_ClipMax_2_V(XV_csc *InstancePtr, u32 Data) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA, Data);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA, Data);
}
u32 XV_csc_Get_HwReg_ClipMax_2_V(XV_csc *InstancePtr) {
@ -690,7 +695,7 @@ u32 XV_csc_Get_HwReg_ClipMax_2_V(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Data = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA);
Data = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_HWREG_CLIPMAX_2_V_DATA);
return Data;
}
@ -698,14 +703,14 @@ void XV_csc_InterruptGlobalEnable(XV_csc *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_GIE, 1);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_GIE, 1);
}
void XV_csc_InterruptGlobalDisable(XV_csc *InstancePtr) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_GIE, 0);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_GIE, 0);
}
void XV_csc_InterruptEnable(XV_csc *InstancePtr, u32 Mask) {
@ -714,8 +719,8 @@ void XV_csc_InterruptEnable(XV_csc *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER, Register | Mask);
Register = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_IER);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_IER, Register | Mask);
}
void XV_csc_InterruptDisable(XV_csc *InstancePtr, u32 Mask) {
@ -724,27 +729,27 @@ void XV_csc_InterruptDisable(XV_csc *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Register = XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER, Register & (~Mask));
Register = XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_IER);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_IER, Register & (~Mask));
}
void XV_csc_InterruptClear(XV_csc *InstancePtr, u32 Mask) {
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
XV_csc_WriteReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_ISR, Mask);
XV_csc_WriteReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_ISR, Mask);
}
u32 XV_csc_InterruptGetEnabled(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_IER);
return XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_IER);
}
u32 XV_csc_InterruptGetStatus(XV_csc *InstancePtr) {
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
return XV_csc_ReadReg(InstancePtr->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_ISR);
return XV_csc_ReadReg(InstancePtr->Config.BaseAddress, XV_CSC_CTRL_ADDR_ISR);
}

11
XilinxProcessorIPLib/drivers/v_csc/src/xv_csc.h
View file

@ -45,11 +45,11 @@ typedef uint32_t u32;
*/
typedef struct {
u16 DeviceId; /**< Unique ID of device */
u32 Ctrl_BaseAddress; /**< The base address of the core instance. */
int PixPerClk; /**< Samples Per Clock supported by core instance */
u32 BaseAddress; /**< The base address of the core instance. */
u16 PixPerClk; /**< Samples Per Clock supported by core instance */
u16 MaxWidth; /**< Maximum columns supported by core instance */
u16 MaxHeight; /**< Maximum rows supported by core instance */
int MaxDataWidth; /**< Maximum Data width of each channel */
u16 MaxDataWidth; /**< Maximum Data width of each channel */
} XV_csc_Config;
#endif
@ -58,7 +58,6 @@ typedef struct {
*/
typedef struct {
XV_csc_Config Config; /**< Hardware Configuration */
u32 Ctrl_BaseAddress; /**< The base address of the core instance. */
u32 IsReady; /**< Device is initialized and ready */
} XV_csc;
@ -87,7 +86,9 @@ typedef struct {
#ifndef __linux__
int XV_csc_Initialize(XV_csc *InstancePtr, u16 DeviceId);
XV_csc_Config* XV_csc_LookupConfig(u16 DeviceId);
int XV_csc_CfgInitialize(XV_csc *InstancePtr, XV_csc_Config *ConfigPtr);
int XV_csc_CfgInitialize(XV_csc *InstancePtr,
XV_csc_Config *ConfigPtr,
u32 EffectiveAddr);
#else
int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName);
int XV_csc_Release(XV_csc *InstancePtr);

59
XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_g.c Normal file
View file

@ -0,0 +1,59 @@
/*******************************************************************
*
* CAUTION: This file is automatically generated by HSI.
* Version:
* DO NOT EDIT.
*
* Copyright (C) 2010-2015 Xilinx, Inc. All Rights Reserved.*
*Permission is hereby granted, free of charge, to any person obtaining a copy
*of this software and associated documentation files (the Software), to deal
*in the Software without restriction, including without limitation the rights
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
*copies of the Software, and to permit persons to whom the Software is
*furnished to do so, subject to the following conditions:
*
*The above copyright notice and this permission notice shall be included in
*all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
*(a) running on a Xilinx device, or
*(b) that interact with a Xilinx device through a bus or interconnect.
*
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
*Except as contained in this notice, the name of the Xilinx shall not be used
*in advertising or otherwise to promote the sale, use or other dealings in
*this Software without prior written authorization from Xilinx.
*
*
* Description: Driver configuration
*
*******************************************************************/
#include "xparameters.h"
#include "xv_csc.h"
/*
* The configuration table for devices
*/
XV_csc_Config XV_csc_ConfigTable[] =
{
{
#ifdef XPAR_XV_CSC_NUM_INSTANCES
XPAR_V_PROC_SS_0_V_CSC_DEVICE_ID,
XPAR_V_PROC_SS_0_V_CSC_S_AXI_CTRL_BASEADDR,
XPAR_V_PROC_SS_0_V_CSC_SAMPLES_PER_CLOCK,
XPAR_V_PROC_SS_0_V_CSC_V_CSC_MAX_WIDTH,
XPAR_V_PROC_SS_0_V_CSC_V_CSC_MAX_HEIGHT,
XPAR_V_PROC_SS_0_V_CSC_MAX_DATA_WIDTH
#endif
}
};

9
XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.c
View file

@ -35,6 +35,7 @@
* @file xv_csc_l2.c
* @addtogroup v_csc_v1_0
* @{
* @details
*
* The CSC Layer-2 Driver. The functions in this file provides an abstraction
* from the register peek/poke methodology by implementing most common use-case
@ -46,7 +47,7 @@
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 rc 05/01/15 Initial Release
* 1.00 rco 07/21/15 Initial Release
* </pre>
*
@ -1080,8 +1081,8 @@ static void cscFwComputeCoeff(XV_csc_L2Reg *pCscFwReg,
if (((pCscFwReg->ColorFormatIn == XVIDC_CSF_YCRCB_444) &&
(pCscFwReg->ColorFormatOut == XVIDC_CSF_YCRCB_444)) ||
((pCscFwReg->ColorFormatIn == XVIDC_CSF_YCRCB_422) &&
(pCscFwReg->ColorFormatOut == XVIDC_CSF_YCRCB_422)))
((pCscFwReg->ColorFormatIn == XVIDC_CSF_YCRCB_422) &&
(pCscFwReg->ColorFormatOut == XVIDC_CSF_YCRCB_422)))
{
cscFwYCbCrtoRGB(M1, pCscFwReg->StandardIn, pCscFwReg->ColorDepth, &ClampMin, &ClipMax);
cscFwMatrixMult(M1, K2, K3);
@ -1242,7 +1243,7 @@ void XV_CscDbgReportStatus(XV_csc *InstancePtr)
done = XV_csc_IsDone(pCsc);
idle = XV_csc_IsIdle(pCsc);
ready = XV_csc_IsReady(pCsc);
ctrl = XV_csc_ReadReg(pCsc->Ctrl_BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
ctrl = XV_csc_ReadReg(pCsc->Config.BaseAddress, XV_CSC_CTRL_ADDR_AP_CTRL);
colstart = XV_csc_Get_HwReg_ColStart(pCsc);
colend = XV_csc_Get_HwReg_ColEnd(pCsc);

3
XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_l2.h
View file

@ -35,6 +35,7 @@
* @file xv_csc_l2.h
* @addtogroup v_csc_v1_0
* @{
* @details
*
* This header file contains layer 2 API's of the csc sub-core driver.
* The functions contained herein provides a high level implementation of features
@ -97,7 +98,7 @@
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 rc 05/01/15 Initial Release
* 1.00 rco 07/21/15 Initial Release
* </pre>
*

18
XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_linux.c
View file

@ -87,8 +87,8 @@ static int uio_info_read_map_size(XV_csc_uio_info* info, int n) {
}
int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName) {
XV_csc_uio_info *InfoPtr = &uio_info;
struct dirent **namelist;
XV_csc_uio_info *InfoPtr = &uio_info;
struct dirent **namelist;
int i, n;
char* s;
char file[ MAX_UIO_PATH_SIZE ];
@ -100,9 +100,9 @@ int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName) {
n = scandir("/sys/class/uio", &namelist, 0, alphasort);
if (n < 0) return XST_DEVICE_NOT_FOUND;
for (i = 0; i < n; i++) {
strcpy(file, "/sys/class/uio/");
strcat(file, namelist[i]->d_name);
strcat(file, "/name");
strcpy(file, "/sys/class/uio/");
strcat(file, namelist[i]->d_name);
strcat(file, "/name");
if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
flag = 1;
s = namelist[i]->d_name;
@ -126,8 +126,8 @@ int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName) {
}
// NOTE: slave interface 'Ctrl' should be mapped to uioX/map0
InstancePtr->Ctrl_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
assert(InstancePtr->Ctrl_BaseAddress);
InstancePtr->Config.BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
assert(InstancePtr->Config.BaseAddress);
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
@ -135,12 +135,12 @@ int XV_csc_Initialize(XV_csc *InstancePtr, const char* InstanceName) {
}
int XV_csc_Release(XV_csc *InstancePtr) {
XV_csc_uio_info *InfoPtr = &uio_info;
XV_csc_uio_info *InfoPtr = &uio_info;
assert(InstancePtr != NULL);
assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
munmap((void*)InstancePtr->Ctrl_BaseAddress, InfoPtr->maps[0].size);
munmap((void*)InstancePtr->Config.BaseAddress, InfoPtr->maps[0].size);
close(InfoPtr->uio_fd);

40
XilinxProcessorIPLib/drivers/v_csc/src/xv_csc_sinit.c
View file

@ -11,35 +11,41 @@
#include "xparameters.h"
#include "xv_csc.h"
#ifndef XPAR_XV_CSC_NUM_INSTANCES
#define XPAR_XV_CSC_NUM_INSTANCES 0
#endif
extern XV_csc_Config XV_csc_ConfigTable[];
XV_csc_Config *XV_csc_LookupConfig(u16 DeviceId) {
XV_csc_Config *ConfigPtr = NULL;
XV_csc_Config *ConfigPtr = NULL;
int Index;
int Index;
for (Index = 0; Index < XPAR_XV_CSC_NUM_INSTANCES; Index++) {
if (XV_csc_ConfigTable[Index].DeviceId == DeviceId) {
ConfigPtr = &XV_csc_ConfigTable[Index];
break;
}
}
for (Index = 0; Index < XPAR_XV_CSC_NUM_INSTANCES; Index++) {
if (XV_csc_ConfigTable[Index].DeviceId == DeviceId) {
ConfigPtr = &XV_csc_ConfigTable[Index];
break;
}
}
return ConfigPtr;
return ConfigPtr;
}
int XV_csc_Initialize(XV_csc *InstancePtr, u16 DeviceId) {
XV_csc_Config *ConfigPtr;
XV_csc_Config *ConfigPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr != NULL);
ConfigPtr = XV_csc_LookupConfig(DeviceId);
if (ConfigPtr == NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
ConfigPtr = XV_csc_LookupConfig(DeviceId);
if (ConfigPtr == NULL) {
InstancePtr->IsReady = 0;
return (XST_DEVICE_NOT_FOUND);
}
return XV_csc_CfgInitialize(InstancePtr, ConfigPtr);
return XV_csc_CfgInitialize(InstancePtr,
ConfigPtr,
ConfigPtr->BaseAddress);
}
#endif