nandps8_v2_0: Added Driver prefix for enums and #defines
Added XNANDPS8_ before all enums and #define. Signed-off-by: Shakti Bhatnagar <shaktib@xilinx.com>
This commit is contained in:
Shakti Bhatnagar
Suneel Garapati
parent
fc61c2a759
commit
aacca7d88f
3 changed files with 82 additions and 83 deletions
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@ -240,11 +240,11 @@ s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
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/*
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* Operate in Polling Mode
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*/
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InstancePtr->Mode = POLLING;
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InstancePtr->Mode = XNANDPS8_POLLING;
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/*
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* Enable MDMA mode by default
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*/
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InstancePtr->DmaMode = MDMA;
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InstancePtr->DmaMode = XNANDPS8_MDMA;
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InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
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/*
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@ -272,15 +272,15 @@ s32 XNandPs8_CfgInitialize(XNandPs8 *InstancePtr, XNandPs8_Config *ConfigPtr,
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* Set ECC mode
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*/
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if (InstancePtr->Features.EzNand != 0U) {
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InstancePtr->EccMode = EZNAND;
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InstancePtr->EccMode = XNANDPS8_EZNAND;
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} else if (InstancePtr->Features.OnDie != 0U) {
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InstancePtr->EccMode = ONDIE;
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InstancePtr->EccMode = XNANDPS8_ONDIE;
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} else {
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InstancePtr->EccMode = HWECC;
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InstancePtr->EccMode = XNANDPS8_HWECC;
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}
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if (isQemuPlatform != 0U) {
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InstancePtr->EccMode = NONE;
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InstancePtr->EccMode = XNANDPS8_NONE;
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goto Out;
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}
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@ -721,7 +721,7 @@ void XNandPs8_EnableDmaMode(XNandPs8 *InstancePtr)
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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InstancePtr->DmaMode = MDMA;
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InstancePtr->DmaMode = XNANDPS8_MDMA;
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}
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/*****************************************************************************/
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@ -745,7 +745,7 @@ void XNandPs8_DisableDmaMode(XNandPs8 *InstancePtr)
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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InstancePtr->DmaMode = PIO;
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InstancePtr->DmaMode = XNANDPS8_PIO;
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}
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/*****************************************************************************/
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@ -769,7 +769,7 @@ void XNandPs8_EnableEccMode(XNandPs8 *InstancePtr)
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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InstancePtr->EccMode = HWECC;
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InstancePtr->EccMode = XNANDPS8_HWECC;
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}
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/*****************************************************************************/
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@ -793,7 +793,7 @@ void XNandPs8_DisableEccMode(XNandPs8 *InstancePtr)
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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InstancePtr->EccMode = NONE;
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InstancePtr->EccMode = XNANDPS8_NONE;
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}
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/*****************************************************************************/
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@ -1299,7 +1299,7 @@ static s32 XNandPs8_OnfiReadStatus(XNandPs8 *InstancePtr, u32 Target,
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/*
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* Program Packet Size and Packet Count
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*/
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if(InstancePtr->DataInterface == SDR){
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if(InstancePtr->DataInterface == XNANDPS8_SDR){
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XNandPs8_SetPktSzCnt(InstancePtr, 1U, 1U);
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}
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else{
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@ -2102,7 +2102,7 @@ static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_PG_PROG1, ONFI_CMD_PG_PROG2,
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1U, 1U, (u8)AddrCycles);
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Enable DMA boundary Interrupt in Interrupt Status
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@ -2132,7 +2132,7 @@ static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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/*
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* Program DMA system address and DMA buffer boundary
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*/
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Flush the Data Cache
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*/
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@ -2162,7 +2162,7 @@ static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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/*
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* Set ECC
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*/
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if (InstancePtr->EccMode == HWECC) {
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if (InstancePtr->EccMode == XNANDPS8_HWECC) {
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XNandPs8_SetEccSpareCmd(InstancePtr, ONFI_CMD_CHNG_WR_COL,
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InstancePtr->Geometry.ColAddrCycles);
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}
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@ -2172,7 +2172,7 @@ static s32 XNandPs8_ProgramPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
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XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_PG_PROG_MASK);
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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goto WriteDmaDone;
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}
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@ -2325,7 +2325,7 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
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PageVar %= InstancePtr->Geometry.NumTargetPages;
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if (InstancePtr->EccMode == HWECC) {
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if (InstancePtr->EccMode == XNANDPS8_HWECC) {
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/*
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* Calculate ECC free positions before and after ECC code
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*/
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@ -2365,7 +2365,7 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
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}
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}
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Enable Transfer Complete Interrupt in Interrupt Status
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* Enable Register
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@ -2408,7 +2408,7 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
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/*
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* Program DMA system address and DMA buffer boundary
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*/
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Flush the Data Cache
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*/
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@ -2451,7 +2451,7 @@ s32 XNandPs8_WriteSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
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XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_PG_PROG_MASK);
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}
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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goto WriteDmaDone;
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}
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@ -2552,7 +2552,7 @@ WriteDmaDone:
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XNANDPS8_INTR_STS_OFFSET,
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XNANDPS8_INTR_STS_TRANS_COMP_STS_EN_MASK);
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if (InstancePtr->EccMode == HWECC) {
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if (InstancePtr->EccMode == XNANDPS8_HWECC) {
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if (PostWrite > 0U) {
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BufPtr = (u32 *)(void *)&Buf[PostEccSpareCol];
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Status = XNandPs8_ChangeWriteColumn(InstancePtr,
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@ -2615,7 +2615,7 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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XNandPs8_Prepare_Cmd(InstancePtr, ONFI_CMD_RD1, ONFI_CMD_RD2,
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1U, 1U, (u8)AddrCycles);
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Enable DMA boundary Interrupt in Interrupt Status
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@ -2639,7 +2639,7 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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/*
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* Enable Single bit error and Multi bit error
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*/
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if (InstancePtr->EccMode == HWECC) {
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if (InstancePtr->EccMode == XNANDPS8_HWECC) {
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/*
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* Interrupt Status Enable Register
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*/
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@ -2662,7 +2662,7 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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/*
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* Program DMA system address and DMA buffer boundary
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*/
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Invalidate the Data Cache
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*/
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@ -2689,7 +2689,7 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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/*
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* Set ECC
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*/
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if (InstancePtr->EccMode == HWECC) {
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if (InstancePtr->EccMode == XNANDPS8_HWECC) {
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XNandPs8_SetEccSpareCmd(InstancePtr,
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(ONFI_CMD_CHNG_RD_COL1 |
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(ONFI_CMD_CHNG_RD_COL2 << (u8)8U)),
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@ -2702,7 +2702,7 @@ static s32 XNandPs8_ReadPage(XNandPs8 *InstancePtr, u32 Target, u32 Page,
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XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
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XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_MASK);
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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goto ReadDmaDone;
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}
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@ -2807,7 +2807,7 @@ CheckEccError:
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/*
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* Check ECC Errors
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*/
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if (InstancePtr->EccMode == HWECC) {
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if (InstancePtr->EccMode == XNANDPS8_HWECC) {
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/*
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* Hamming Multi Bit Errors
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*/
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@ -2900,7 +2900,7 @@ s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
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PageVar %= InstancePtr->Geometry.NumTargetPages;
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Enable Transfer Complete Interrupt in Interrupt Status
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* Enable Register
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@ -2937,7 +2937,7 @@ s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
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/*
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* Program DMA system address and DMA buffer boundary
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*/
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Invalidate the Data Cache
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@ -2967,7 +2967,7 @@ s32 XNandPs8_ReadSpareBytes(XNandPs8 *InstancePtr, u32 Page, u8 *Buf)
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XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
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XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_MASK);
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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goto ReadDmaDone;
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}
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@ -3199,7 +3199,7 @@ s32 XNandPs8_GetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
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*/
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Xil_AssertNonvoid(Buf != NULL);
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if (InstancePtr->DataInterface == NVDDR) {
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if (InstancePtr->DataInterface == XNANDPS8_NVDDR) {
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PktSize = 8U;
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}
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@ -3339,7 +3339,7 @@ s32 XNandPs8_SetFeature(XNandPs8 *InstancePtr, u32 Target, u8 Feature,
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* Assert the input arguments.
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*/
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Xil_AssertNonvoid(Buf != NULL);
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if (InstancePtr->DataInterface == NVDDR) {
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if (InstancePtr->DataInterface == XNANDPS8_NVDDR) {
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PktSize = 8U;
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}
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@ -3511,13 +3511,13 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
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/*
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* Check for valid input arguments
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*/
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if((NewIntf != SDR && NewIntf != NVDDR) ||
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if((NewIntf != XNANDPS8_SDR && NewIntf != XNANDPS8_NVDDR) ||
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(NewModeVar > 5U)){
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Status = XST_FAILURE;
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goto Out;
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}
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if(NewIntf == NVDDR){
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if(NewIntf == XNANDPS8_NVDDR){
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NewModeVar = NewModeVar | 0x10U;
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}
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/*
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@ -3534,19 +3534,19 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
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goto Out;
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}
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if ((CurIntf == NVDDR) && (NewIntf == SDR)) {
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if ((CurIntf == XNANDPS8_NVDDR) && (NewIntf == XNANDPS8_SDR)) {
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NewModeVar = SDR0;
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NewModeVar = XNANDPS8_SDR0;
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/*
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* Change the clock frequency
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*/
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XNandPs8_ChangeClockFreq(InstancePtr, SDR_CLK);
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XNandPs8_ChangeClockFreq(InstancePtr, XNANDPS8_SDR_CLK);
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/*
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* Update Data Interface Register
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*/
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RegVal = ((NewModeVar % 6U) << ((NewIntf == NVDDR) ? 3U : 0U)) |
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RegVal = ((NewModeVar % 6U) << ((NewIntf == XNANDPS8_NVDDR) ? 3U : 0U)) |
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((u32)NewIntf << XNANDPS8_DATA_INTF_DATA_INTF_SHIFT);
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XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
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XNANDPS8_DATA_INTF_OFFSET, RegVal);
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@ -3594,7 +3594,7 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
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}
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SetFeature = NewModeVar;
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if(CurIntf == NVDDR && NewIntf == NVDDR){
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if(CurIntf == XNANDPS8_NVDDR && NewIntf == XNANDPS8_NVDDR){
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SetFeature |= SetFeature << 8U;
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}
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/*
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@ -3614,7 +3614,7 @@ s32 XNandPs8_ChangeTimingMode(XNandPs8 *InstancePtr,
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/*
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* Update Data Interface Register
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*/
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RegVal = ((NewMode % 6U) << ((NewIntf == NVDDR) ? 3U : 0U)) |
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RegVal = ((NewMode % 6U) << ((NewIntf == XNANDPS8_NVDDR) ? 3U : 0U)) |
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((u32)NewIntf << XNANDPS8_DATA_INTF_DATA_INTF_SHIFT);
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XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
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XNANDPS8_DATA_INTF_OFFSET, RegVal);
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@ -3680,7 +3680,7 @@ static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
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Xil_AssertNonvoid(Target < XNANDPS8_MAX_TARGETS);
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Xil_AssertNonvoid(Buf != NULL);
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Enable DMA boundary Interrupt in Interrupt Status
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* Enable Register
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@ -3718,7 +3718,7 @@ static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
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/*
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* Program DMA system address and DMA buffer boundary
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*/
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Invalidate the Data Cache
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*/
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@ -3746,7 +3746,7 @@ static s32 XNandPs8_ChangeReadColumn(XNandPs8 *InstancePtr, u32 Target,
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XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
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XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_RD_MASK);
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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goto ReadDmaDone;
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}
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@ -3891,7 +3891,7 @@ static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
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return XST_SUCCESS;
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}
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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/*
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* Enable DMA boundary Interrupt in Interrupt Status
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* Enable Register
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@ -3932,7 +3932,7 @@ static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
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/*
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* Program DMA system address and DMA buffer boundary
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*/
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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#ifdef __aarch64__
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XNandPs8_WriteReg(InstancePtr->Config.BaseAddress,
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XNANDPS8_DMA_SYS_ADDR1_OFFSET,
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@ -3956,7 +3956,7 @@ static s32 XNandPs8_ChangeWriteColumn(XNandPs8 *InstancePtr, u32 Target,
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XNandPs8_WriteReg((InstancePtr)->Config.BaseAddress,
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XNANDPS8_PROG_OFFSET,XNANDPS8_PROG_CHNG_ROW_ADDR_END_MASK);
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if (InstancePtr->DmaMode == MDMA) {
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if (InstancePtr->DmaMode == XNANDPS8_MDMA) {
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goto WriteDmaDone;
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}
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@ -4142,12 +4142,12 @@ void XNandPs8_Prepare_Cmd(XNandPs8 *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState,
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RegValue = (u32)Cmd1 | (((u32)Cmd2 << (u32)XNANDPS8_CMD_CMD2_SHIFT) &
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(u32)XNANDPS8_CMD_CMD2_MASK);
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if ((EccState != 0U) && (InstancePtr->EccMode == HWECC)) {
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if ((EccState != 0U) && (InstancePtr->EccMode == XNANDPS8_HWECC)) {
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RegValue |= 1U << XNANDPS8_CMD_ECC_ON_SHIFT;
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}
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|
||||
if ((DmaMode != 0U) && (InstancePtr->DmaMode == MDMA)) {
|
||||
RegValue |= MDMA << XNANDPS8_CMD_DMA_EN_SHIFT;
|
||||
if ((DmaMode != 0U) && (InstancePtr->DmaMode == XNANDPS8_MDMA)) {
|
||||
RegValue |= XNANDPS8_MDMA << XNANDPS8_CMD_DMA_EN_SHIFT;
|
||||
}
|
||||
|
||||
if (AddrCycles != 0U) {
|
||||
|
|
|
|||
|
|
@ -171,7 +171,6 @@ extern "C" {
|
|||
/************************** Constant Definitions *****************************/
|
||||
|
||||
#define XNANDPS8_DEBUG
|
||||
#define RTL_3_1_FIX
|
||||
|
||||
#define XNANDPS8_MAX_TARGETS 1U /**< ce_n0, ce_n1 */
|
||||
#define XNANDPS8_MAX_PKT_SIZE 0x7FFU /**< Max packet size */
|
||||
|
|
@ -188,8 +187,8 @@ extern "C" {
|
|||
#define XNANDPS8_BUS_WIDTH_8 0U /**< 8-bit bus width */
|
||||
#define XNANDPS8_BUS_WIDTH_16 1U /**< 16-bit bus width */
|
||||
|
||||
#define XNANDPS8_HAMMING 0x1U /**< Hamming Flash */
|
||||
#define XNANDPS8_BCH 0x2U /**< BCH Flash */
|
||||
#define XNANDPS8_HAMMING 0x1U /**< Hamming Flash */
|
||||
#define XNANDPS8_BCH 0x2U /**< BCH Flash */
|
||||
|
||||
#define XNANDPS8_MAX_BLOCKS 32768U /**< Max number of Blocks */
|
||||
#define XNANDPS8_MAX_SPARE_SIZE 0x800U /**< Max spare bytes of a NAND
|
||||
|
|
@ -197,13 +196,13 @@ extern "C" {
|
|||
|
||||
#define XNANDPS8_INTR_POLL_TIMEOUT 10000U
|
||||
|
||||
#define SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U)
|
||||
#define NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U)
|
||||
#define NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U)
|
||||
#define NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U)
|
||||
#define NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U)
|
||||
#define NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U)
|
||||
#define NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U)
|
||||
#define XNANDPS8_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U)
|
||||
#define XNANDPS8_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U)
|
||||
#define XNANDPS8_NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U)
|
||||
#define XNANDPS8_NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U)
|
||||
#define XNANDPS8_NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U)
|
||||
#define XNANDPS8_NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U)
|
||||
#define XNANDPS8_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U)
|
||||
|
||||
/**
|
||||
* The XNandPs8_Config structure contains configuration information for NAND
|
||||
|
|
@ -218,53 +217,53 @@ typedef struct {
|
|||
* The XNandPs8_DataInterface enum contains flash operating mode.
|
||||
*/
|
||||
typedef enum {
|
||||
SDR = 0U, /**< Single Data Rate */
|
||||
NVDDR /**< Double Data Rate */
|
||||
XNANDPS8_SDR = 0U, /**< Single Data Rate */
|
||||
XNANDPS8_NVDDR /**< Double Data Rate */
|
||||
} XNandPs8_DataInterface;
|
||||
|
||||
/**
|
||||
* XNandPs8_TimingMode enum contains timing modes.
|
||||
*/
|
||||
typedef enum {
|
||||
SDR0 = 0U,
|
||||
SDR1,
|
||||
SDR2,
|
||||
SDR3,
|
||||
SDR4,
|
||||
SDR5,
|
||||
NVDDR0,
|
||||
NVDDR1,
|
||||
NVDDR2,
|
||||
NVDDR3,
|
||||
NVDDR4,
|
||||
NVDDR5
|
||||
XNANDPS8_SDR0 = 0U,
|
||||
XNANDPS8_SDR1,
|
||||
XNANDPS8_SDR2,
|
||||
XNANDPS8_SDR3,
|
||||
XNANDPS8_SDR4,
|
||||
XNANDPS8_SDR5,
|
||||
XNANDPS8_NVDDR0,
|
||||
XNANDPS8_NVDDR1,
|
||||
XNANDPS8_NVDDR2,
|
||||
XNANDPS8_NVDDR3,
|
||||
XNANDPS8_NVDDR4,
|
||||
XNANDPS8_NVDDR5
|
||||
} XNandPs8_TimingMode;
|
||||
|
||||
/**
|
||||
* The XNandPs8_SWMode enum contains the driver operating mode.
|
||||
*/
|
||||
typedef enum {
|
||||
POLLING = 0, /**< Polling */
|
||||
INTERRUPT /**< Interrupt */
|
||||
XNANDPS8_POLLING = 0, /**< Polling */
|
||||
XNANDPS8_INTERRUPT /**< Interrupt */
|
||||
} XNandPs8_SWMode;
|
||||
|
||||
/**
|
||||
* The XNandPs8_DmaMode enum contains the controller MDMA mode.
|
||||
*/
|
||||
typedef enum {
|
||||
PIO = 0, /**< PIO Mode */
|
||||
SDMA, /**< SDMA Mode */
|
||||
MDMA /**< MDMA Mode */
|
||||
XNANDPS8_PIO = 0, /**< PIO Mode */
|
||||
XNANDPS8_SDMA, /**< SDMA Mode */
|
||||
XNANDPS8_MDMA /**< MDMA Mode */
|
||||
} XNandPs8_DmaMode;
|
||||
|
||||
/**
|
||||
* The XNandPs8_EccMode enum contains ECC functionality.
|
||||
*/
|
||||
typedef enum {
|
||||
NONE = 0,
|
||||
HWECC,
|
||||
EZNAND,
|
||||
ONDIE
|
||||
XNANDPS8_NONE = 0,
|
||||
XNANDPS8_HWECC,
|
||||
XNANDPS8_EZNAND,
|
||||
XNANDPS8_ONDIE
|
||||
} XNandPs8_EccMode;
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -108,7 +108,7 @@ void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr)
|
|||
InstancePtr->BbtDesc.PageOffset[Index] =
|
||||
XNANDPS8_BBT_DESC_PAGE_OFFSET;
|
||||
}
|
||||
if (InstancePtr->EccMode == ONDIE) {
|
||||
if (InstancePtr->EccMode == XNANDPS8_ONDIE) {
|
||||
InstancePtr->BbtDesc.SigOffset = XNANDPS8_ONDIE_SIG_OFFSET;
|
||||
InstancePtr->BbtDesc.VerOffset = XNANDPS8_ONDIE_VER_OFFSET;
|
||||
} else {
|
||||
|
|
@ -131,7 +131,7 @@ void XNandPs8_InitBbtDesc(XNandPs8 *InstancePtr)
|
|||
InstancePtr->BbtMirrorDesc.PageOffset[Index] =
|
||||
XNANDPS8_BBT_DESC_PAGE_OFFSET;
|
||||
}
|
||||
if (InstancePtr->EccMode == ONDIE) {
|
||||
if (InstancePtr->EccMode == XNANDPS8_ONDIE) {
|
||||
InstancePtr->BbtMirrorDesc.SigOffset =
|
||||
XNANDPS8_ONDIE_SIG_OFFSET;
|
||||
InstancePtr->BbtMirrorDesc.VerOffset =
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue