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xilisf: Add support 4Byte addressing for Micron flash.

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This patch adds support to access greather than 16MB Micron
flash using 4Byte addressing.

Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
This commit is contained in:
Naga Sureshkumar Relli 2015-05-13 07:27:54 +05:30 • committed by Nava kishore Manne
parent fd5e7146a1
commit afbfa90ae1
13 changed files with 466 additions and 166 deletions
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2
lib/sw_services/xilisf/data/xilisf.mld
View file

@ -1,6 +1,6 @@
###############################################################################
#
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
# Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal

2
lib/sw_services/xilisf/data/xilisf.tcl
View file

@ -1,6 +1,6 @@
###############################################################################
#
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
# Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal

106
lib/sw_services/xilisf/examples/xilisf_stm_rdwr_polled_example.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -44,7 +44,8 @@
* - Reads back the Page that is written and compares the data.
*
* This example has been tested with a STM (Numonyx) M25P16 device on a Xilinx
* Spartan-3A Starter Kit board.
* Spartan-3A Starter Kit board and AC701 board with a Micron flash N25Q256A
* (32MB, supporting 4 Byte addressing mode).
*
*
* @note
@ -59,6 +60,8 @@
* 1.00a sdm 04/02/08 First release
* 2.00a ktn 11/22/09 The Spi Driver APIs have changed. Replaced the call
* to XSpi_mIntrGlobalDisable with XSpi_IntrGlobalDisable.
* 5.2 asa 05/12/15 Added support for Micron N25Q256A flash part which
* supports 4 byte addressing.
* </pre>
*
******************************************************************************/
@ -129,13 +132,15 @@ static XSpi Spi;
* to the Serial Flash, through a single Write operation.
* The size of this buffer should be equal to XISF_CMD_MAX_EXTRA_BYTES, if the
* application only reads from the Serial Flash (no write operations).
* For 4 byte addressing mode support, to account for the extra address bye
* the buffer size is incremented by 1.
*/
u8 IsfWriteBuffer[ISF_PAGE_SIZE + XISF_CMD_SEND_EXTRA_BYTES];
u8 IsfWriteBuffer[ISF_PAGE_SIZE + XISF_CMD_SEND_EXTRA_BYTES + 1];
/*
* Buffers used during Read/Write transactions.
*/
u8 ReadBuffer[ISF_PAGE_SIZE + XISF_CMD_SEND_EXTRA_BYTES]; /* Read Buffer */
u8 ReadBuffer[ISF_PAGE_SIZE + XISF_CMD_SEND_EXTRA_BYTES + 1]; /* Read Buffer */
u8 WriteBuffer[ISF_PAGE_SIZE]; /* Write buffer */
/************************** Function Definitions ******************************/
@ -181,9 +186,6 @@ int main()
*/
XSpi_IntrGlobalDisable(&Spi);
/*
* Initialize the Serial Flash Library.
*/
Status = XIsf_Initialize(&Isf, &Spi, ISF_SPI_SELECT, IsfWriteBuffer);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
@ -196,52 +198,53 @@ int main()
Address = ISF_TEST_ADDRESS;
/*
* The following code Erases a Sector in the STM Serial Flash.
* Check is the flash part is micron in which case, switch to 4 byte
* addressing mode.
*/
if (Isf.ManufacturerID == XISF_MANUFACTURER_ID_MICRON) {
Status = XIsf_WriteEnable(&Isf, XISF_WRITE_ENABLE);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIsf_MicronFlashEnter4BAddMode(&Isf);
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
/*
* Perform the Write Enable operation.
*/
Status = XIsf_WriteEnable(&Isf, XISF_WRITE_ENABLE);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Flash is not Busy.
*/
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform the Sector Erase operation.
*/
Status = XIsf_Erase(&Isf, XISF_SECTOR_ERASE, Address);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Flash is not Busy.
*/
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform the Write Enable operation.
*/
Status = XIsf_WriteEnable(&Isf, XISF_WRITE_ENABLE);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Flash is not Busy.
*/
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
@ -266,17 +269,11 @@ int main()
WriteParam.WritePtr[Index] = Index + ISF_TEST_BYTE;
}
/*
* Perform the Write operation.
*/
Status = XIsf_Write(&Isf, XISF_WRITE, (void*) &WriteParam);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Flash is not Busy.
*/
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
@ -292,20 +289,51 @@ int main()
ReadParam.NumBytes = ISF_PAGE_SIZE;
ReadParam.ReadPtr = ReadBuffer;
/*
* Perform the read operation.
*/
Status = XIsf_Read(&Isf, XISF_READ, (void*) &ReadParam);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Compare the data read against the data Written.
* Compare the data read against the data Written. For Micron flash
* which supports 4 Byte mode, comparison should take care of the extra
* address byte.
*/
for(Index = 0; Index < ISF_PAGE_SIZE; Index++) {
if(ReadBuffer[Index + XISF_CMD_SEND_EXTRA_BYTES] !=
(u8)(Index + ISF_TEST_BYTE)) {
if (Isf.ManufacturerID == XISF_MANUFACTURER_ID_MICRON) {
for(Index = 0; Index < ISF_PAGE_SIZE; Index++) {
if(ReadBuffer[Index + XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE] !=
(u8)(Index + ISF_TEST_BYTE)) {
return XST_FAILURE;
}
}
} else {
for(Index = 0; Index < ISF_PAGE_SIZE; Index++) {
if(ReadBuffer[Index + XISF_CMD_SEND_EXTRA_BYTES] !=
(u8)(Index + ISF_TEST_BYTE)) {
return XST_FAILURE;
}
}
}
/*
* For micron flash part supporting 4 byte ddressing mode, exit from
* 4 Byte mode.
*/
if (Isf.ManufacturerID == XISF_MANUFACTURER_ID_MICRON) {
Status = XIsf_WriteEnable(&Isf, XISF_WRITE_ENABLE);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
XIsf_MicronFlashExit4BAddMode(&Isf);
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
}

129
lib/sw_services/xilisf/examples/xilisf_stm_read_write_example.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -59,6 +59,7 @@
* 2.00a ktn 11/22/09 Updated to use HAL processor APIs.
* 5.0 sb 08/05/14 Registering to Xilisf Interrupt handler
* instead of driver handler.
* 5.2 asa 05/12/15 Added support for Micron N25Q256A flash.
*
* </pre>
*
@ -145,12 +146,12 @@ static int ErrorCount; /* Errors occurred during Spi transfers */
* The size of this buffer should be equal to XISF_CMD_MAX_EXTRA_BYTES, if the
* application only reads from the Serial Flash (no write operations).
*/
u8 IsfWriteBuffer[ISF_PAGE_SIZE + XISF_CMD_SEND_EXTRA_BYTES];
u8 IsfWriteBuffer[ISF_PAGE_SIZE + XISF_CMD_SEND_EXTRA_BYTES + 1];
/*
* Buffers used during Read/Write transactions.
*/
u8 ReadBuffer[ISF_PAGE_SIZE + XISF_CMD_SEND_EXTRA_BYTES]; /* Read Buffer */
u8 ReadBuffer[ISF_PAGE_SIZE + XISF_CMD_SEND_EXTRA_BYTES + 1]; /* Read Buffer */
u8 WriteBuffer[ISF_PAGE_SIZE]; /* Write buffer */
/************************** Function Definitions ******************************/
@ -225,80 +226,84 @@ int main()
*/
Address = ISF_TEST_ADDRESS;
/*
* The following code Erases a Sector in the STM Serial Flash.
*/
/*
* Perform the Write Enable operation.
*/
TransferInProgress = TRUE;
Status = XIsf_WriteEnable(&Isf, XISF_WRITE_ENABLE);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Transfer is complete and check for errors.
*/
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
}
/*
* Wait till the Flash is not Busy.
*/
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform the Sector Erase operation.
* Check is the flash part is micron in which case, switch to 4 byte
* addressing mode.
*/
if (Isf.ManufacturerID == XISF_MANUFACTURER_ID_MICRON) {
TransferInProgress = TRUE;
Status = XIsf_WriteEnable(&Isf, XISF_WRITE_ENABLE);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
}
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
TransferInProgress = TRUE;
XIsf_MicronFlashEnter4BAddMode(&Isf);
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
}
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
}
TransferInProgress = TRUE;
Status = XIsf_Erase(&Isf, XISF_SECTOR_ERASE, Address);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Transfer is complete and check for errors.
*/
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
}
/*
* Wait till the Flash is not Busy.
*/
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Perform the Write Enable operation.
*/
TransferInProgress = TRUE;
Status = XIsf_WriteEnable(&Isf, XISF_WRITE_ENABLE);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Transfer is complete and check for errors.
*/
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
}
/*
* Wait till the Flash is not Busy.
*/
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
@ -323,26 +328,17 @@ int main()
WriteParam.WritePtr[Index] = Index + ISF_TEST_BYTE;
}
/*
* Perform the Write operation.
*/
TransferInProgress = TRUE;
Status = XIsf_Write(&Isf, XISF_WRITE, (void*) &WriteParam);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Transfer is complete and check for errors.
*/
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
}
/*
* Wait till the Flash is not Busy.
*/
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
@ -358,18 +354,12 @@ int main()
ReadParam.NumBytes = ISF_PAGE_SIZE;
ReadParam.ReadPtr = ReadBuffer;
/*
* Perform the read operation.
*/
TransferInProgress = TRUE;
Status = XIsf_Read(&Isf, XISF_READ, (void*) &ReadParam);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Wait till the Transfer is complete and check for errors.
*/
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
@ -378,11 +368,50 @@ int main()
/*
* Compare the data read against the data Written.
*/
for(Index = 0; Index < ISF_PAGE_SIZE; Index++) {
if(ReadBuffer[Index + XISF_CMD_SEND_EXTRA_BYTES] !=
(u8)(Index + ISF_TEST_BYTE)) {
if (Isf.ManufacturerID == XISF_MANUFACTURER_ID_MICRON) {
for(Index = 0; Index < ISF_PAGE_SIZE; Index++) {
if(ReadBuffer[Index + XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE] !=
(u8)(Index + ISF_TEST_BYTE)) {
return XST_FAILURE;
}
}
} else {
for(Index = 0; Index < ISF_PAGE_SIZE; Index++) {
if(ReadBuffer[Index + XISF_CMD_SEND_EXTRA_BYTES] !=
(u8)(Index + ISF_TEST_BYTE)) {
return XST_FAILURE;
}
}
}
if (Isf.ManufacturerID == XISF_MANUFACTURER_ID_MICRON) {
TransferInProgress = TRUE;
Status = XIsf_WriteEnable(&Isf, XISF_WRITE_ENABLE);
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
}
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
TransferInProgress = TRUE;
XIsf_MicronFlashExit4BAddMode(&Isf);
while(TransferInProgress);
if(ErrorCount != 0) {
return XST_FAILURE;
}
Status = IsfWaitForFlashNotBusy();
if(Status != XST_SUCCESS) {
return XST_FAILURE;
}
return XST_SUCCESS;

2
lib/sw_services/xilisf/src/Makefile
View file

@ -1,6 +1,6 @@
###############################################################################
#
# Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
# Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
#
# Permission is hereby granted, free of charge, to any person obtaining a copy
# of this software and associated documentation files (the "Software"), to deal

27
lib/sw_services/xilisf/src/include/xilisf.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -140,7 +140,7 @@
* Read/Write Volatile/Non-volatile configuration register.
*
* The following Numonyx flash memories are supported by this library.
* N25Q32 N25Q64 N25Q128
* N25Q32 N25Q64 N25Q128 N25Q256A
*
* - Spansion S25FL
* The Spansion S25FL Serial Flash is divided into sectors of 64 KB and
@ -489,6 +489,11 @@
* XIsf_IfaceHandler()
* 5.1 sb 12/23/14 Added check for flash interface for Winbond, Spansion
* and Micron flash family for PSQSPI.
* 5.2 asa 5/12/15 Added support for Micron N25Q256A (>16MB) flash devices.
* This meant adding necessary support for 4 byte addressing mode.
* APIs were added to enter and exit from 4 byte mode. Changes were
* made in read, erase and write APIs to support 4 byte mode.
* These were done to fix CR#858950.
*
* </pre>
*
@ -787,8 +792,8 @@ typedef struct {
u8 NumDie; /**< No. of die forming a single flash */
u32 SectorSize; /**< Size of the Sector */
u32 NumSectors; /**< No. of sectors */
u32 ManufacturerID; /**< Serial Flash Manufacturer ID */
#endif
u32 ManufacturerID; /**< Serial Flash Manufacturer ID */
XIsf_Iface *SpiInstPtr; /**< SPI Device Instance pointer */
u32 SpiSlaveSelect; /**< SPI Slave select for the Serial Flash */
u8 *WriteBufPtr; /**< Pointer to Write Buffer */
@ -797,6 +802,7 @@ typedef struct {
* devices */
u8 RegDone; /**< Registration Done flag */
u8 IntrMode; /**< Operating Mode flag Interrupt/Polling */
u8 FourByteAddrMode; /**< In four byte address mode flag */
int (*XIsf_Iface_SetOptions)
(XIsf_Iface *InstancePtr, u32 Options);
#ifndef XPAR_XISF_INTERFACE_PSQSPI
@ -977,6 +983,21 @@ int XIsf_Read(XIsf *InstancePtr, XIsf_ReadOperation Operation,
*/
int XIsf_Erase(XIsf *InstancePtr, XIsf_EraseOperation Operation, u32 Address);
#if (((XPAR_XISF_FLASH_FAMILY == INTEL) || (XPAR_XISF_FLASH_FAMILY == STM) \
|| (XPAR_XISF_FLASH_FAMILY == SST) || \
(XPAR_XISF_FLASH_FAMILY == WINBOND) || \
(XPAR_XISF_FLASH_FAMILY == SPANSION)) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
/*
* Function for entering into 4 byte mode for Micron flash.
*/
int XIsf_MicronFlashEnter4BAddMode(XIsf *InstancePtr);
/*
* Function for exiting from 4 byte mode for Micron flash.
*/
int XIsf_MicronFlashExit4BAddMode(XIsf *InstancePtr);
#endif
/*
* Function related to Sector protection.
*/

11
lib/sw_services/xilisf/src/include/xilisf_atmel.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -204,6 +204,15 @@ extern "C" {
*/
#define XISF_CMD_SEND_EXTRA_BYTES 4 /**< Command extra bytes */
/**
* This definition specifies the extra bytes in each of the Write/Read/Erase
* commands, commands operating on SPR, auto page write, page to
* buffer and buffer to page transfer commands in 4 bytes addressing mode.
* This count includes Command byte, Address bytes and any
* don't care bytes needed.
*/
#define XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE 5 /**< Command extra bytes */
/**
* This definitions specify the extra bytes in Fast read Fast buffer read
* commands. This count includes Command byte, address bytes and any don't care

34
lib/sw_services/xilisf/src/include/xilisf_intelstm.h
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -55,6 +55,7 @@
* Added support to SST flash on SPI PS interface.
* 3.02a srt 04/26/13 Modified SECTOR and BLOCK Erase commands for
* SST flash (CR 703816).
* 5.2 asa 05/12/15 Added macros for 4 byte commands.
* </pre>
*
******************************************************************************/
@ -116,6 +117,8 @@ extern "C" {
#define XISF_NM_DEV_N25Q64 0xBA17 /**< Device ID for N25Q64 */
#define XISF_NM_DEV_N25Q128 0xBA18 /**< Device ID for N25Q128 */
#define XISF_MIC_DEV_N25Q128 0xBB18 /**< Device ID for N25Q128 */
#define XISF_MIC_DEV_N25Q256_3V0 0xBA19
#define XISF_MIC_DEV_N25Q256_1V8 0xBB19
/**
* The following definitions specify the Device Id for the different
@ -161,19 +164,26 @@ extern "C" {
* Definitions of Read commands.
*/
#define XISF_CMD_RANDOM_READ 0x03 /**< Random Read command */
#define XISF_CMD_RANDOM_READ_4BYTE 0x13 /**< Random 4 byte Read command */
#define XISF_CMD_FAST_READ 0x0B /**< Fast Read command */
#define XISF_CMD_FAST_READ_4BYTE 0x0C /**< 4 byte Fast Read command */
#define XISF_CMD_ISFINFO_READ 0x9F /**< Device Info command */
#define XISF_CMD_STATUSREG_READ 0x05 /**< Status Reg Read command */
#define XISF_CMD_STATUSREG2_READ 0x35 /**< Status Reg2 Read command */
#define XISF_CMD_DUAL_OP_FAST_READ 0x3B /**< Dual output fast read */
#define XISF_CMD_DUAL_OP_FAST_READ_4B 0x3C /**< 4 byte Dual output fast read */
#define XISF_CMD_DUAL_IO_FAST_READ 0xBB /**< Dual i/o fast read */
#define XISF_CMD_DUAL_IO_FAST_READ_4B 0xBC /**< 4 byte Dual i/o fast read */
#define XISF_CMD_QUAD_OP_FAST_READ 0x6B /**< Quad output fast read */
#define XISF_CMD_QUAD_OP_FAST_READ_4B 0x6C /**< 4 byte Quad output fast read */
#define XISF_CMD_QUAD_IO_FAST_READ 0xEB /**< Quad i/o fast read */
#define XISF_CMD_QUAD_IO_FAST_READ_4B 0xEC /**< 4 byte Quad i/o fast read */
/**
* Definitions of Write commands.
*/
#define XISF_CMD_PAGEPROG_WRITE 0x02 /**< Page Program command */
#define XISF_CMD_PAGEPROG_WRITE_4BYTE 0x12 /**< 4 byte Page Program command */
#define XISF_CMD_STATUSREG_WRITE 0x01 /**< Status Reg Write Command */
#define XISF_CMD_DUAL_IP_PAGE_WRITE 0xA2 /**< Dual input fast page write
*/
@ -195,6 +205,7 @@ extern "C" {
#define XISF_CMD_SECTOR_ERASE 0xD8 /**< Sector Erase command */
#define XISF_CMD_SUB_SECTOR_ERASE 0x20 /**< Sub-sector Erase command.
* only for N25QXX */
#define XISF_CMD_4BYTE_SECTOR_ERASE 0xDC
#endif /* ((XPAR_XISF_FLASH_FAMILY==INTEL)||(XPAR_XISF_FLASH_FAMILY == STM) ||
(XPAR_XISF_FLASH_FAMILY == SPANSION)) */
@ -207,6 +218,7 @@ extern "C" {
* Definitions of commands used for
* - Write Enable/Disable.
* - Deep Power Down mode Enter/Release.
* - Switch to 4 byte addressing
*/
#define XISF_CMD_ENABLE_WRITE 0x06 /**< Write enable command */
#define XISF_CMD_DISABLE_WRITE 0x04 /**< Write disable command */
@ -216,6 +228,10 @@ extern "C" {
#define XISF_CMD_ENABLE_HPM 0xA3 /**< Enable high performance
* mode */
#if (XPAR_XISF_FLASH_FAMILY == SPANSION)
#define XISF_CMD_ENTER_4BYTE_ADDR_MODE 0xB7
#define XISF_CMD_EXIT_4BYTE_ADDR_MODE 0xE9
#endif
#if (XPAR_XISF_FLASH_FAMILY == INTEL)
/**
* Definitions of commands which are only supported in Intel Serial Flash.
@ -273,6 +289,12 @@ extern "C" {
#define XISF_CMD_WRITE_ENABLE_DISABLE_BYTES 1 /**< Write enable/disable
* command extra bytes */
/**
* This definition specifies the extra bytes in 4 byte addr mode enter and exit
* commands. This count refers to the Command byte.
*/
#define XISF_CMD_4BYTE_ADDR_ENTER_EXIT_BYTES 1 /**< Four byte addr mode
* command extra bytes */
/**
* This definition specifies the extra bytes in each of the Write/Read/Erase
* commands, commands operating on SPR, auto page write, page to
@ -281,6 +303,15 @@ extern "C" {
*/
#define XISF_CMD_SEND_EXTRA_BYTES 4 /**< Command extra bytes */
/**
* This definition specifies the extra bytes in each of the Write/Read/Erase
* commands, commands operating on SPR, auto page write, page to
* buffer and buffer to page transfer commands in 4 bytes addressing mode.
* This count includes Command byte, Address bytes and any
* don't care bytes needed.
*/
#define XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE 5 /**< Command extra bytes */
/**
* This definition specifies the extra bytes in Fast Read and Fast Buffer Read
* commands. This count includes Command byte, address bytes and any don't care
@ -308,6 +339,7 @@ extern "C" {
/**
* Address Shift Masks.
*/
#define XISF_ADDR_SHIFT24 24 /**< 24 bit Shift */
#define XISF_ADDR_SHIFT16 16 /**< 16 bit Shift */
#define XISF_ADDR_SHIFT8 8 /**< 8 bit Shift */

125
lib/sw_services/xilisf/src/xilisf.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -89,6 +89,9 @@
* - XIsf_Ioctl()
* 5.1 sb 12/23/14 Added check for flash interface for Winbond, Spansion
* and Micron flash family for PSQSPI.
* 5.2 asa 05/12/15 Added APIs to support 4 byte addressing for Micron flash.
* 2 APIs were added, one to enter into 4 byte mode and the other
* to exit from the same.
*
* </pre>
*
@ -187,9 +190,7 @@ int SendBankSelect(XIsf *InstancePtr, u32 BankSel);
static int AtmelFlashInitialize(XIsf *InstancePtr, u8 *ReadBuf);
#endif /* (XPAR_XISF_FLASH_FAMILY == ATMEL) */
#if (((XPAR_XISF_FLASH_FAMILY == INTEL) || (XPAR_XISF_FLASH_FAMILY == STM) || \
(XPAR_XISF_FLASH_FAMILY == SST) || (XPAR_XISF_FLASH_FAMILY == WINBOND) || \
(XPAR_XISF_FLASH_FAMILY == SPANSION)) && \
#if (((XPAR_XISF_FLASH_FAMILY == SPANSION)) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
static int IntelStmFlashInitialize(XIsf *InstancePtr, u8 *ReadBuf);
#endif /* (((XPAR_XISF_FLASH_FAMILY == INTEL) || \
@ -389,6 +390,10 @@ static const IntelStmDeviceGeometry IntelStmDevices[] = {
XISF_BYTES256_PER_PAGE, XISF_PAGES256_PER_SECTOR,
XISF_NUM_OF_SECTORS256},
{XISF_MANUFACTURER_ID_MICRON, XISF_MIC_DEV_N25Q256_3V0,
XISF_BYTES256_PER_PAGE, XISF_PAGES256_PER_SECTOR,
XISF_NUM_OF_SECTORS512},
};
#endif /* (((XPAR_XISF_FLASH_FAMILY==INTEL) || (XPAR_XISF_FLASH_FAMILY==STM) \
|| (XPAR_XISF_FLASH_FAMILY == SST) || \
@ -598,6 +603,7 @@ int XIsf_Initialize(XIsf *InstancePtr, XIsf_Iface *SpiInstPtr, u8 SlaveSelect,
if (Status != (int)(XST_SUCCESS)) {
return (int)(XST_FAILURE);
}
#endif
#if (XPAR_XISF_FLASH_FAMILY == ATMEL)
@ -1322,11 +1328,113 @@ static int AtmelFlashInitialize(XIsf *InstancePtr, u8 *BufferPtr)
}
#endif /* (XPAR_XISF_FLASH_FAMILY == ATMEL) */
#if (((XPAR_XISF_FLASH_FAMILY == INTEL) || (XPAR_XISF_FLASH_FAMILY == STM) \
|| (XPAR_XISF_FLASH_FAMILY == SST) || \
(XPAR_XISF_FLASH_FAMILY == WINBOND) || \
(XPAR_XISF_FLASH_FAMILY == SPANSION)) && \
#if (((XPAR_XISF_FLASH_FAMILY == SPANSION)) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
/*****************************************************************************/
/**
*
* This function enters the Micron flash device into 4 bytes addressing mode.
* As per the Micron spec, before issuing the command to enter into 4 byte addr
* mode, a write enable command is issued.
*
* @param InstancePtr is a pointer to the XIsf instance.
*
* @return - XST_SUCCESS
* - XST_FAILURE
*
* @note Applicable only for Micron flash devices
*
******************************************************************************/
int XIsf_MicronFlashEnter4BAddMode(XIsf *InstancePtr)
{
int Status;
u8* NULLPtr = NULL;
u8 Mode;
if (InstancePtr == NULL) {
return (int)(XST_FAILURE);
}
if (InstancePtr->IsReady != TRUE) {
return (int)(XST_FAILURE);
}
if (InstancePtr->FourByteAddrMode == TRUE) {
return (int)(XST_SUCCESS);
}
InstancePtr->WriteBufPtr[BYTE1] = XISF_CMD_ENTER_4BYTE_ADDR_MODE;
Status = XIsf_Transfer(InstancePtr, InstancePtr->WriteBufPtr,
NULLPtr, XISF_CMD_4BYTE_ADDR_ENTER_EXIT_BYTES);
Mode = XIsf_GetTransferMode(InstancePtr);
if(Mode == XISF_INTERRUPT_MODE){
InstancePtr->StatusHandler(InstancePtr,
XIsf_StatusEventInfo, XIsf_ByteCountInfo);
}
if (Status != (int)(XST_SUCCESS)) {
return (int)(XST_FAILURE);
}
InstancePtr->FourByteAddrMode = TRUE;
return Status;
}
/*****************************************************************************/
/**
*
* This function exits the Micron flash device from 4 bytes addressing mode.
* As per the Micron spec, before issuing this command a write enable command is
* first issued.
*
* @param InstancePtr is a pointer to the XIsf instance.
*
* @return - XST_SUCCESS
* - XST_FAILURE
*
* @note Applicable only for Micron flash devices
*
******************************************************************************/
int XIsf_MicronFlashExit4BAddMode(XIsf *InstancePtr)
{
int Status;
u8* NULLPtr = NULL;
u8 Mode;
if (InstancePtr == NULL) {
return (int)(XST_FAILURE);
}
if (InstancePtr->IsReady != TRUE) {
return (int)(XST_FAILURE);
}
if (InstancePtr->FourByteAddrMode == FALSE) {
return (int)(XST_SUCCESS);
}
InstancePtr->WriteBufPtr[BYTE1] = XISF_CMD_EXIT_4BYTE_ADDR_MODE;
Status = XIsf_Transfer(InstancePtr, InstancePtr->WriteBufPtr,
NULLPtr, XISF_CMD_4BYTE_ADDR_ENTER_EXIT_BYTES);
Mode = XIsf_GetTransferMode(InstancePtr);
if(Mode == XISF_INTERRUPT_MODE){
InstancePtr->StatusHandler(InstancePtr,
XIsf_StatusEventInfo, XIsf_ByteCountInfo);
}
if (Status != (int)(XST_SUCCESS)) {
return (int)(XST_FAILURE);
}
InstancePtr->FourByteAddrMode = FALSE;
return Status;
}
/*****************************************************************************/
/**
*
@ -1378,6 +1486,7 @@ static int IntelStmFlashInitialize(XIsf *InstancePtr, u8 *BufferPtr)
IntelStmDevices[Index].DeviceCode) &&
(ManufacturerID ==
IntelStmDevices[Index].ManufacturerID)) {
InstancePtr->ManufacturerID = IntelStmDevices[Index].ManufacturerID;
InstancePtr->BytesPerPage =
IntelStmDevices[Index].BytesPerPage;

43
lib/sw_services/xilisf/src/xilisf_erase.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -56,6 +56,8 @@
* Changed API:
* SectorErase()
* BulkErase()
* 5.2 asa 05/12/15 Added support for Micron (N25Q256A) flash part
* which supports 4 byte addressing.
* </pre>
*
******************************************************************************/
@ -75,7 +77,6 @@
extern int XIsf_Transfer(XIsf *InstancePtr, u8 *WritePtr, u8* ReadPtr,
u32 ByteCount);
extern u32 GetRealAddr(XIsf_Iface *QspiPtr, u32 Address);
#ifdef XPAR_XISF_INTERFACE_PSQSPI
extern int SendBankSelect(XIsf *InstancePtr, u32 BankSel);
#endif
@ -304,6 +305,8 @@ static int SectorErase(XIsf *InstancePtr, u32 Address)
u32 FlashMake = InstancePtr->ManufacturerID;
#endif
Xil_AssertNonvoid(NULLPtr == NULL);
/*
* Translate address based on type of connection
* If stacked assert the slave select based on address
@ -346,11 +349,24 @@ static int SectorErase(XIsf *InstancePtr, u32 Address)
}
}
#endif
InstancePtr->WriteBufPtr[BYTE1] = XISF_CMD_SECTOR_ERASE;
InstancePtr->WriteBufPtr[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
InstancePtr->WriteBufPtr[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
InstancePtr->WriteBufPtr[BYTE4] = (u8) (RealAddr);
#if ((XPAR_XISF_FLASH_FAMILY == SPANSION) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
if (InstancePtr->FourByteAddrMode == TRUE) {
InstancePtr->WriteBufPtr[BYTE1] = XISF_CMD_SECTOR_ERASE;
InstancePtr->WriteBufPtr[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT24);
InstancePtr->WriteBufPtr[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
InstancePtr->WriteBufPtr[BYTE4] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
InstancePtr->WriteBufPtr[BYTE5] = (u8) (RealAddr);
} else {
#endif
InstancePtr->WriteBufPtr[BYTE1] = XISF_CMD_SECTOR_ERASE;
InstancePtr->WriteBufPtr[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
InstancePtr->WriteBufPtr[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
InstancePtr->WriteBufPtr[BYTE4] = (u8) (RealAddr);
#if ((XPAR_XISF_FLASH_FAMILY == SPANSION) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
}
#endif
#ifdef XPAR_XISF_INTERFACE_PSQSPI
/*
@ -361,14 +377,13 @@ static int SectorErase(XIsf *InstancePtr, u32 Address)
return (int)XST_FAILURE;
}
#endif
Xil_AssertNonvoid(NULLPtr == NULL);
/*
* Initiate the Transfer.
*/
Status = XIsf_Transfer(InstancePtr, InstancePtr->WriteBufPtr,
if (InstancePtr->FourByteAddrMode == TRUE) {
Status = XIsf_Transfer(InstancePtr, InstancePtr->WriteBufPtr,
NULLPtr, XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE);
} else {
Status = XIsf_Transfer(InstancePtr, InstancePtr->WriteBufPtr,
NULLPtr, XISF_CMD_SEND_EXTRA_BYTES);
}
if (Status != (int)XST_SUCCESS) {
return (int)XST_FAILURE;
}

89
lib/sw_services/xilisf/src/xilisf_read.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -52,6 +52,9 @@
* Changed API:
* ReadData()
* FastReadData()
*
* 5.2 asa 05/12/15 Added support for Micron (N25Q256A) flash part
* which supports 4 byte addressing.
* </pre>
*
******************************************************************************/
@ -267,7 +270,7 @@ int XIsf_Read(XIsf *InstancePtr, XIsf_ReadOperation Operation,
case XISF_DUAL_OP_FAST_READ:
ReadParamPtr = (XIsf_ReadParam*)(void *) OpParamPtr;
Xil_AssertNonvoid(ReadParamPtr != NULL);
Status = FastReadData(InstancePtr,
Status = FastReadData(InstancePtr,
XISF_CMD_DUAL_OP_FAST_READ,
ReadParamPtr->Address,
ReadParamPtr->ReadPtr,
@ -278,7 +281,7 @@ int XIsf_Read(XIsf *InstancePtr, XIsf_ReadOperation Operation,
case XISF_DUAL_IO_FAST_READ:
ReadParamPtr = (XIsf_ReadParam*)(void *) OpParamPtr;
Xil_AssertNonvoid(ReadParamPtr != NULL);
Status = FastReadData(InstancePtr,
Status = FastReadData(InstancePtr,
XISF_CMD_DUAL_IO_FAST_READ,
ReadParamPtr->Address,
ReadParamPtr->ReadPtr,
@ -289,7 +292,7 @@ int XIsf_Read(XIsf *InstancePtr, XIsf_ReadOperation Operation,
case XISF_QUAD_OP_FAST_READ:
ReadParamPtr = (XIsf_ReadParam*)(void *) OpParamPtr;
Xil_AssertNonvoid(ReadParamPtr != NULL);
Status = FastReadData(InstancePtr,
Status = FastReadData(InstancePtr,
XISF_CMD_QUAD_OP_FAST_READ,
ReadParamPtr->Address,
ReadParamPtr->ReadPtr,
@ -300,7 +303,7 @@ int XIsf_Read(XIsf *InstancePtr, XIsf_ReadOperation Operation,
case XISF_QUAD_IO_FAST_READ:
ReadParamPtr = (XIsf_ReadParam*)(void *) OpParamPtr;
Xil_AssertNonvoid(ReadParamPtr != NULL);
Status = FastReadData(InstancePtr,
Status = FastReadData(InstancePtr,
XISF_CMD_QUAD_IO_FAST_READ,
ReadParamPtr->Address,
ReadParamPtr->ReadPtr,
@ -364,7 +367,7 @@ static int ReadData(XIsf *InstancePtr, u32 Address, u8 *ReadPtr, u32 ByteCount)
u32 TotalByteCnt = ByteCount;
u32 LocalByteCnt = ByteCount;
u32 LocalAddress = Address;
u8 WriteBuffer[5] = {0};
u8 WriteBuffer[10] = {0};
if (LocalByteCnt <= 0 ) {
return (int)XST_FAILURE;
}
@ -420,15 +423,33 @@ static int ReadData(XIsf *InstancePtr, u32 Address, u8 *ReadPtr, u32 ByteCount)
#ifdef XPAR_XISF_INTERFACE_PSQSPI
}
#endif
WriteBuffer[BYTE1] = XISF_CMD_RANDOM_READ;
WriteBuffer[BYTE2] = (u8)((RealAddr & 0xFF0000) >> XISF_ADDR_SHIFT16);
WriteBuffer[BYTE3] = (u8)((RealAddr & 0xFF00) >> XISF_ADDR_SHIFT8);
WriteBuffer[BYTE4] = (u8)(RealAddr & 0xFF);
Status = XIsf_Transfer(InstancePtr, WriteBuffer,
#if ((XPAR_XISF_FLASH_FAMILY == SPANSION) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
if (InstancePtr->FourByteAddrMode == TRUE) {
WriteBuffer[BYTE1] = XISF_CMD_RANDOM_READ_4BYTE;
WriteBuffer[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT24);
WriteBuffer[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
WriteBuffer[BYTE4] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
WriteBuffer[BYTE5] = (u8) (RealAddr);
} else {
#endif
WriteBuffer[BYTE1] = XISF_CMD_RANDOM_READ;
WriteBuffer[BYTE2] = (u8)((RealAddr & 0xFF0000) >> XISF_ADDR_SHIFT16);
WriteBuffer[BYTE3] = (u8)((RealAddr & 0xFF00) >> XISF_ADDR_SHIFT8);
WriteBuffer[BYTE4] = (u8)(RealAddr & 0xFF);
#if ((XPAR_XISF_FLASH_FAMILY == SPANSION) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
}
#endif
if (InstancePtr->FourByteAddrMode == TRUE) {
Status = XIsf_Transfer(InstancePtr, WriteBuffer,
&(ReadPtr[TotalByteCnt - LocalByteCnt]),
RealByteCnt + XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE);
} else {
Status = XIsf_Transfer(InstancePtr, WriteBuffer,
&(ReadPtr[TotalByteCnt - LocalByteCnt]),
RealByteCnt + XISF_CMD_SEND_EXTRA_BYTES);
}
if (Status != (int)(XST_SUCCESS)) {
return (int)XST_FAILURE;
}
@ -567,24 +588,42 @@ static int FastReadData(XIsf *InstancePtr, u8 Command, u32 Address,
#ifdef XPAR_XISF_INTERFACE_PSQSPI
}
#endif
#if ((XPAR_XISF_FLASH_FAMILY == SPANSION) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
if (InstancePtr->FourByteAddrMode == TRUE) {
WriteBuffer[BYTE1] = Command;
WriteBuffer[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT24);
WriteBuffer[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
WriteBuffer[BYTE4] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
WriteBuffer[BYTE5] = (u8) RealAddr;
WriteBuffer[BYTE1] = Command;
WriteBuffer[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
WriteBuffer[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
WriteBuffer[BYTE4] = (u8) RealAddr;
for (Index = 0; Index < NumDummyBytes; Index++) {
WriteBuffer[Index + BYTE5 + 1] = (u8) (XISF_DUMMYBYTE);
}
} else {
#endif
WriteBuffer[BYTE1] = Command;
WriteBuffer[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
WriteBuffer[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
WriteBuffer[BYTE4] = (u8) RealAddr;
for (Index = 0; Index < NumDummyBytes; Index++) {
WriteBuffer[Index + BYTE5] = (u8) (XISF_DUMMYBYTE);
for (Index = 0; Index < NumDummyBytes; Index++) {
WriteBuffer[Index + BYTE5] = (u8) (XISF_DUMMYBYTE);
}
#if ((XPAR_XISF_FLASH_FAMILY == SPANSION) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
}
#endif
RealByteCnt += NumDummyBytes;
/*
* Initiate the Transfer.
*/
Status = (int)XIsf_Transfer(InstancePtr, WriteBuffer,
if (InstancePtr->FourByteAddrMode == TRUE) {
Status = (int)XIsf_Transfer(InstancePtr, WriteBuffer,
&(ReadPtr[TotalByteCnt - LocalByteCnt]),
RealByteCnt + XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE);
} else {
Status = (int)XIsf_Transfer(InstancePtr, WriteBuffer,
&(ReadPtr[TotalByteCnt - LocalByteCnt]),
RealByteCnt + XISF_CMD_SEND_EXTRA_BYTES);
}
if (Status != (int)(XST_SUCCESS)) {
return (int)(XST_FAILURE);
}

2
lib/sw_services/xilisf/src/xilisf_spr.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal

60
lib/sw_services/xilisf/src/xilisf_write.c
View file

@ -1,6 +1,6 @@
/******************************************************************************
*
* Copyright (C) 2012 - 2014 Xilinx, Inc. All rights reserved.
* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@ -54,6 +54,8 @@
* Changed API:
* WriteData()
* XIsf_Write()
* 5.2 asa 05/12/15 Added support for Micron (N25Q256A) flash part
* which supports 4 byte addressing.
* </pre>
*
******************************************************************************/
@ -236,10 +238,10 @@ int XIsf_Write(XIsf *InstancePtr, XIsf_WriteOperation Operation,
WriteParamPtr = (XIsf_WriteParam*)(void *) OpParamPtr;
Xil_AssertNonvoid(WriteParamPtr != NULL);
Status = WriteData(InstancePtr,
XISF_CMD_PAGEPROG_WRITE,
WriteParamPtr->Address,
WriteParamPtr->WritePtr,
WriteParamPtr->NumBytes);
XISF_CMD_PAGEPROG_WRITE,
WriteParamPtr->Address,
WriteParamPtr->WritePtr,
WriteParamPtr->NumBytes);
break;
case XISF_AUTO_PAGE_WRITE:
@ -348,9 +350,6 @@ int XIsf_Write(XIsf *InstancePtr, XIsf_WriteOperation Operation,
break;
}
/*
* Get the Transfer Mode
*/
Mode = XIsf_GetTransferMode(InstancePtr);
if(Mode == XISF_INTERRUPT_MODE){
@ -448,17 +447,34 @@ static int WriteData(XIsf *InstancePtr, u8 Command, u32 Address,
XIsf_SetTransferMode(InstancePtr, Mode);
}
#endif
InstancePtr->WriteBufPtr[BYTE1] = Command;
InstancePtr->WriteBufPtr[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
InstancePtr->WriteBufPtr[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
InstancePtr->WriteBufPtr[BYTE4] = (u8) (RealAddr);
for(Index = 4U; Index < (ByteCount + XISF_CMD_SEND_EXTRA_BYTES);
Index++) {
#if ((XPAR_XISF_FLASH_FAMILY == SPANSION) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
if (InstancePtr->FourByteAddrMode == TRUE) {
InstancePtr->WriteBufPtr[BYTE1] = Command;
InstancePtr->WriteBufPtr[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT24);
InstancePtr->WriteBufPtr[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
InstancePtr->WriteBufPtr[BYTE4] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
InstancePtr->WriteBufPtr[BYTE5] = (u8) (RealAddr);
for(Index = 5U; Index < (ByteCount + XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE);
Index++) {
InstancePtr->WriteBufPtr[Index] = *LocalBufPtr;
LocalBufPtr += 1;
}
} else {
#endif
InstancePtr->WriteBufPtr[BYTE1] = Command;
InstancePtr->WriteBufPtr[BYTE2] = (u8) (RealAddr >> XISF_ADDR_SHIFT16);
InstancePtr->WriteBufPtr[BYTE3] = (u8) (RealAddr >> XISF_ADDR_SHIFT8);
InstancePtr->WriteBufPtr[BYTE4] = (u8) (RealAddr);
for(Index = 4U; Index < (ByteCount + XISF_CMD_SEND_EXTRA_BYTES);
Index++) {
InstancePtr->WriteBufPtr[Index] = *LocalBufPtr;
LocalBufPtr += 1;
}
#if ((XPAR_XISF_FLASH_FAMILY == SPANSION) && \
(!defined(XPAR_XISF_INTERFACE_PSQSPI)))
}
#endif
#ifdef XPAR_XISF_INTERFACE_PSQSPI
/*
@ -466,11 +482,13 @@ static int WriteData(XIsf *InstancePtr, u8 Command, u32 Address,
*/
Status = XIsf_WriteEnable(InstancePtr, XISF_WRITE_ENABLE);
#endif
/*
* Initiate the Transfer.
*/
Status = XIsf_Transfer(InstancePtr, InstancePtr->WriteBufPtr, NULLPtr,
(ByteCount + XISF_CMD_SEND_EXTRA_BYTES));
if (InstancePtr->FourByteAddrMode == TRUE) {
Status = XIsf_Transfer(InstancePtr, InstancePtr->WriteBufPtr, NULLPtr,
(ByteCount + XISF_CMD_SEND_EXTRA_BYTES_4BYTE_MODE));
} else {
Status = XIsf_Transfer(InstancePtr, InstancePtr->WriteBufPtr, NULLPtr,
(ByteCount + XISF_CMD_SEND_EXTRA_BYTES));
}
if (Status != (int)XST_SUCCESS) {
return (int)XST_FAILURE;
}