bsp: a9: change in asm_vectors and xil_exception
This patch modifies asm_vectors.s and xil_exception.c to print the address for instruction causing data abort and prefetch abort in default handler Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
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4 changed files with 40 additions and 16 deletions
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@ -44,6 +44,9 @@
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; 3.11a asa 9/17/13 Added support for neon.
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; 4.00 pkp 01/22/14 Modified return addresses for interrupt
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; handlers
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; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
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; abort and prefetch abort into DataAbortAddr and
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; PrefetchAbortAddr for further use to fix CR#854523
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;</pre>
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;
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; @note
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@ -62,6 +65,8 @@
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IMPORT SWInterrupt
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IMPORT DataAbortInterrupt
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IMPORT PrefetchAbortInterrupt
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IMPORT DataAbortAddr
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IMPORT PrefetchAbortAddr
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AREA |.vectors|, CODE
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REQUIRE8 {TRUE}
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@ -137,18 +142,22 @@ SVCHandler ; SWI handler
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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movs pc, lr ; adjust return
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DataAbortHandler ; Data Abort handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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ldr r0, =DataAbortAddr
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sub r1, lr,#8
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str r1, [r0] ;Address of instruction causing data abort
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bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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subs pc, lr, #8 ; adjust return
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PrefetchAbortHandler ; Prefetch Abort handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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ldr r0, =PrefetchAbortAddr
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sub r1, lr,#4
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str r1, [r0] ;Address of instruction causing prefetch abort
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bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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subs pc, lr, #4 ; adjust return
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END
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@ -47,6 +47,9 @@
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* 4.00a pkp 22/01/14 Modified return addresses for interrupt
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* handlers (DataAbortHandler and SVCHandler)
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* to fix CR#767251
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* 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
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* abort and prefetch abort into DataAbortAddr and
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* PrefetchAbortAddr for further use to fix CR#854523
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* </pre>
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*
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* @note
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@ -61,18 +64,8 @@
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.org 0
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.text
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.globl _boot
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.globl _vector_table
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.globl FIQInterrupt
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.globl IRQInterrupt
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.globl SWInterrupt
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.globl DataAbortInterrupt
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.globl PrefetchAbortInterrupt
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.globl IRQHandler
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.globl prof_pc
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.section .vectors
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_vector_table:
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B _boot
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@ -176,6 +169,9 @@ DataAbortHandler: /* Data Abort handler */
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dsb
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#endif
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stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
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ldr r0, =DataAbortAddr
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sub r1, lr, #8
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str r1, [r0] /* Stores instruction causing data abort */
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bl DataAbortInterrupt /*DataAbortInterrupt :call C function here */
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@ -188,6 +184,9 @@ PrefetchAbortHandler: /* Prefetch Abort handler */
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dsb
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#endif
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stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */
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ldr r0, =PrefetchAbortAddr
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sub r1, lr, #4
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str r1, [r0] /* Stores instruction causing prefetch abort */
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bl PrefetchAbortInterrupt /* PrefetchAbortInterrupt: call C function here */
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@ -195,5 +194,4 @@ PrefetchAbortHandler: /* Prefetch Abort handler */
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subs pc, lr, #4 /* points to the instruction that caused the Prefetch Abort exception */
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.end
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@ -43,6 +43,9 @@
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; 1.00a Initial version
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; 4.2 pkp 06/27/14 Modified return addresses for interrupt
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; handlers
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; 5.1 pkp 05/13/15 Saved the addresses of instruction causing data
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; abort and prefetch abort into DataAbortAddr and
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; PrefetchAbortAddr for further use to fix CR#854523
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; </pre>
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;
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; @note
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@ -80,6 +83,8 @@
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IMPORT SWInterrupt
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IMPORT DataAbortInterrupt
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IMPORT PrefetchAbortInterrupt
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IMPORT DataAbortAddr
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IMPORT PrefetchAbortAddr
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_vector_table
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ARM
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@ -135,15 +140,20 @@ SVCHandler ; SWI handler
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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movs pc, lr ; adjust return
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DataAbortHandler ; Data Abort handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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ldr r0, =DataAbortAddr
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sub r1, lr,#8
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str r1, [r0] ;Address of instruction causing data abort
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bl DataAbortInterrupt ;DataAbortInterrupt :call C function here
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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subs pc, lr, #8 ; adjust return
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PrefetchAbortHandler ; Prefetch Abort handler
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stmdb sp!,{r0-r3,r12,lr} ; state save from compiled code
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ldr r0, =PrefetchAbortAddr
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sub r1, lr,#4
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str r1, [r0] ;Address of instruction causing prefetch abort
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bl PrefetchAbortInterrupt ; PrefetchAbortInterrupt: call C function here
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ldmia sp!,{r0-r3,r12,lr} ; state restore from compiled code
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subs pc, lr, #4 ; adjust return
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@ -50,6 +50,8 @@
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* DataAbortHandler and PrefetchAbortHandler respectively
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* Both handlers are registers in vector table entries
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* using XExc_VectorTable
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* 5.1 pkp 05/13/15 Added debugging message to print address of instruction
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* causing data abort and prefetch abort
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* </pre>
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*
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*****************************************************************************/
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@ -89,6 +91,9 @@ XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
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{Xil_ExceptionNullHandler, NULL},
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};
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u32 DataAbortAddr; /* Address of instruction causing data abort */
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u32 PrefetchAbortAddr; /* Address of instruction causing prefetch abort */
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/*****************************************************************************/
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/****************************************************************************/
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@ -209,7 +214,8 @@ void Xil_DataAbortHandler(void *CallBackRef){
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{ volatile register u32 Reg __asm(XREG_CP15_DATA_FAULT_STATUS);
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FaultStatus = Reg; }
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#endif
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xdbg_printf(XDBG_DEBUG_ERROR, "Data abort with Data Fault Status Register %x\n",FaultStatus);
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xdbg_printf(XDBG_DEBUG_GENERAL, "Data abort with Data Fault Status Register %x\n",FaultStatus);
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xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Data abort %x\n",DataAbortAddr);
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while(1) {
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;
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}
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@ -238,7 +244,8 @@ void Xil_PrefetchAbortHandler(void *CallBackRef){
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{ volatile register u32 Reg __asm(XREG_CP15_INST_FAULT_STATUS);
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FaultStatus = Reg; }
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#endif
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xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus);
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xdbg_printf(XDBG_DEBUG_GENERAL, "Prefetch abort with Instruction Fault Status Register %x\n",FaultStatus);
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xdbg_printf(XDBG_DEBUG_GENERAL, "Address of Instrcution causing Prefetch abort %x\n",PrefetchAbortAddr);
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while(1) {
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;
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}
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