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Standalone BSP : Add Coresight DCC support in .mld

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This patch adds coresight DCC support for Zynq Ultrascale+
MP Platform by modifying stdin and stdout range options.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
Venkata Naga Sai Krishna Kolapalli 2015-06-16 17:10:54 +05:30 • committed by Nava kishore Manne
parent bc29600582
commit b07d492a65
1 changed files with 2 additions and 2 deletions
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4
lib/bsp/standalone/data/standalone.mld
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@ -41,8 +41,8 @@ OPTION OS_STATE = ACTIVE;
OPTION VERSION = 5.2;
OPTION NAME = standalone;
PARAM name = stdin, desc = "stdin peripheral", type = peripheral_instance, requires_interface = stdin, default=none, range = (ps7_uart, ps7_coresight_comp, iomodule, axi_uartlite, axi_uart16550, mdm);
PARAM name = stdout, desc = "stdout peripheral", type = peripheral_instance, requires_interface = stdout, default=none, range = (ps7_uart, ps7_coresight_comp, iomodule, axi_uartlite, axi_uart16550, mdm);
PARAM name = stdin, desc = "stdin peripheral", type = peripheral_instance, requires_interface = stdin, default=none, range = (ps7_uart, psu_uart, ps7_coresight_comp, psu_coresight_0, iomodule, axi_uartlite, axi_uart16550, mdm);
PARAM name = stdout, desc = "stdout peripheral", type = peripheral_instance, requires_interface = stdout, default=none, range = (ps7_uart, psu_uart, ps7_coresight_comp, psu_coresight_0, iomodule, axi_uartlite, axi_uart16550, mdm);
BEGIN CATEGORY sw_intrusive_profiling
PARAM name = enable_sw_intrusive_profiling, type = bool, default = false, desc = "Enable S/W Intrusive Profiling on Hardware Targets", permit = user;
PARAM name = profile_timer, type = peripheral_instance, range = (opb_timer, xps_timer, axi_timer), default = none, desc = "Specify the Timer to use for Profiling. For PowerPC system, specify none to use PIT timer. For ARM system, specify none to use SCU timer";