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Coresight : Add support for Zynq Ultrascale+ MP.

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This patch adds coresight DCC driver support for
Zynq Ultrascale+ MP platform.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
This commit is contained in:
Venkata Naga Sai Krishna Kolapalli 2015-06-16 17:10:53 +05:30 • committed by Nava kishore Manne
parent 372c9797d2
commit bc29600582
4 changed files with 17 additions and 4 deletions
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2
XilinxProcessorIPLib/drivers/coresightps_dcc/data/coresightps_dcc.mdd
View file

@ -34,7 +34,7 @@ BEGIN driver coresightps_dcc
OPTION copyfiles = all;
OPTION driver_state = ACTIVE;
OPTION supported_peripherals = (ps7_coresight_comp);
OPTION supported_peripherals = (ps7_coresight_comp psu_coresight_0);
OPTION VERSION = 1.1;
OPTION NAME = coresightps_dcc;

4
XilinxProcessorIPLib/drivers/coresightps_dcc/src/Makefile
View file

@ -8,6 +8,10 @@ LIB=libxil.a
CC_FLAGS = $(COMPILER_FLAGS)
ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
ifeq ($(notdir $(COMPILER)), arm-none-eabi-gcc)
ECC_FLAGS += -mcpu=cortex-r5
endif
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}

14
XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.c
View file

@ -49,6 +49,7 @@
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00 kvn 02/14/15 First release
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
*
* </pre>
*
@ -88,7 +89,9 @@ void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data)
(void) BaseAddress;
while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX)
dsb();
#if defined (__GNUC__) || defined (__ICCARM__)
#ifdef __aarch64__
asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data));
#elif defined (__GNUC__) || defined (__ICCARM__)
asm volatile("mcr p14, 0, %0, c0, c5, 0"
: : "r" (Data));
#else
@ -124,7 +127,9 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX))
dsb();
#if defined (__GNUC__) || defined (__ICCARM__)
#ifdef __aarch64__
asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data));
#elif defined (__GNUC__) || defined (__ICCARM__)
asm volatile("mrc p14, 0, %0, c0, c5, 0"
: "=r" (Data));
#else
@ -154,7 +159,10 @@ u8 XCoresightPs_DccRecvByte(u32 BaseAddress)
static INLINE u32 XCoresightPs_DccGetStatus(void)
{
u32 Status;
#if defined (__GNUC__) || defined (__ICCARM__)
#ifdef __aarch64__
asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status));
#elif defined (__GNUC__) || defined (__ICCARM__)
asm volatile("mrc p14, 0, %0, c0, c1, 0"
: "=r" (Status) : : "cc");
#else

1
XilinxProcessorIPLib/drivers/coresightps_dcc/src/xcoresightpsdcc.h
View file

@ -53,6 +53,7 @@
* Ver Who Date Changes
* ----- ----- -------- -----------------------------------------------
* 1.00 kvn 02/14/15 First release
* 1.1 kvn 06/12/15 Add support for Zynq Ultrascale+ MP.
*
* </pre>
*