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bsp: a53: asm instructions have been modified to return proper value

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This patch modifies asm instruction ldr and mfcp for a53 64bit mode
to return 64bit values

Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Kinjal Pravinbhai Patel 2015-10-16 18:06:37 +05:30 • committed by Nava kishore Manne
parent 676a985bc1
commit b239d6a0db
1 changed files with 2 additions and 2 deletions
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4
lib/bsp/standalone/src/cortexa53/64bit/gcc/xpseudo_asm_gcc.h
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@ -110,7 +110,7 @@ extern "C" {
/* Memory Operations */ /* Memory Operations */
#define ldr(adr) ({u32 rval; \ #define ldr(adr) ({u64 rval; \
__asm__ __volatile__(\ __asm__ __volatile__(\
"ldr %0,[%1]"\ "ldr %0,[%1]"\
: "=r" (rval) : "r" (adr)\ : "=r" (rval) : "r" (adr)\
@ -151,7 +151,7 @@ extern "C" {
#define mtcptlbi(reg) asm("tlbi " #reg) #define mtcptlbi(reg) asm("tlbi " #reg)
#define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val)) #define mtcpat(reg,val) asm("at " #reg ",%0" : : "r" (val))
/* CP15 operations */ /* CP15 operations */
#define mfcp(reg) ({u32 rval;\ #define mfcp(reg) ({u64 rval;\
asm("mrs %0, " #reg : "=r" (rval));\ asm("mrs %0, " #reg : "=r" (rval));\
rval;\ rval;\
}) })