Adding zpe fsbl hdf with old design bit stream

Wall Data:
  Originally submitted from RDI_devivar_sdk_nov15
  Build Type: none
  Test Types: pre-commits, gui pre-commits
[git-p4: depot-paths = "//Rodin/HEAD/data/embeddedsw/": change = 977974]

lib/zpe_templates/ZPE_ZC_702_HwPlatform/ps7_init.html

@@ -77,7 +77,7 @@
 </DIV>
 </A>
 </DIV>
-<DIV class="content_container">This design is targeted for 7z020 board (part number: 7z020clg484-1)
+<DIV class="content_container">This design is targeted for xc7z020 board (part number: xc7z020clg484-1)
 
 <br>
 <H1>Zynq Design Summary</H1>
@@ -87,7 +87,7 @@
 <B>Device</B>
 </TD>
 <TD width=80% BGCOLOR=#E6E6E6>
-7z020
+xc7z020
 </TD>
 </TR>
 <TR valign="top">
@@ -103,7 +103,7 @@
 <B>Part</B>
 </TD>
 <TD width=80% BGCOLOR=#E6E6E6>
-7z020clg484-1
+xc7z020clg484-1
 </TD>
 </TR>
 <TR valign="top">

lib/zpe_templates/ZPE_ZC_702_HwPlatform/sysdef.xml

@@ -10,7 +10,7 @@
 	<File Type="PS_FSBL_INIT" Name="ps7_init.h" ModTime="1407149188"/>
 	<File Type="PS_XMD_INIT" Name="ps7_init.tcl" ModTime="1407149188"/>
 	<File Type="PS_INIT_HELP" Name="ps7_init.html" ModTime="1407149188"/>
-	<File Type="BIT" Name="zpe_without_controller_wrapper.bit" ModTime="1407155537"/>
+	<File Type="BIT" Name="zpe_without_controller_wrapper.bit" ModTime="1407133622"/>
 	<File Type="BD_TCL" Name="zpe_without_controller_bd.tcl" ModTime="1407149188"/>
 	<USEDRESOURCES LUT="38170" FF="36527" BRAM="56" DSP="0"/>
 </Project>