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axidma: Mark only BD Memory region as uncacheable

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This patch updates the Xil_SetTlbAttributes to mark the BD memory region
only uncaheable and updated the cache flush/invalidate api's for a53 case.

Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
Acked by: Anirudha Sarangi <anirudh@xilinx.com>
This commit is contained in:
Kedareswara rao Appana 2015-08-24 12:48:47 +05:30 • committed by Nava kishore Manne
parent 478171fa76
commit bcdb65d21b
2 changed files with 18 additions and 1 deletions
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11
XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_intr.c
View file

@ -162,6 +162,7 @@ extern void xil_printf(const char *format, ...);
* Buffer and Buffer Descriptor related constant definition
*/
#define MAX_PKT_LEN 0x100
#define MARK_UNCACHEABLE 0x701
/*
* Number of BDs in the transfer example
@ -276,6 +277,10 @@ int main(void)
#endif
xil_printf("\r\n--- Entering main() --- \r\n");
#ifdef __aarch64__
Xil_SetTlbAttributes(TX_BD_SPACE_BASE, MARK_UNCACHEABLE);
Xil_SetTlbAttributes(RX_BD_SPACE_BASE, MARK_UNCACHEABLE);
#endif
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
if (!Config) {
@ -428,7 +433,9 @@ static int CheckData(int Length, u8 StartValue)
/* Invalidate the DestBuffer before receiving the data, in case the
* Data Cache is enabled
*/
#ifndef __aarch64__
Xil_DCacheInvalidateRange((u32)RxPacket, Length);
#endif
for(Index = 0; Index < Length; Index++) {
if (RxPacket[Index] != Value) {
@ -1113,6 +1120,10 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr)
*/
Xil_DCacheFlushRange((u32)TxPacket, MAX_PKT_LEN *
NUMBER_OF_BDS_TO_TRANSFER);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)RX_BUFFER_BASE, MAX_PKT_LEN *
NUMBER_OF_BDS_TO_TRANSFER);
#endif
Status = XAxiDma_BdRingAlloc(TxRingPtr, NUMBER_OF_BDS_TO_TRANSFER,
&BdPtr);

8
XilinxProcessorIPLib/drivers/axidma/examples/xaxidma_example_sg_poll.c
View file

@ -200,7 +200,8 @@ int main(void)
xil_printf("\r\n--- Entering main() --- \r\n");
#ifdef __aarch64__
Xil_SetTlbAttributes(MEM_BASE_ADDR, MARK_UNCACHEABLE);
Xil_SetTlbAttributes(TX_BD_SPACE_BASE, MARK_UNCACHEABLE);
Xil_SetTlbAttributes(RX_BD_SPACE_BASE, MARK_UNCACHEABLE);
#endif
Config = XAxiDma_LookupConfig(DMA_DEV_ID);
@ -515,6 +516,9 @@ static int SendPacket(XAxiDma * AxiDmaInstPtr)
* is enabled
*/
Xil_DCacheFlushRange((UINTPTR)TxPacket, MAX_PKT_LEN);
#ifdef __aarch64__
Xil_DCacheFlushRange((UINTPTR)RX_BUFFER_BASE, MAX_PKT_LEN);
#endif
/* Allocate a BD */
@ -597,7 +601,9 @@ static int CheckData(void)
/* Invalidate the DestBuffer before receiving the data, in case the
* Data Cache is enabled
*/
#ifndef __aarch64__
Xil_DCacheInvalidateRange((UINTPTR)RxPacket, MAX_PKT_LEN);
#endif
for(Index = 0; Index < MAX_PKT_LEN; Index++) {
if (RxPacket[Index] != Value) {