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vprocss: Add dynamic scaler filter coefficient selection logic

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- Added dynamic scaler filter selection logic
- Added indirection layer for sub-core API's (picture settings,
  PIP background color, debug information)
- Fixed VDMA alignment in 1/2/4 pixel configurations
- Added example directory. Included files to be uused with
  vpss example design that will be released separately

Signed-off-by: Rohit Consul <rohit.consul@xilinx.com>
Acked-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Rohit Consul 2015-08-27 16:16:08 -07:00 • committed by Nava kishore Manne
parent 3f21bcd139
commit c8e6ea5336
11 changed files with 2358 additions and 161 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

212
XilinxProcessorIPLib/drivers/vprocss/examples/lscript.ld Normal file
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/*******************************************************************/
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/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */
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164
XilinxProcessorIPLib/drivers/vprocss/examples/main.c Normal file
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#include <stdio.h>
#include "xil_cache.h"
#include "xparameters.h"
#include "system.h"
#include "xvprocss_vdma.h"
#define XVPROCSS_SW_VER "v1.00"
#define VERBOSE_MODE 0
#define VIDEO_MONITOR_LOCK_TIMEOUT (1000000)
/************************** Variable Definitions *****************************/
XPeriph PeriphInst;
XVprocSs VprocInst;
/***************************************************************************
* This is the main thread that will do all initializations.
* It will call configure functions for all subsystems and system level
* peripherals
***************************************************************************/
int main(void)
{
XPeriph *PeriphPtr;
XVprocSs *VpssPtr;
int status;
u32 Timeout;
static int Lock = FALSE;
/* Bind instance pointer with definition */
PeriphPtr = &PeriphInst;
VpssPtr = &VprocInst;
/* Initialize ICache */
Xil_ICacheInvalidate();
Xil_ICacheEnable();
/* Initialize DCache */
Xil_DCacheInvalidate();
Xil_DCacheEnable();
xil_printf("\r\n--------------------------------------------------------\r\n");
xil_printf(" Video Processing Subsystem Example Design %s\r\n", XVPROCSS_SW_VER);
xil_printf(" (c) 2015 by Xilinx Inc.\r\n");
xil_printf("--------------------------------------------------------\r\n");
xil_printf("\r\nInitialize System Design...\r\n");
status = XSys_Init(PeriphPtr, VpssPtr);
if(status != XST_SUCCESS)
{
xil_printf("CRITICAL ERR:: System Init Failed. Cannot recover from this error. Check HW\n\r");
}
#if (VERBOSE_MODE == 1)
xil_printf("\r\nINFO> Setting up VPSS AXIS In/Out\r\n");
#endif
//Set TPG default parameters
XPeriph_SetTpgParams(PeriphPtr,
1920,
1080,
XVIDC_CSF_RGB,
XTPG_BKGND_COLOR_BARS,
FALSE);
//Set AXIS In to TPG settings
XSys_SetStreamParam(VpssPtr,
XSYS_VPSS_STREAM_IN,
PeriphInst.TpgConfig.Width,
PeriphInst.TpgConfig.Height,
PeriphInst.TpgConfig.ColorFmt,
PeriphInst.TpgConfig.IsInterlaced);
if(VpssPtr->Config.Topology == XVPROCSS_TOPOLOGY_SCALER_ONLY)
{
/* Only Scaling Ratio can be changed. Stream out color format
* must be same as stream in
*/
//Set AXIS Out
XSys_SetStreamParam(VpssPtr,
XSYS_VPSS_STREAM_OUT,
3840,
2160,
PeriphInst.TpgConfig.ColorFmt,
FALSE);
}
else //FULL_FLEDGED
{
//Set AXIS Out
XSys_SetStreamParam(VpssPtr,
XSYS_VPSS_STREAM_OUT,
3840,
2160,
XVIDC_CSF_YCRCB_422,
FALSE);
}
//Configure video processing subsystem
status = XVprocSs_SetSubsystemConfig(VpssPtr);
//Query vpss configuration
XVprocSs_ReportSubsystemConfig(VpssPtr);
if(status == XST_SUCCESS)
{
//Configure VTC with output timing
XPeriph_ConfigVtc(PeriphPtr,
&VpssPtr->VidOut,
VprocInst.Config.PixPerClock);
//Config TPG for AXIS In
XPeriph_ConfigTpg(PeriphPtr);
#if (VERBOSE_MODE == 1)
XPeriph_TpgDbgReportStatus(PeriphPtr);
#endif
xil_printf("\r\nWaiting for output to lock: ");
Timeout = VIDEO_MONITOR_LOCK_TIMEOUT;
while(!Lock && Timeout)
{
if(XPeriph_IsVideoLocked(PeriphPtr))
{
xil_printf("Locked\r\n");
Lock = TRUE;
}
--Timeout;
}
if(!Timeout)
{
xil_printf("\r\nTEST FAILED\r\n");
}
else
{
xil_printf("\r\nTEST PASSED\r\n");
}
}
else
{
xil_printf("\r\nERR:: VProcss Configuration Failed. \r\n");
xil_printf("\r\nTEST FAILED\r\n");
}
while(1)
{
//NOP
}
/* Clean up DCache. For writeback caches, the disable_dcache routine
internally does the flush and invalidate. For write through caches,
an explicit invalidation must be performed on the entire cache. */
#if XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 0
Xil_DCacheInvalidate ();
#endif
Xil_DCacheDisable ();
/* Clean up ICache */
Xil_ICacheInvalidate ();
Xil_ICacheDisable ();
return 0;
}

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XilinxProcessorIPLib/drivers/vprocss/examples/periph.c Normal file
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/******************************************************************************
*
* (c) Copyright 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file periph.c
*
* This is top level resource file that will initialize all system level
* peripherals
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 0.01 rc 07/07/14 First release
* </pre>
*
******************************************************************************/
#include "xparameters.h"
#include "xdebug.h"
#include "periph.h"
#include "xuartlite_l.h"
/************************** Constant Definitions *****************************/
/**************************** Type Definitions *******************************/
/**************************** Local Global *******************************/
/* Peripheral IP driver Instance */
XUartLite Uartl;
XV_tpg Tpg;
XVtc Vtc;
XGpio VidLocMonitor;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Function Definition ******************************/
/*****************************************************************************/
/**
* This function reports system wide common peripherals included in the design
*
* @param InstancePtr is a pointer to the Subsystem instance to be
* worked on.
*
*****************************************************************************/
void XPeriph_ReportDeviceInfo(XPeriph *InstancePtr)
{
u32 numInstances;
xil_printf("\r\n ->System Peripherals Included\r\n");
numInstances = XPAR_XUARTLITE_NUM_INSTANCES;
if(numInstances > 0)
{
xil_printf(" : %d UART-Lite core\r\n", numInstances);
}
numInstances = XPAR_XV_TPG_NUM_INSTANCES;
if(numInstances > 0)
{
xil_printf(" : %d TPG\r\n", numInstances);
}
numInstances = XPAR_XVTC_NUM_INSTANCES;
if(numInstances > 0)
{
xil_printf(" : %d VTC\r\n", numInstances);
}
numInstances = XPAR_XGPIO_NUM_INSTANCES;
if(numInstances > 1)
{
xil_printf(" : 1 Video Lock Monitor\r\n");
}
}
/*****************************************************************************/
/**
* This function initializes system wide common peripherals.
*
* @param InstancePtr is a pointer to the Subsystem instance to be
* worked on.
* @return XST_SUCCESS
*
*****************************************************************************/
int XPeriph_PowerOnInit(XPeriph *InstancePtr)
{
int status = XST_FAILURE;
XUartLite_Config *UartlCfgPtr;
XVtc_Config *VtcConfigPtr;
XGpio_Config *VidLockMonCfgPtr;
Xil_AssertNonvoid(InstancePtr != NULL);
//Bind the peripheral instance to ip drivers
InstancePtr->UartlPtr = &Uartl;
InstancePtr->TpgPtr = &Tpg;
InstancePtr->VtcPtr = &Vtc;
InstancePtr->VidLockMonitorPtr = &VidLocMonitor;
//UART-Lite
xdbg_printf(XDBG_DEBUG_GENERAL," ->Initializing UART Lite.... \r\n");
UartlCfgPtr = XUartLite_LookupConfig(XPAR_MICROBLAZE_SS_AXI_UARTLITE_0_DEVICE_ID);
if(UartlCfgPtr == NULL)
{
xil_printf("ERR:: UART Lite device not found\r\n");
return(XST_DEVICE_NOT_FOUND);
}
status = XUartLite_CfgInitialize(InstancePtr->UartlPtr,
UartlCfgPtr,
UartlCfgPtr->RegBaseAddr);
if(status != XST_SUCCESS)
{
xil_printf("ERR:: UART Lite Initialization failed %d\r\n", status);
return(XST_FAILURE);
}
//Reset UART FIFO
XUartLite_ResetFifos(InstancePtr->UartlPtr);
//TPG
xdbg_printf(XDBG_DEBUG_GENERAL," ->Initializing TPG.... \r\n");
status = XV_tpg_Initialize(InstancePtr->TpgPtr, XPAR_V_TPG_0_DEVICE_ID);
if(status == XST_DEVICE_NOT_FOUND)
{
xil_printf("ERR:: TPG device not found\r\n");
return(status);
}
//VTC
xdbg_printf(XDBG_DEBUG_GENERAL," ->Initializing VTC.... \r\n");
VtcConfigPtr = XVtc_LookupConfig(XPAR_V_TC_0_DEVICE_ID);
if(VtcConfigPtr == NULL)
{
xil_printf("ERR:: VTC device not found\r\n");
return(XST_DEVICE_NOT_FOUND);
}
status = XVtc_CfgInitialize(InstancePtr->VtcPtr,
VtcConfigPtr,
VtcConfigPtr->BaseAddress);
if(status != XST_SUCCESS)
{
xil_printf("ERR:: VTC Initialization failed %d\r\n", status);
return(XST_FAILURE);
}
//GPIO - Video Lock Monitor
xdbg_printf(XDBG_DEBUG_GENERAL," ->Initializing Video Lock Monitor.... \r\n");
VidLockMonCfgPtr = XGpio_LookupConfig(XPAR_VIDEO_LOCK_MONITOR_DEVICE_ID);
if(VidLockMonCfgPtr == NULL)
{
xil_printf("ERR:: GPIO device not found\r\n");
return(XST_DEVICE_NOT_FOUND);
}
status = XGpio_CfgInitialize(InstancePtr->VidLockMonitorPtr,
VidLockMonCfgPtr,
VidLockMonCfgPtr->BaseAddress);
if(status != XST_SUCCESS)
{
xil_printf("ERR:: Video Lock Monitor Initialization failed %d\r\n", status);
return(XST_FAILURE);
}
return(status);
}
/*****************************************************************************/
/**
* This function configures TPG to user defined parameters
*
* @param InstancePtr is a pointer to the peripheral instance
*
*****************************************************************************/
void XPeriph_ConfigTpg(XPeriph *InstancePtr)
{
XV_tpg *pTpg = InstancePtr->TpgPtr;
//Stop TPG
XV_tpg_DisableAutoRestart(pTpg);
XV_tpg_Set_height(pTpg, InstancePtr->TpgConfig.Height);
XV_tpg_Set_width(pTpg, InstancePtr->TpgConfig.Width);
XV_tpg_Set_colorFormat(pTpg, InstancePtr->TpgConfig.ColorFmt);
XV_tpg_Set_bckgndId(pTpg, InstancePtr->TpgConfig.Pattern);
XV_tpg_Set_ovrlayId(pTpg, 0);
//Start TPG
XV_tpg_EnableAutoRestart(pTpg);
XV_tpg_Start(pTpg);
}
/*****************************************************************************/
/**
* This function programs TPG to user defined resolution
*
* @param InstancePtr is a pointer to the peripheral instance
* @param width is the new active width
* @param height is the new active height
*****************************************************************************/
void XPeriph_SetTpgParams(XPeriph *InstancePtr,
u16 width,
u16 height,
XVidC_ColorFormat Cformat,
u16 Pattern,
u16 IsInterlaced)
{
xdbg_printf(XDBG_DEBUG_GENERAL,"\r\nConfigure TPG to %d x %d\r\n",
(int)width, (int)height);
XPeriph_SetTPGWidth(InstancePtr, width);
XPeriph_SetTPGHeight(InstancePtr, height);
XPeriph_SetTPGColorFormat(InstancePtr, Cformat);
XPeriph_SetTPGPattern(InstancePtr, Pattern);
XPeriph_SetTPGInterlacedMode(InstancePtr, IsInterlaced);
}
/*****************************************************************************/
/**
* This function stops TPG IP
*
* @param InstancePtr is a pointer to the peripheral instance
*
*****************************************************************************/
void XPeriph_DisableTpg(XPeriph *InstancePtr)
{
//Stop TPG
XV_tpg_DisableAutoRestart(InstancePtr->TpgPtr);
}
/*****************************************************************************/
/**
* This function reports TPG Status
*
* @param InstancePtr is a pointer to the peripheral instance
*
*****************************************************************************/
void XPeriph_TpgDbgReportStatus(XPeriph *InstancePtr)
{
u32 done, idle, ready, ctrl;
u32 width, height, bgid, cfmt;
XV_tpg *pTpg = InstancePtr->TpgPtr;
if(pTpg)
{
xil_printf("\r\n\r\n----->TPG STATUS<----\r\n");
done = XV_tpg_IsDone(pTpg);
idle = XV_tpg_IsIdle(pTpg);
ready = XV_tpg_IsReady(pTpg);
ctrl = XV_tpg_ReadReg(pTpg->Config.BaseAddress, XV_TPG_CTRL_ADDR_AP_CTRL);
width = XV_tpg_Get_width(pTpg);
height = XV_tpg_Get_height(pTpg);
bgid = XV_tpg_Get_bckgndId(pTpg);
cfmt = XV_tpg_Get_colorFormat(pTpg);
xil_printf("IsDone: %d\r\n", done);
xil_printf("IsIdle: %d\r\n", idle);
xil_printf("IsReady: %d\r\n", ready);
xil_printf("Ctrl: 0x%x\r\n\r\n", ctrl);
xil_printf("Width: %d\r\n",width);
xil_printf("Height: %d\r\n",height);
xil_printf("Backgnd Id: %d\r\n",bgid);
xil_printf("Color Format: %d\r\n",cfmt);
}
}
/*****************************************************************************/
/**
* This function configures VTC to output parameters
*
* @param InstancePtr is a pointer to the peripheral instance
* @param StreamPtr is a pointer output stream
*
*****************************************************************************/
void XPeriph_ConfigVtc(XPeriph *InstancePtr,
XVidC_VideoStream *StreamPtr,
u32 PixPerClk)
{
XVtc_Polarity Polarity;
XVtc_SourceSelect SourceSelect;
XVtc_Timing VideoTiming;
/* Disable Generator */
XVtc_Reset(InstancePtr->VtcPtr);
XVtc_DisableGenerator(InstancePtr->VtcPtr);
XVtc_Disable(InstancePtr->VtcPtr);
/* Set up source select
1 = Generator registers, 0 = Detector registers
**/
memset((void *)&SourceSelect, 1, sizeof(SourceSelect));
/* 1 = Generator registers, 0 = Detector registers */
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;
// XVtc_SetSource(InstancePtr->VtcPtr, &SourceSelect);
// Note: Can not use SetSource function call because the XVtc_SourceSelect struct
// does not have the interlace field. Workaround is to write it manually.
XVtc_WriteReg(InstancePtr->VtcPtr->Config.BaseAddress, (XVTC_CTL_OFFSET), 0x07FFFF00);
VideoTiming.HActiveVideo = StreamPtr->Timing.HActive;
VideoTiming.HFrontPorch = StreamPtr->Timing.HFrontPorch;
VideoTiming.HSyncWidth = StreamPtr->Timing.HSyncWidth;
VideoTiming.HBackPorch = StreamPtr->Timing.HBackPorch;
VideoTiming.HSyncPolarity = StreamPtr->Timing.HSyncPolarity;
/* Vertical Timing */
VideoTiming.VActiveVideo = StreamPtr->Timing.VActive;
// The VTC has an offset issue.
// This results into a wrong front porch and back porch value.
// As a workaround the front porch and back porch need to be adjusted.
VideoTiming.V0FrontPorch = StreamPtr->Timing.F0PVFrontPorch;
VideoTiming.V0BackPorch = StreamPtr->Timing.F0PVBackPorch;
VideoTiming.V0SyncWidth = StreamPtr->Timing.F0PVSyncWidth;
VideoTiming.V1FrontPorch = StreamPtr->Timing.F1VFrontPorch;
VideoTiming.V1SyncWidth = StreamPtr->Timing.F1VSyncWidth;
VideoTiming.V1BackPorch = StreamPtr->Timing.F1VBackPorch;
VideoTiming.VSyncPolarity = StreamPtr->Timing.VSyncPolarity;
VideoTiming.Interlaced = FALSE;
/* YUV420 */
if(StreamPtr->ColorFormatId == XVIDC_CSF_YCRCB_420) {
VideoTiming.HActiveVideo = VideoTiming.HActiveVideo/4;
VideoTiming.HFrontPorch = VideoTiming.HFrontPorch/4;
VideoTiming.HBackPorch = VideoTiming.HBackPorch/4;
VideoTiming.HSyncWidth = VideoTiming.HSyncWidth/4;
}
/* Other color spaces */
else
{
VideoTiming.HActiveVideo = VideoTiming.HActiveVideo/PixPerClk;
VideoTiming.HFrontPorch = VideoTiming.HFrontPorch/PixPerClk;
VideoTiming.HBackPorch = VideoTiming.HBackPorch/PixPerClk;
VideoTiming.HSyncWidth = VideoTiming.HSyncWidth/PixPerClk;
}
XVtc_SetGeneratorTiming(InstancePtr->VtcPtr, &VideoTiming);
/* Set up Polarity of all outputs */
memset((void *)&Polarity, 0, sizeof(XVtc_Polarity));
Polarity.ActiveChromaPol = 1;
Polarity.ActiveVideoPol = 1;
// Polarity.FieldIdPol = ((VideoTiming.Interlaced) ? 0 : 1);
// Note: With this fix the polarity of field-id does not have to be switched.
// I have found that the DELL monitor I am using does not care
// about polarity for interlaced video. As a result setting polarity HIGH or
// LOW for interlaced video does not make a difference.
Polarity.FieldIdPol = 0;
Polarity.VBlankPol = VideoTiming.VSyncPolarity;
Polarity.VSyncPol = VideoTiming.VSyncPolarity;
Polarity.HBlankPol = VideoTiming.HSyncPolarity;
Polarity.HSyncPol = VideoTiming.HSyncPolarity;
XVtc_SetPolarity(InstancePtr->VtcPtr, &Polarity);
/* Enable generator module */
XVtc_Enable(InstancePtr->VtcPtr);
XVtc_EnableGenerator(InstancePtr->VtcPtr);
XVtc_RegUpdateEnable(InstancePtr->VtcPtr);
}

202
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@ -0,0 +1,202 @@
/******************************************************************************
*
* (c) Copyright 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file periph.h
*
* This is header for resource file that will initialize all system
* level peripherals
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 0.01 rc 07/07/14 First release
* </pre>
*
******************************************************************************/
#ifndef XPERIPH_H /* prevent circular inclusions */
#define XPERIPH_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include "string.h"
#include "xvidc.h"
#include "xuartlite.h"
#include "xv_tpg.h"
#include "xgpio.h"
#include "xvtc.h"
/************************** Constant Definitions *****************************/
/************************** Structure Definitions *****************************/
typedef struct
{
u16 Width;
u16 Height;
XVidC_ColorFormat ColorFmt;
u16 IsInterlaced;
u16 Pattern;
}XPeriph_TpgConfig;
/**
* System Peripheral configuration structure.
* Each device should have a configuration structure associated
*/
typedef struct
{
XUartLite *UartlPtr;
XV_tpg *TpgPtr;
XVtc *VtcPtr;
XGpio *VidLockMonitorPtr;
XPeriph_TpgConfig TpgConfig;
}XPeriph;
/************************** Macros Definitions *******************************/
/*****************************************************************************/
/**
* This macro sets the TPG color format
*
* @param pPeriph is pointer to the peripheral Instance
* @param ColorFormat is the new color format
* @return none
*
*****************************************************************************/
#define XPeriph_SetTPGColorFormat(pPeriph, ColorFormat) \
((pPeriph)->TpgConfig.ColorFmt = ColorFormat)
/*****************************************************************************/
/**
* This macro sets the TPG pattern
*
* @param pPeriph is pointer to the peripheral Instance
* @param pattern is the new pattern id
* @return none
*
*****************************************************************************/
#define XPeriph_SetTPGPattern(pPeriph, Pattern) \
((pPeriph)->TpgConfig.Pattern = Pattern)
/*****************************************************************************/
/**
* This macro sets TPG active width
*
* @param pPeriph is pointer to the peripheral Instance
* @param width is the new active width
* @return none
*
*****************************************************************************/
#define XPeriph_SetTPGWidth(pPeriph, width) \
((pPeriph)->TpgConfig.Width = width)
/*****************************************************************************/
/**
* This macro sets TPG active height
*
* @param pPeriph is pointer to the peripheral Instance
* @param height is the new active height
* @return none
*
*****************************************************************************/
#define XPeriph_SetTPGHeight(pPeriph, height) \
((pPeriph)->TpgConfig.Height = height)
/*****************************************************************************/
/**
* This macro sets TPG Interlaced Mode
*
* @param pPeriph is pointer to the peripheral Instance
* @param mode is the interlace mode T/F
* @return none
*
*****************************************************************************/
#define XPeriph_SetTPGInterlacedMode(pPeriph, mode) \
((pPeriph)->TpgConfig.IsInterlaced = mode)
/*****************************************************************************/
/**
* This macro read GPIO to check video lock status
*
* @param pPeriph is pointer to the peripheral Instance
* @return T/F
*
*****************************************************************************/
#define XPeriph_IsVideoLocked(pPeriph) \
(XGpio_DiscreteRead((pPeriph)->VidLockMonitorPtr, 1))
/************************** Exported APIs ************************************/
int XPeriph_PowerOnInit(XPeriph *InstancePtr);
void XPeriph_ReportDeviceInfo(XPeriph *InstancePtr);
void XPeriph_ConfigTpg(XPeriph *InstancePtr);
void XPeriph_ConfigVtc(XPeriph *InstancePtr,
XVidC_VideoStream *StreamPtr,
u32 PixPerClk);
void XPeriph_DisableTpg(XPeriph *InstancePtr);
void XPeriph_SetTpgParams(XPeriph *InstancePtr,
u16 width,
u16 height,
XVidC_ColorFormat Cformat,
u16 Pattern,
u16 IsInterlaced);
void XPeriph_TpgDbgReportStatus(XPeriph *InstancePtr);
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

223
XilinxProcessorIPLib/drivers/vprocss/examples/system.c Normal file
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@ -0,0 +1,223 @@
/******************************************************************************
*
* (c) Copyright 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file system.c
*
* This is top level resource file that will initialize all system level
* peripherals
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 0.01 rc 07/07/14 First release
* </pre>
*
******************************************************************************/
#include "xparameters.h"
#include "system.h"
/************************** Constant Definitions *****************************/
#define USR_FRAME_BUF_BASEADDR (XPAR_MEMORY_SS_MIG_7SERIES_0_BASEADDR+(0x20000000))
/**************************** Type Definitions *******************************/
/**************************** Local Global *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
/************************** Function Definition ******************************/
/*****************************************************************************/
/**
*
* This function is the system level initialization routine. It in turn calls
* each of the included subsystem initialization function
*
* @param pPeriph is a pointer to the peripherals instance
* @param pVprocss is a pointer to the video proc subsystem instance
*
* @return
* - XST_SUCCESS if init. was successful.
* - XST_FAILURE if init. was unsuccessful.
*
* @note None.
*
******************************************************************************/
int XSys_Init(XPeriph *pPeriph, XVprocSs *pVprocss)
{
int status;
XVprocSs_Config *VprocSsConfigPtr;
Xil_AssertNonvoid(pPeriph != NULL);
Xil_AssertNonvoid(pVprocss != NULL);
//Init all instance variables to 0
memset(pPeriph, 0, sizeof(XPeriph));
memset(pVprocss, 0, sizeof(XVprocSs));
xil_printf("\r\n ->Initialize System Peripherals.... \r\n");
status = XPeriph_PowerOnInit(pPeriph);
if(status != XST_SUCCESS)
{
xil_printf("ERR:: System Peripheral Init. error\n\r");
return(XST_FAILURE);
}
xil_printf("\r\n ->Initialize Video Processing Subsystem...\r\n");
VprocSsConfigPtr = XVprocSs_LookupConfig(XPAR_V_PROC_SS_0_DEVICE_ID);
if(VprocSsConfigPtr == NULL)
{
xil_printf("ERR:: VprocSs device not found\r\n");
return (XST_DEVICE_NOT_FOUND);
}
if(VprocSsConfigPtr->Topology == XVPROCSS_TOPOLOGY_FULL_FLEDGED)
{
XVprocSs_SetFrameBufBaseaddr(pVprocss, USR_FRAME_BUF_BASEADDR);
}
status = XVprocSs_CfgInitialize(pVprocss,
VprocSsConfigPtr,
VprocSsConfigPtr->BaseAddress);
if(status != XST_SUCCESS)
{
xil_printf("ERR:: Video Processing Subsystem Init. error\n\r");
return(XST_FAILURE);
}
return(status);
}
/*****************************************************************************/
/**
*
* This function is to set vpss stream parameters
*
* @param pVprocss is a pointer to the video proc subsystem instance
* @param Direction defined if parameters are to be applied to Input or
* output stream
* @param Width is stream width
* @param Height is stream height
* @param cfmt is stream color format
*
* @return None
*
* @note None.
*
******************************************************************************/
void XSys_SetStreamParam(XVprocSs *pVprocss,
u16 Direction,
u16 Width,
u16 Height,
XVidC_ColorFormat cfmt,
u16 IsInterlaced)
{
XVidC_VideoMode resId;
XVidC_VideoStream Stream;
resId = XVidC_GetVideoModeId(Width, Height, XVIDC_FR_60HZ, FALSE);
//Setup Video Processing Subsystem
Stream.VmId = resId;
Stream.Timing.HActive = Width;
Stream.Timing.VActive = Height;
Stream.ColorFormatId = cfmt;
Stream.ColorDepth = pVprocss->Config.ColorDepth;
Stream.PixPerClk = pVprocss->Config.PixPerClock;
Stream.FrameRate = XVIDC_FR_60HZ;
Stream.IsInterlaced = IsInterlaced;
if(Direction == XSYS_VPSS_STREAM_IN)
{
XVprocSs_SetVidStreamIn(pVprocss, &Stream);
}
else
{
XVprocSs_SetVidStreamOut(pVprocss, &Stream);
}
}
/*****************************************************************************/
/**
*
* This function reports all the IP's included in the system design.
* It calls each subsystem API to report its child nodes
*
* @param pPeriph is a pointer to the peripherals instance
* @param pVprocss is a pointer to the video proc subsystem instance
*
* @return None
*
* @note None.
*
******************************************************************************/
void XSys_ReportSystemInfo(XPeriph *pPeriph, XVprocSs *pVprocss)
{
Xil_AssertVoid(pPeriph != NULL);
Xil_AssertVoid(pVprocss != NULL);
xil_printf("\r\n\r\r****Reporting System Design Info****\r\n");
//Report Peripherals found at System level
XPeriph_ReportDeviceInfo(pPeriph);
//Report cores in Video Processing subsystem
XVprocSs_ReportSubsystemCoreInfo(pVprocss);
}

105
XilinxProcessorIPLib/drivers/vprocss/examples/system.h Normal file
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@ -0,0 +1,105 @@
/******************************************************************************
*
* (c) Copyright 2014 - 2015 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
******************************************************************************/
/*****************************************************************************/
/**
*
* @file system.h
*
* This is header for top level resource file that will initialize all system
* level peripherals
*
* <pre>
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 0.01 rc 07/07/14 First release
* </pre>
*
******************************************************************************/
#ifndef XSYSTEM_H /* prevent circular inclusions */
#define XSYSTEM_H /* by using protection macros */
#ifdef __cplusplus
extern "C" {
#endif
#include "periph.h"
#include "xvprocss.h"
/************************** Constant Definitions *****************************/
typedef enum
{
XSYS_VPSS_STREAM_IN = 0,
XSYS_VPSS_STREAM_OUT
}XSys_StreamDirection;
/************************** Structure Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Exported APIs ************************************/
int XSys_Init(XPeriph *pPeriph, XVprocSs *pVprocss);
void XSys_ReportSystemInfo(XPeriph *pPeriph,
XVprocSs *pVprocss);
void XSys_SetStreamParam(XVprocSs *pVprocss,
u16 Direction,
u16 Width,
u16 Height,
XVidC_ColorFormat cfmt,
u16 IsInterlaced);
#ifdef __cplusplus
}
#endif
#endif /* End of protection macro */

57
XilinxProcessorIPLib/drivers/vprocss/src/vdma/xvprocss_vdma.c
View file

@ -163,29 +163,32 @@ int XVprocSs_VdmaWriteSetup(XAxiVdma *XVdmaPtr,
u32 Addr;
int Status;
u32 HSizeInBytes;
u32 StrideInBytes;;
u32 StrideInBytes;
u32 BlockOffset;
u32 alignBytes = 0;
u32 StartHPosBytes;
u32 alignBytes;
if(XVdmaPtr)
{
HSizeInBytes = (window->Width*PixelWidthInBits)/8;
StrideInBytes = (FrameWidth*PixelWidthInBits)/8;
/* Compute start location for sub-frame */
BlockOffset = (window->StartY * StrideInBytes) + (window->StartX*PixelWidthInBits)/8;
HSizeInBytes = (window->Width * PixelWidthInBits)/8;
StrideInBytes = (FrameWidth * PixelWidthInBits)/8;
StartHPosBytes = (window->StartX * PixelWidthInBits)/8;
/* If DMA engine does not support unaligned transfers then align block
* offset, hsize and stride to next data width boundary
* offset, hsize and stride to next data width boundary (aximm)
*/
if(!XVdmaPtr->WriteChannel.HasDRE)
{
alignBytes = XVdmaPtr->WriteChannel.WordLength-1;
BlockOffset = (BlockOffset + alignBytes) & ~(alignBytes);
HSizeInBytes = (HSizeInBytes + alignBytes) & ~(alignBytes);
StrideInBytes = (StrideInBytes + alignBytes) & ~(alignBytes);
HSizeInBytes = (HSizeInBytes + alignBytes) & ~(alignBytes);
StrideInBytes = (StrideInBytes + alignBytes) & ~(alignBytes);
StartHPosBytes = (StartHPosBytes + alignBytes) & ~(alignBytes);
}
/* Compute start location for sub-frame */
BlockOffset = ((window->StartY * StrideInBytes) + StartHPosBytes);
WriteCfg.VertSizeInput = window->Height;
WriteCfg.HoriSizeInput = HSizeInBytes;
@ -200,7 +203,7 @@ int XVprocSs_VdmaWriteSetup(XAxiVdma *XVdmaPtr,
WriteCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */
WriteCfg.GenLockRepeat = 1; /* Repeat previous frame on frame errors */
WriteCfg.GenLockRepeat = 0; /* Do not repeat previous frame on frame errors */
Status = XAxiVdma_DmaConfig(XVdmaPtr, XAXIVDMA_WRITE, &WriteCfg);
if (Status != XST_SUCCESS)
{
@ -262,27 +265,35 @@ int XVprocSs_VdmaReadSetup(XAxiVdma *XVdmaPtr,
u32 HSizeInBytes;
u32 StrideInBytes;
u32 BlockOffset;
u32 alignBytes = 0;
u32 alignBytes;
u32 StartHPosBytes;
if(XVdmaPtr)
{
HSizeInBytes = (window->Width*PixelWidthInBits)/8;
StrideInBytes = (FrameWidth*PixelWidthInBits)/8;
//Compute start location for sub-frame
BlockOffset = (window->StartY * StrideInBytes) + (window->StartX*PixelWidthInBits)/8;
HSizeInBytes = (window->Width * PixelWidthInBits)/8;
StrideInBytes = (FrameWidth * PixelWidthInBits)/8;
StartHPosBytes = (window->StartX * PixelWidthInBits)/8;
/* If DMA engine does not support unaligned transfers then align block
* offset, hsize and stride to next data width boundary
* offset, hsize and stride
* Block offset and Stride are aligned to aximm width
* hsize is aligned to axis width
*/
if(!XVdmaPtr->ReadChannel.HasDRE)
{
alignBytes = XVdmaPtr->ReadChannel.WordLength-1;
BlockOffset = (BlockOffset + alignBytes) & ~(alignBytes);
HSizeInBytes = (HSizeInBytes + alignBytes) & ~(alignBytes);
StrideInBytes = (StrideInBytes + alignBytes) & ~(alignBytes);
StrideInBytes = (StrideInBytes + alignBytes) & ~(alignBytes);
StartHPosBytes = (StartHPosBytes + alignBytes) & ~(alignBytes);
/* align hsize to stream width (axis) */
alignBytes = XVdmaPtr->ReadChannel.StreamWidth;
HSizeInBytes = ((HSizeInBytes+alignBytes-1)/alignBytes)*alignBytes;
}
//Compute start location for sub-frame
BlockOffset = ((window->StartY * StrideInBytes) + StartHPosBytes);
ReadCfg.VertSizeInput = window->Height;
ReadCfg.HoriSizeInput = HSizeInBytes;
@ -541,7 +552,7 @@ void XVprocSs_VdmaDbgReportStatus(XAxiVdma *XVdmaPtr, u32 PixelWidthInBits)
{
xil_printf("\r\n\r\n----->VDMA IP STATUS<----\r\n");
xil_printf("INFO: VDMA Rd/Wr Client Width/Stride defined in Bytes Per Pixel\r\n");
xil_printf("Bytes Per Pixel = %d\r\n\r\n", PixelWidthInBits/8);
xil_printf("Bytes Per Pixel = %d.%d\r\n\r\n", (PixelWidthInBits/8), (PixelWidthInBits%8));
xil_printf("Read Channel Setting \r\n" );
//clear status register before reading
XAxiVdma_ClearDmaChannelErrors(XVdmaPtr, XAXIVDMA_READ, 0xFFFFFFFF);

880
XilinxProcessorIPLib/drivers/vprocss/src/xvprocss.c
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File diff suppressed because it is too large Load diff

129
XilinxProcessorIPLib/drivers/vprocss/src/xvprocss.h
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@ -175,7 +175,7 @@
*
* Ver Who Date Changes
* ----- ---- -------- -------------------------------------------------------
* 1.00 rco 08/17/15 Initial Release
* 1.00 rco 08/28/15 Initial Release
* </pre>
*
@ -196,7 +196,7 @@ extern "C" {
#include "xaxivdma.h"
/**
* Subsystem sub-core header files
* Subsystem sub-core layer 2 header files
* Layer 2 includes Layer-1
*/
#include "xv_csc_l2.h"
@ -209,44 +209,46 @@ extern "C" {
/****************************** Type Definitions ******************************/
/**
* AXIS Switch Port enumeration for Sub-Core connection
* This typedef enumerates the AXIS Switch Port for Sub-Core connection
*/
typedef enum
{
XVPROCSS_RTR_VIDOUT = 0, //M0
XVPROCSS_RTR_SCALER_V, //M1
XVPROCSS_RTR_SCALER_H, //M2
XVPROCSS_RTR_VDMA, //M3
XVPROCSS_RTR_LBOX, //M4
XVPROCSS_RTR_CR_H, //M5
XVPROCSS_RTR_CR_V_IN, //M6
XVPROCSS_RTR_CR_V_OUT, //M7
XVPROCSS_RTR_CSC, //M8
XVPROCSS_RTR_DEINT, //M9
XVPROCSS_RTR_MAX
}XVPROCSS_RTR_MIx_ID;
XVPROCSS_SUBCORE_SCALER_V = 1,
XVPROCSS_SUBCORE_SCALER_H,
XVPROCSS_SUBCORE_VDMA,
XVPROCSS_SUBCORE_LBOX,
XVPROCSS_SUBCORE_CR_H,
XVPROCSS_SUBCORE_CR_V_IN,
XVPROCSS_SUBCORE_CR_V_OUT,
XVPROCSS_SUBCORE_CSC,
XVPROCSS_SUBCORE_DEINT,
XVPROCSS_SUBCORE_MAX
}XVPROCSS_SUBCORE_ID;
/**
* Subsystem Configuration Mode Select
* This typedef enumerates supported subsystem configuration topology
*/
typedef enum
{
XVPROCSS_TOPOLOGY_SCALER_ONLY = 0,
XVPROCSS_TOPOLOGY_FULL_FLEDGED,
XVPROCSS_TOPOLOGY_NUM_SUPPORTED
}XVPROCSS_CONFIG_TOPOLOGY;
/**
* Types of Windows (Sub-frames) available in the Subsystem
* This typedef enumerates types of Windows (Sub-frames) available in the
* Subsystem
*/
typedef enum
{
XVPROCSS_ZOOM_WIN = 0,
XVPROCSS_PIP_WIN,
XVPROCSS_PIXEL_WIN
XVPROCSS_PIXEL_WIN,
XVPROCSS_WIN_NUM_SUPPORTED
}XVprocSs_Win;
/**
* Scaling Modes supported
* This typedef enumerates supported scaling modes
*/
typedef enum
{
@ -256,6 +258,17 @@ typedef enum
XVPROCSS_SCALE_NOT_SUPPORTED
}XVprocSs_ScaleMode;
/** This typedef enumerates supported Color Channels
*
*/
typedef enum
{
XVPROCSS_COLOR_CH_Y_RED = 0,
XVPROCSS_COLOR_CH_CB_GREEN,
XVPROCSS_COLOR_CH_CR_BLUE,
XVPROCSS_COLOR_CH_NUM_SUPPORTED
}XVprocSs_ColorChannel;
/**
* Video Processing Subsystem context scratch pad memory.
* This contains internal flags, state variables, routing table
@ -270,8 +283,8 @@ typedef struct
u32 DeintBufAddr; /**< Deinterlacer field buffer Addr. in DDR */
u8 PixelWidthInBits; /**< Number of bits required to store 1 pixel */
u8 RtngTable[XVPROCSS_RTR_MAX]; /**< Storage for computed routing map */
u8 StartCore[XVPROCSS_RTR_MAX]; /**< Enable flag to start sub-core */
u8 RtngTable[XVPROCSS_SUBCORE_MAX]; /**< Storage for computed routing map */
u8 StartCore[XVPROCSS_SUBCORE_MAX]; /**< Enable flag to start sub-core */
u8 RtrNumCores; /**< Number of sub-cores in routing map */
u8 ScaleMode; /**< Stored computed scaling mode - UP/DN/1:1 */
u8 MemEn; /**< Flag to indicate if stream routes through memory */
@ -381,9 +394,21 @@ typedef struct
/************************** Macros Definitions *******************************/
/*****************************************************************************/
/**
* This macro checks if subsystem is in Maximum configuration mode
* This macro returns the subsystem topology
*
* @param XVprocSsPtr is a pointer to the Video Processing subsystem instance
*
* @return XVPROCSS_TOPOLOGY_FULL_FLEDGED or XVPROCSS_TOPOLOGY_SCALER_ONLY
*
*****************************************************************************/
#define XVprocSs_GetSubsystemTopology(XVprocSsPtr) \
((XVprocSsPtr)->Config.Topology)
/*****************************************************************************/
/**
* This macro checks if subsystem is in Maximum (Full_Fledged) configuration
*
* @param XVprocSsPtr is a pointer to the Video Processing subsystem instance
*
* @return Return 1 if condition is TRUE or 0 if FALSE
*
*****************************************************************************/
@ -427,6 +452,19 @@ typedef struct
*****************************************************************************/
#define XVprocSs_IsZoomModeOn(XVprocSsPtr) ((XVprocSsPtr)->CtxtData.ZoomEn)
/*****************************************************************************/
/**
* This macro returns the Pip/Zoom window horizontal increment size
*
* @param XVprocSsPtr is a pointer to the Video Processing subsystem instance
*
* @return Pixel H Step size
*
*****************************************************************************/
#define XVprocSs_GetPipZoomWinHStepSize(XVprocSsPtr) \
((XVprocSsPtr)->CtxtData.PixelHStepSize)
/*****************************************************************************/
/**
* This macro clears the PIP mode flag stored in subsystem internal scratch
@ -513,13 +551,54 @@ void XVprocSs_GetZoomPipWindow(XVprocSs *InstancePtr,
XVidC_VideoWindow *win);
void XVprocSs_UpdateZoomPipWindow(XVprocSs *InstancePtr);
/* Picture Control functions */
s32 XVprocSs_GetPictureBrightness(XVprocSs *InstancePtr);
void XVprocSs_SetPictureBrightness(XVprocSs *InstancePtr, s32 NewValue);
s32 XVprocSs_GetPictureContrast(XVprocSs *InstancePtr);
void XVprocSs_SetPictureContrast(XVprocSs *InstancePtr, s32 NewValue);
s32 XVprocSs_GetPictureSaturation(XVprocSs *InstancePtr);
void XVprocSs_SetPictureSaturation(XVprocSs *InstancePtr, s32 NewValue);
s32 XVprocSs_GetPictureGain(XVprocSs *InstancePtr,
XVprocSs_ColorChannel ChId);
void XVprocSs_SetPictureGain(XVprocSs *InstancePtr,
XVprocSs_ColorChannel ChId,
s32 NewValue);
XVidC_ColorStd XVprocSs_GetPictureColorStdIn(XVprocSs *InstancePtr);
void XVprocSs_SetPictureColorStdIn(XVprocSs *InstancePtr,
XVidC_ColorStd NewVal);
XVidC_ColorStd XVprocSs_GetPictureColorStdOut(XVprocSs *InstancePtr);
void XVprocSs_SetPictureColorStdOut(XVprocSs *InstancePtr,
XVidC_ColorStd NewVal);
XVidC_ColorRange XVprocSs_GetPictureColorRange(XVprocSs *InstancePtr);
void XVprocSs_SetPictureColorRange(XVprocSs *InstancePtr,
XVidC_ColorRange NewVal);
int XVprocSs_SetPictureActiveWindow(XVprocSs *InstancePtr,
XVidC_VideoWindow *Win);
void XVprocSs_SetPIPBackgroundColor(XVprocSs *InstancePtr,
XLboxColorId ColorId);
/* External Filter Load functions */
void XVprocSs_LoadScalerCoeff(XVprocSs *InstancePtr,
u32 CoreId,
u16 num_phases,
u16 num_taps,
const short *Coeff);
void XVprocSs_LoadChromaResamplerCoeff(XVprocSs *InstancePtr,
u32 CoreId,
u16 num_taps,
const short *Coeff);
/* Debug functions */
void XVprocSs_ReportSubsystemConfig(XVprocSs *InstancePtr);
void XVprocSs_ReportSubsystemCoreInfo(XVprocSs *InstancePtr);
void XVprocSs_ReportSubcoreStatus(XVprocSs *InstancePtr,
u32 SubcoreId);
void XVprocSs_SetUserTimerHandler(XVprocSs *InstancePtr,
XVidC_DelayHandler CallbackFunc,
void *CallbackRef);
void XVprocSs_ReportCoreInfo(XVprocSs *InstancePtr);
void XVprocSs_ReportSubsystemConfig(XVprocSs *InstancePtr);
#ifdef __cplusplus
}
#endif

13
XilinxProcessorIPLib/drivers/vprocss/src/xvprocss_coreinit.c
View file

@ -370,12 +370,6 @@ int XVprocSs_SubcoreInitHScaler(XVprocSs *XVprocSsPtr)
xil_printf("VPROCSS ERR:: Horiz. Scaler Initialization failed\r\n");
return(XST_FAILURE);
}
if(XVprocSsPtr->HscalerPtr->Config.ScalerType == XV_HSCALER_POLYPHASE)
{
/* Load Default filter coefficients */
XV_HScalerLoadDefaultCoeff(XVprocSsPtr->HscalerPtr, &XVprocSsPtr->HscL2Reg);
}
}
return(XST_SUCCESS);
}
@ -429,13 +423,6 @@ int XVprocSs_SubcoreInitVScaler(XVprocSs *XVprocSsPtr)
xil_printf("VPROCSS ERR:: Vert. Scaler Initialization failed\r\n");
return(XST_FAILURE);
}
if(XVprocSsPtr->VscalerPtr->Config.ScalerType == XV_VSCALER_POLYPHASE)
{
/* Load Default filter coefficients */
XV_VScalerLoadDefaultCoeff(XVprocSsPtr->VscalerPtr, &XVprocSsPtr->VscL2Reg);
}
}
return(XST_SUCCESS);
}

103
XilinxProcessorIPLib/drivers/vprocss/src/xvprocss_router.c
View file

@ -59,7 +59,8 @@
/************************** Constant Definitions *****************************/
/* AXIS Switch Port# connected to input stream */
#define AXIS_SWITCH_VIDIN_S0 (0)
#define XVPROCSS_AXIS_SWITCH_VIDIN_S0 (0)
#define XVPROCSS_AXIS_SWITCH_VIDOUT_M0 (0)
/************************** Function Prototypes ******************************/
static int validateWindowSize(const XVidC_VideoWindow *win,
@ -206,7 +207,7 @@ static XVprocSs_ScaleMode GetScalingMode(XVprocSs *XVprocSsPtr)
int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
{
#ifdef DEBUG
const char *ipStr[XVPROCSS_RTR_MAX] =
const char *ipStr[XVPROCSS_SUBCORE_MAX] =
{
"VID_OUT",
"SCALER-V",
@ -250,35 +251,35 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
/* Check if input is I/P */
if(StrmInPtr->IsInterlaced)
{
pTable[index++] = XVPROCSS_RTR_DEINT;
pTable[index++] = XVPROCSS_SUBCORE_DEINT;
}
/* Check if input is 420 */
if(StrmInPtr->ColorFormatId == XVIDC_CSF_YCRCB_420)
{
//up-sample vertically to 422 as none of the IP supports 420
pTable[index++] = XVPROCSS_RTR_CR_V_IN;
pTable[index++] = XVPROCSS_SUBCORE_CR_V_IN;
CtxtPtr->StrmCformat = XVIDC_CSF_YCRCB_422;
}
switch(CtxtPtr->ScaleMode)
{
case XVPROCSS_SCALE_1_1:
pTable[index++] = XVPROCSS_RTR_VDMA;
pTable[index++] = XVPROCSS_SUBCORE_VDMA;
CtxtPtr->MemEn = TRUE;
break;
case XVPROCSS_SCALE_UP:
pTable[index++] = XVPROCSS_RTR_VDMA; /* VDMA is before Scaler */
pTable[index++] = XVPROCSS_RTR_SCALER_V;
pTable[index++] = XVPROCSS_RTR_SCALER_H;
pTable[index++] = XVPROCSS_SUBCORE_VDMA; /* VDMA is before Scaler */
pTable[index++] = XVPROCSS_SUBCORE_SCALER_V;
pTable[index++] = XVPROCSS_SUBCORE_SCALER_H;
CtxtPtr->MemEn = TRUE;
break;
case XVPROCSS_SCALE_DN:
pTable[index++] = XVPROCSS_RTR_SCALER_H;
pTable[index++] = XVPROCSS_RTR_SCALER_V;
pTable[index++] = XVPROCSS_RTR_VDMA; /* VDMA is after Scaler */
pTable[index++] = XVPROCSS_SUBCORE_SCALER_H;
pTable[index++] = XVPROCSS_SUBCORE_SCALER_V;
pTable[index++] = XVPROCSS_SUBCORE_VDMA; /* VDMA is after Scaler */
CtxtPtr->MemEn = TRUE;
break;
@ -289,7 +290,7 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
}
/* Send stream to LBox to add H/V bars, if needed */
pTable[index++] = XVPROCSS_RTR_LBOX;
pTable[index++] = XVPROCSS_SUBCORE_LBOX;
/* Check for input and output color format to derive required conversions */
switch(StrmOutPtr->ColorFormatId)
@ -298,9 +299,9 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
switch(StrmInPtr->ColorFormatId)
{
case XVIDC_CSF_RGB:
pTable[index++] = XVPROCSS_RTR_CSC; //convert RGB->444
pTable[index++] = XVPROCSS_RTR_CR_H; //convert 444->422
pTable[index++] = XVPROCSS_RTR_CR_V_OUT; //convert 422->420
pTable[index++] = XVPROCSS_SUBCORE_CSC; //convert RGB->444
pTable[index++] = XVPROCSS_SUBCORE_CR_H; //convert 444->422
pTable[index++] = XVPROCSS_SUBCORE_CR_V_OUT; //convert 422->420
CtxtPtr->CscIn = XVIDC_CSF_RGB;
CtxtPtr->CscOut = XVIDC_CSF_YCRCB_444;
CtxtPtr->HcrIn = XVIDC_CSF_YCRCB_444;
@ -308,9 +309,9 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
break;
case XVIDC_CSF_YCRCB_444:
pTable[index++] = XVPROCSS_RTR_CSC; //picture control in 444
pTable[index++] = XVPROCSS_RTR_CR_H; //convert 444->422
pTable[index++] = XVPROCSS_RTR_CR_V_OUT; //convert 422->420
pTable[index++] = XVPROCSS_SUBCORE_CSC; //picture control in 444
pTable[index++] = XVPROCSS_SUBCORE_CR_H; //convert 444->422
pTable[index++] = XVPROCSS_SUBCORE_CR_V_OUT; //convert 422->420
CtxtPtr->CscIn = XVIDC_CSF_YCRCB_444;
CtxtPtr->CscOut = XVIDC_CSF_YCRCB_444;
CtxtPtr->HcrIn = XVIDC_CSF_YCRCB_444;
@ -319,8 +320,8 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
case XVIDC_CSF_YCRCB_422:
case XVIDC_CSF_YCRCB_420: //Input was up converted to 422
pTable[index++] = XVPROCSS_RTR_CSC; //picture control in 422
pTable[index++] = XVPROCSS_RTR_CR_V_OUT; //convert 422->420
pTable[index++] = XVPROCSS_SUBCORE_CSC; //picture control in 422
pTable[index++] = XVPROCSS_SUBCORE_CR_V_OUT; //convert 422->420
CtxtPtr->CscIn = XVIDC_CSF_YCRCB_422;
CtxtPtr->CscOut = XVIDC_CSF_YCRCB_422;
break;
@ -337,15 +338,15 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
{
case XVIDC_CSF_RGB:
case XVIDC_CSF_YCRCB_444: //convert 444->RGB
pTable[index++] = XVPROCSS_RTR_CSC;
pTable[index++] = XVPROCSS_SUBCORE_CSC;
CtxtPtr->CscIn = StrmInPtr->ColorFormatId;
CtxtPtr->CscOut = XVIDC_CSF_RGB;
break;
case XVIDC_CSF_YCRCB_422:
case XVIDC_CSF_YCRCB_420: //Input was up converted to 422
pTable[index++] = XVPROCSS_RTR_CR_H; //convert 422->444
pTable[index++] = XVPROCSS_RTR_CSC; //convert 444->RGB
pTable[index++] = XVPROCSS_SUBCORE_CR_H; //convert 422->444
pTable[index++] = XVPROCSS_SUBCORE_CSC; //convert 444->RGB
CtxtPtr->HcrIn = XVIDC_CSF_YCRCB_422;
CtxtPtr->HcrOut = XVIDC_CSF_YCRCB_444;
CtxtPtr->CscIn = XVIDC_CSF_YCRCB_444;
@ -363,8 +364,8 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
switch(StrmInPtr->ColorFormatId)
{
case XVIDC_CSF_RGB:
pTable[index++] = XVPROCSS_RTR_CSC; //convert RGB->444
pTable[index++] = XVPROCSS_RTR_CR_H; //convert 444->422
pTable[index++] = XVPROCSS_SUBCORE_CSC; //convert RGB->444
pTable[index++] = XVPROCSS_SUBCORE_CR_H; //convert 444->422
CtxtPtr->CscIn = XVIDC_CSF_RGB;
CtxtPtr->CscOut = XVIDC_CSF_YCRCB_444;
CtxtPtr->HcrIn = XVIDC_CSF_YCRCB_444;
@ -372,8 +373,8 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
break;
case XVIDC_CSF_YCRCB_444:
pTable[index++] = XVPROCSS_RTR_CSC; //picture control in 444
pTable[index++] = XVPROCSS_RTR_CR_H; //convert 444->422
pTable[index++] = XVPROCSS_SUBCORE_CSC; //picture control in 444
pTable[index++] = XVPROCSS_SUBCORE_CR_H; //convert 444->422
CtxtPtr->CscIn = XVIDC_CSF_YCRCB_444;
CtxtPtr->CscOut = XVIDC_CSF_YCRCB_444;
CtxtPtr->HcrIn = XVIDC_CSF_YCRCB_444;
@ -382,7 +383,7 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
case XVIDC_CSF_YCRCB_422:
case XVIDC_CSF_YCRCB_420: //Input was up converted to 422
pTable[index++] = XVPROCSS_RTR_CSC; //picture control in 422
pTable[index++] = XVPROCSS_SUBCORE_CSC; //picture control in 422
CtxtPtr->CscIn = XVIDC_CSF_YCRCB_422;
CtxtPtr->CscOut = XVIDC_CSF_YCRCB_422;
break;
@ -399,15 +400,15 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
{
case XVIDC_CSF_RGB: //convert 444->RGB
case XVIDC_CSF_YCRCB_444:
pTable[index++] = XVPROCSS_RTR_CSC;
pTable[index++] = XVPROCSS_SUBCORE_CSC;
CtxtPtr->CscIn = StrmInPtr->ColorFormatId;
CtxtPtr->CscOut = XVIDC_CSF_YCRCB_444;
break;
case XVIDC_CSF_YCRCB_422:
case XVIDC_CSF_YCRCB_420: //Input was up converted to 422
pTable[index++] = XVPROCSS_RTR_CR_H; //convert 422->444
pTable[index++] = XVPROCSS_RTR_CSC; //picture control
pTable[index++] = XVPROCSS_SUBCORE_CR_H; //convert 422->444
pTable[index++] = XVPROCSS_SUBCORE_CSC; //picture control
CtxtPtr->HcrIn = XVIDC_CSF_YCRCB_422;
CtxtPtr->HcrOut = XVIDC_CSF_YCRCB_444;
CtxtPtr->CscIn = XVIDC_CSF_YCRCB_444;
@ -428,7 +429,7 @@ int XVprocSs_BuildRoutingTable(XVprocSs *XVprocSsPtr)
}
/* Connect Last IP in chain to switch output */
pTable[index++] = XVPROCSS_RTR_VIDOUT;
pTable[index++] = XVPROCSS_AXIS_SWITCH_VIDOUT_M0;
/* save number of cores in processing path */
CtxtPtr->RtrNumCores = index;
@ -475,7 +476,7 @@ void XVprocSs_ProgRouterMux(XVprocSs *XVprocSsPtr)
/* Connect Input Stream to the 1st core in path */
nextMi = prevSi = pTable[0];
XAxisScr_MiPortEnable(XVprocSsPtr->RouterPtr, nextMi, AXIS_SWITCH_VIDIN_S0);
XAxisScr_MiPortEnable(XVprocSsPtr->RouterPtr, nextMi, XVPROCSS_AXIS_SWITCH_VIDIN_S0);
/* Traverse routing map and connect cores in the chain */
for(count=1; count<numProcElem; ++count)
@ -542,14 +543,14 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
default:
break;
}
StartCorePtr[XVPROCSS_RTR_VDMA] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_VDMA] = TRUE;
}
for(count=0; count<CtxtPtr->RtrNumCores; ++count)
{
switch(pTable[count])
{
case XVPROCSS_RTR_SCALER_V:
case XVPROCSS_SUBCORE_SCALER_V:
if(XVprocSsPtr->VscalerPtr)
{
if(CtxtPtr->ScaleMode == XVPROCSS_SCALE_DN)
@ -578,11 +579,11 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
vsc_WidthIn,
vsc_HeightIn,
vsc_HeightOut);
StartCorePtr[XVPROCSS_RTR_SCALER_V] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_SCALER_V] = TRUE;
}
break;
case XVPROCSS_RTR_SCALER_H:
case XVPROCSS_SUBCORE_SCALER_H:
if(XVprocSsPtr->HscalerPtr)
{
if(CtxtPtr->ScaleMode == XVPROCSS_SCALE_DN)
@ -610,15 +611,15 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
hsc_WidthIn,
hsc_WidthOut,
XVprocSsPtr->CtxtData.StrmCformat);
StartCorePtr[XVPROCSS_RTR_SCALER_H] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_SCALER_H] = TRUE;
}
break;
case XVPROCSS_RTR_VDMA:
case XVPROCSS_SUBCORE_VDMA:
/* NOP - Programmed before the switch statement */
break;
case XVPROCSS_RTR_LBOX:
case XVPROCSS_SUBCORE_LBOX:
if(XVprocSsPtr->LboxPtr)
{
if(XVprocSs_IsPipModeOn(XVprocSsPtr))
@ -645,11 +646,11 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
XVprocSsPtr->CtxtData.StrmCformat,
XVprocSsPtr->VidOut.ColorDepth);
StartCorePtr[XVPROCSS_RTR_LBOX] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_LBOX] = TRUE;
}
break;
case XVPROCSS_RTR_CR_H:
case XVPROCSS_SUBCORE_CR_H:
if(XVprocSsPtr->HcrsmplrPtr)
{
XV_HCrsmplSetActiveSize(XVprocSsPtr->HcrsmplrPtr,
@ -660,11 +661,11 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
&XVprocSsPtr->HcrL2Reg,
CtxtPtr->HcrIn,
CtxtPtr->HcrOut);
StartCorePtr[XVPROCSS_RTR_CR_H] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_CR_H] = TRUE;
}
break;
case XVPROCSS_RTR_CR_V_IN:
case XVPROCSS_SUBCORE_CR_V_IN:
if(XVprocSsPtr->VcrsmplrInPtr)
{
XV_VCrsmplSetActiveSize(XVprocSsPtr->VcrsmplrInPtr,
@ -675,11 +676,11 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
&XVprocSsPtr->VcrInL2Reg,
XVIDC_CSF_YCRCB_420,
XVIDC_CSF_YCRCB_422);
StartCorePtr[XVPROCSS_RTR_CR_V_IN] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_CR_V_IN] = TRUE;
}
break;
case XVPROCSS_RTR_CR_V_OUT:
case XVPROCSS_SUBCORE_CR_V_OUT:
if(XVprocSsPtr->VcrsmplrOutPtr)
{
XV_VCrsmplSetActiveSize(XVprocSsPtr->VcrsmplrOutPtr,
@ -690,11 +691,11 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
&XVprocSsPtr->VcrOutL2Reg,
XVIDC_CSF_YCRCB_422,
XVIDC_CSF_YCRCB_420);
StartCorePtr[XVPROCSS_RTR_CR_V_OUT] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_CR_V_OUT] = TRUE;
}
break;
case XVPROCSS_RTR_CSC:
case XVPROCSS_SUBCORE_CSC:
if(XVprocSsPtr->CscPtr)
{
XV_CscSetColorspace(XVprocSsPtr->CscPtr,
@ -709,11 +710,11 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
XVprocSsPtr->VidOut.Timing.HActive,
XVprocSsPtr->VidOut.Timing.VActive);
StartCorePtr[XVPROCSS_RTR_CSC] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_CSC] = TRUE;
}
break;
case XVPROCSS_RTR_DEINT:
case XVPROCSS_SUBCORE_DEINT:
if(XVprocSsPtr->DeintPtr)
{
xdbg_printf(XDBG_DEBUG_GENERAL," -> Configure Deinterlacer for %dx%d to %dx%d\r\n", \
@ -733,7 +734,7 @@ void XVprocSs_SetupRouterDataFlow(XVprocSs *XVprocSsPtr)
XVprocSsPtr->VidIn.Timing.VActive); //field height
XV_deinterlacer_Set_invert_field_id(XVprocSsPtr->DeintPtr, 0); //TBD
StartCorePtr[XVPROCSS_RTR_DEINT] = TRUE;
StartCorePtr[XVPROCSS_SUBCORE_DEINT] = TRUE;
}
break;
}