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emacps: Update upper 32 bits of queue pointer address

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For 64 bit address, upper 32 bits should be updated in respective
TX and RX queue pointer registers. For tx, typecast with u32 should not
be there; remove it. For rx, update the correspondign register.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
Harini Katakam 2015-08-10 20:11:54 +05:30 • committed by Nava kishore Manne
parent 6066ca5b0b
commit ce83a9b664
3 changed files with 17 additions and 5 deletions
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16
XilinxProcessorIPLib/drivers/emacps/src/xemacps.c
View file

@ -51,6 +51,7 @@
* 3.0 hk 02/20/15 Added support for jumbo frames. Increase AHB burst.
* Disable extended mode. Perform all 64 bit changes under
* check for arch64.
* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr registers
*
* </pre>
******************************************************************************/
@ -470,10 +471,17 @@ void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum,
(QPtr & ULONG64_LO_MASK));
}
#ifdef __aarch64__
/* Set the MSB of Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_QBASE_OFFSET,
(u32)((QPtr & (u32)ULONG64_HI_MASK) >> 32U));
if (Direction == XEMACPS_SEND) {
/* Set the MSB of TX Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_TXQBASE_OFFSET,
(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
} else {
/* Set the MSB of RX Queue start address */
XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
XEMACPS_MSBBUF_RXQBASE_OFFSET,
(u32)((QPtr & ULONG64_HI_MASK) >> 32U));
}
#endif
}
/** @} */

1
XilinxProcessorIPLib/drivers/emacps/src/xemacps.h
View file

@ -314,6 +314,7 @@
* Remove "used bit set" from TX error interrupt masks.
* 3.1 hk 07/27/15 Do not call error handler with '0' error code when
* there is no error. CR# 869403
* 08/10/15 Update upper 32 bit tx and rx queue ptr registers.
* </pre>
*
****************************************************************************/

5
XilinxProcessorIPLib/drivers/emacps/src/xemacps_hw.h
View file

@ -59,6 +59,7 @@
* 3.0 kvn 02/13/15 Modified code for MISRA-C:2012 compliance.
* 3.0 hk 03/18/15 Added support for jumbo frames.
* Remove "used bit set" from TX error interrupt masks.
* 3.1 hk 08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
* </pre>
*
******************************************************************************/
@ -300,7 +301,9 @@ typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
reg */
#define XEMACPS_RXQ1BASE_OFFSET 0x00000480U /**< RX Q1 Base address
reg */
#define XEMACPS_MSBBUF_QBASE_OFFSET 0x000004C8U /**< MSB Buffer Q Base
#define XEMACPS_MSBBUF_TXQBASE_OFFSET 0x000004C8U /**< MSB Buffer TX Q Base
reg */
#define XEMACPS_MSBBUF_RXQBASE_OFFSET 0x000004D4U /**< MSB Buffer RX Q Base
reg */
#define XEMACPS_INTQ1_IER_OFFSET 0x00000600U /**< Interrupt Q1 Enable
reg */