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sw_apps:zynqmp_fsbl: Modified PMU Trigger logic

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This patch corrects the logic used to trigger PMU_0 IPI.
Also added code to Enable PMU_0 IPI.

Signed-off-by: RamyaSree <rdarapun@xilinx.com>
Acked-by: Sarat Chand Savitala <saratcha@xilinx.com>
This commit is contained in:
RamyaSree 2015-10-13 20:44:05 +05:30 • committed by Nava kishore Manne
parent 5594d1f3fc
commit d29d6bdcd0
2 changed files with 8 additions and 2 deletions
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5
lib/sw_apps/zynqmp_fsbl/src/xfsbl_hw.h
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@ -470,7 +470,10 @@ extern "C" {
/* Register: IPI_PMU_0_TRIG */
#define IPI_PMU_0_TRIG ( ( IPI_BASEADDR ) + 0X00030000U )
#define IPI_APU_TRIG_PMU_0_SHIFT 16U
#define IPI_PMU_0_TRIG_PMU_0_MASK 0X00010000U
#define IPI_PMU_0_IER ( ( IPI_BASEADDR ) + 0X00030018U )
#define IPI_PMU_0_IER_PMU_0_MASK 0X00010000U
/**************************** Type Definitions *******************************/

5
lib/sw_apps/zynqmp_fsbl/src/xfsbl_partition_load.c
View file

@ -907,8 +907,11 @@ static u32 XFsbl_PartitionCopy(XFsblPs * FsblInstancePtr, u32 PartitionNum)
if (DestinationDevice == XIH_PH_ATTRB_DEST_DEVICE_PMU)
{
/* Enable PMU_0 IPI */
XFsbl_Out32(IPI_PMU_0_IER, IPI_PMU_0_IER_PMU_0_MASK);
/* Trigger PMU0 IPI in PMU IPI TRIG Reg */
XFsbl_Out32(IPI_PMU_0_TRIG, IPI_APU_TRIG_PMU_0_SHIFT);
XFsbl_Out32(IPI_PMU_0_TRIG, IPI_PMU_0_TRIG_PMU_0_MASK);
/**
* Wait until PMU Microblaze goes to sleep state,