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qspipsu: Change comment about bus width of dummy entry

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The recommendation from design is to have bus width of dummy entry =
bus width of address phase (whether this is 1, 2 or 4).
This code will remain same irrespective of QEMU. Hence change the comment.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
This commit is contained in:
Harini Katakam 2015-04-28 12:16:30 +05:30 • committed by Nava kishore Manne
parent b2ef81cba0
commit daedbcdf08
2 changed files with 4 additions and 6 deletions
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5
XilinxProcessorIPLib/drivers/qspipsu_v1_1/examples/xqspipsu_generic_flash_interrupt_example.c
View file

@ -1236,9 +1236,8 @@ int FlashRead(XQspiPsu *QspiPsuPtr, u32 Address, u32 ByteCount, u8 Command,
/* Update Dummy cycles as per flash specs for QUAD IO */
/*
* Silicon and REMUS do not care what the SPI mode is
* for dummies, but QEMU expects it to match the address
* phase. Make it so.
* Bus width of dummy phase is recommended to be the same as
* address phase
*/
FlashMsg[1].BusWidth = FlashMsg[0].BusWidth;

5
XilinxProcessorIPLib/drivers/qspipsu_v1_1/examples/xqspipsu_generic_flash_polled_example.c
View file

@ -1154,9 +1154,8 @@ int FlashRead(XQspiPsu *QspiPsuPtr, u32 Address, u32 ByteCount, u8 Command,
/* Update Dummy cycles as per flash specs for QUAD IO */
/*
* Silicon and REMUS do not care what the SPI mode is
* for dummies, but QEMU expects it to match the address
* phase. Make it so.
* Bus width of dummy phase is recommended to be the same as
* address phase
*/
FlashMsg[1].BusWidth = FlashMsg[0].BusWidth;