dp: rx: Added core masks, shifts, and register values.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion
Nava kishore Manne
parent
178a11326e
commit
e0d0e0c1e7
2 changed files with 633 additions and 104 deletions
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@ -73,7 +73,8 @@
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#define XDPRX_USER_PIXEL_WIDTH 0x010 /**< Selects the width of the
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user data input port. */
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#define XDPRX_INTERRUPT_MASK 0x014 /**< Masks the specified
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interrupt sources. */
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interrupt sources for
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stream 1. */
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#define XDPRX_MISC_CTRL 0x018 /**< Miscellaneous control of
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RX behavior. */
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#define XDPRX_SOFT_RESET 0x01C /**< Software reset. */
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@ -116,7 +117,8 @@
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payload allocation, and
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for the AUX channel. */
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#define XDPRX_INTERRUPT_MASK_1 0x044 /**< Masks the specified
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interrupt sources. */
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interrupt sources for
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streams 2, 3, 4. */
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#define XDPRX_INTERRUPT_CAUSE_1 0x048 /**< Indicates the cause of a
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pending host interrupts
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for streams 2, 3, 4. */
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@ -455,6 +457,625 @@
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(XDPRX_SINK_DEVICE_SPECIFIC_FIELD + (4 * RegNum))
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/* @} */
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/******************************************************************************/
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/** @name DPRX core masks, shifts, and register values.
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* @{
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*/
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/* 0x004: AUX_CLK_DIVIDER */
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#define XDPRX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF /**< Clock divider value. */
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#define XDPRX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK \
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0xFF00 /**< AUX (noise) signal width
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filter. */
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#define XDPRX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \
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8 /**< Shift bits for AUX signal
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width filter. */
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/* 0x010: USER_PIXEL_WIDTH */
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#define XDPRX_USER_PIXEL_WIDTH_1 0x1 /**< Single pixel wide
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interface. */
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#define XDPRX_USER_PIXEL_WIDTH_2 0x2 /**< Dual pixel output mode. */
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#define XDPRX_USER_PIXEL_WIDTH_4 0x4 /**< Quad pixel output mode. */
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/* 0x014: INTERRUPT_MASK */
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#define XDPRX_INTERRUPT_MASK_VM_CHANGE_MASK \
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0x00001 /**< Mask the interrupt
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assertion for a
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resolution change, as
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detected from the MSA
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fields. */
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#define XDPRX_INTERRUPT_MASK_POWER_STATE_MASK \
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0x00002 /**< Mask the interrupt
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assertion for a power
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state change. */
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#define XDPRX_INTERRUPT_MASK_NO_VIDEO_MASK \
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0x00004 /**< Mask the interrupt
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assertion for the
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no-video condition being
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detected after active
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video received. */
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#define XDPRX_INTERRUPT_MASK_VBLANK_MASK \
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0x00008 /**< Mask the interrupt
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assertion for the start
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of the blanking
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interval. */
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#define XDPRX_INTERRUPT_MASK_TRAINING_LOST_MASK \
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0x00010 /**< Mask the interrupt
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assertion for training
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loss on active lanes. */
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#define XDPRX_INTERRUPT_MASK_VIDEO_MASK 0x00040 /**< Mask the interrupt
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assertion for a valid
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video frame being
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detected on the main
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link. Video interrupt is
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set after a delay of 8
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video frames following a
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valid scrambler reset
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character. */
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#define XDPRX_INTERRUPT_MASK_INFO_PKT_MASK \
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0x00100 /**< Mask the interrupt
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assertion for an audio
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info packet being
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received. */
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#define XDPRX_INTERRUPT_MASK_EXT_PKT_MASK \
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0x00200 /**< Mask the interrupt
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assertion for an audio
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extension packet being
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received. */
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#define XDPRX_INTERRUPT_MASK_VCP_ALLOC_MASK \
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0x00400 /**< Mask the interrupt
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assertion for a virtual
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channel payload being
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allocated. */
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#define XDPRX_INTERRUPT_MASK_VCP_DEALLOC_MASK \
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0x00800 /**< Mask the interrupt
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assertion for a virtual
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channel payload being
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allocated. */
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#define XDPRX_INTERRUPT_MASK_DOWN_REPLY_MASK \
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0x01000 /**< Mask the interrupt
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assertion for a
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downstream reply being
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ready. */
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#define XDPRX_INTERRUPT_MASK_DOWN_REQUEST_MASK \
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0x02000 /**< Mask the interrupt
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assertion for a
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downstream request being
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ready. */
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#define XDPRX_INTERRUPT_MASK_TRAINING_DONE_MASK \
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0x04000 /**< Mask the interrupt
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assertion for link
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training completion. */
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#define XDPRX_INTERRUPT_MASK_BW_CHANGE_MASK \
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0x08000 /**< Mask the interrupt
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assertion for a change
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in bandwidth. */
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#define XDPRX_INTERRUPT_MASK_TP1_MASK 0x10000 /**< Mask the interrupt
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assertion for start of
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training pattern 1. */
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#define XDPRX_INTERRUPT_MASK_TP2_MASK 0x20000 /**< Mask the interrupt
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assertion for start of
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training pattern 2. */
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#define XDPRX_INTERRUPT_MASK_TP3_MASK 0x40000 /**< Mask the interrupt
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assertion for start of
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training pattern 3. */
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#define XDPRX_INTERRUPT_MASK_ALL_MASK 0x7FFFF /**< Mask all interrupts. */
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/* 0x018: MISC_CTRL */
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#define XDPRX_MISC_CTRL_USE_FILT_MSA_MASK \
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0x1 /**< When set, two matching
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values must be detected
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for each field of the
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MSA values before the
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associated register is
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updated internally. */
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#define XDPRX_MISC_CTRL_LONG_I2C_USE_DEFER_MASK \
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0x2 /**< When set, the long I2C
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write data transfwers
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are responded to using
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DEFER instead of partial
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ACKs. */
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#define XDPRX_MISC_CTRL_I2C_USE_AUX_DEFER_MASK \
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0x4 /**< When set, I2C DEFERs will
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be sent as AUX DEFERs to
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the source device. */
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/* 0x01C: SOFT_RESET */
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#define XDPRX_SOFT_RESET_VIDEO_MASK 0x01 /**< Reset the video logic. */
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#define XDPRX_SOFT_RESET_AUX_MASK 0x80 /**< Reset the AUX logic. */
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/* 0x02C: HPD_INTERRUPT */
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#define XDPRX_HPD_INTERRUPT_ASSERT_MASK \
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0x00000001 /**< Instructs the RX core to
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assert an interrupt to
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the TX using the HPD
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signal. */
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#define XDPRX_HPD_INTERRUPT_LENGTH_US_MASK \
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0xFFFF0000 /**< The length of the HPD pulse
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to generate (in
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microseconds). */
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#define XDPRX_HPD_INTERRUPT_LENGTH_US_SHIFT 16 /**< Shift bits for the HPD
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pulse length. */
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/* 0x040: INTERRUPT_CAUSE */
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#define XDPRX_INTERRUPT_CAUSE_VM_CHANGE_MASK \
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XDPRX_INTERRUPT_MASK_VM_CHANGE_MASK /**< Interrupt caused by a
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resolution change, as
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detected from the MSA
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fields. */
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#define XDPRX_INTERRUPT_CAUSE_POWER_STATE_MASK \
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XDPRX_INTERRUPT_MASK_POWER_STATE_MASK /**< Interrupt caused by a
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power state change. */
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#define XDPRX_INTERRUPT_CAUSE_NO_VIDEO_MASK \
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XDPRX_INTERRUPT_MASK_NO_VIDEO_MASK /**< Interrupt caused by the
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no-video condition being
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detected after active
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video received. */
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#define XDPRX_INTERRUPT_CAUSE_VBLANK_MASK \
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XDPRX_INTERRUPT_MASK_VBLANK_MASK /**< Interrupt caused by the
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start of the blanking
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interval. */
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#define XDPRX_INTERRUPT_CAUSE_TRAINING_LOST_MASK \
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XDPRX_INTERRUPT_MASK_TRAINING_LOST_MASK /**< Interrupt caused by
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training loss on active
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lanes. */
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#define XDPRX_INTERRUPT_CAUSE_VIDEO_MASK \
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XDPRX_INTERRUPT_MASK_VIDEO_MASK /**< Interrupt caused by a valid
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video frame being
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detected on the main
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link. Video interrupt is
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set after a delay of 8
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video frames following a
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valid scrambler reset
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character. */
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#define XDPRX_INTERRUPT_CAUSE_INFO_PKT_MASK \
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XDPRX_INTERRUPT_MASK_INFO_PKT_MASK /**< Interrupt caused by an
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audio info packet being
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received. */
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#define XDPRX_INTERRUPT_CAUSE_EXT_PKT_MASK \
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XDPRX_INTERRUPT_MASK_EXT_PKT_MASK /**< Interrupt caused by an
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audio extension packet
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being received. */
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#define XDPRX_INTERRUPT_CAUSE_VCP_ALLOC_MASK \
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XDPRX_INTERRUPT_MASK_VCP_ALLOC_MASK /**< Interrupt caused by a
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virtual channel payload
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being allocated. */
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#define XDPRX_INTERRUPT_CAUSE_VCP_DEALLOC_MASK \
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XDPRX_INTERRUPT_MASK_VCP_DEALLOC_MASK /**< Interrupt caused by a
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virtual channel payload
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being allocated. */
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#define XDPRX_INTERRUPT_CAUSE_DOWN_REPLY_MASK \
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XDPRX_INTERRUPT_MASK_DOWN_REPLY_MASK /**< Interrupt caused by a
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downstream reply being
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ready. */
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#define XDPRX_INTERRUPT_CAUSE_DOWN_REQUEST_MASK \
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XDPRX_INTERRUPT_MASK_DOWN_REQUEST_MASK /**< Interrupt caused by a
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downstream request being
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ready. */
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#define XDPRX_INTERRUPT_CAUSE_TRAINING_DONE_MASK \
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XDPRX_INTERRUPT_MASK_TRAINING_DONE_MASK /**< Interrupt caused by link
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training completion. */
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#define XDPRX_INTERRUPT_CAUSE_BW_CHANGE_MASK \
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XDPRX_INTERRUPT_MASK_BW_CHANGE_MASK /**< Interrupt caused by a
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change in bandwidth. */
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#define XDPRX_INTERRUPT_CAUSE_TP1_MASK \
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XDPRX_INTERRUPT_MASK_TP1_MASK /**< Interrupt caused by the
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start of training
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pattern 1. */
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#define XDPRX_INTERRUPT_CAUSE_TP2_MASK \
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XDPRX_INTERRUPT_MASK_TP2_MASK /**< Interrupt caused by the
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start of training
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pattern 2. */
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#define XDPRX_INTERRUPT_CAUSE_TP3_MASK \
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XDPRX_INTERRUPT_MASK_TP3_MASK /**< Interrupt caused by the
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start of training
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pattern 3. */
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/* 0x044: INTERRUPT_MASK_1 */
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#define XDPRX_INTERRUPT_MASK_1_EXT_PKT_STREAM234_MASK(Stream) \
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(0x00001 << ((Stream - 2) * 6)) /**< Mask the interrupt
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assertion for an audio
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extension packet being
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received for stream
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2, 3, or 4. */
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#define XDPRX_INTERRUPT_MASK_1_INFO_PKT_STREAM234_MASK(Stream) \
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(0x00002 << ((Stream - 2) * 6)) /**< Mask the interrupt
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assertion for an audio
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info packet being
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received for stream
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2, 3, or 4. */
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#define XDPRX_INTERRUPT_MASK_1_VM_CHANGE_STREAM234_MASK(Stream) \
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(0x00004 << ((Stream - 2) * 6)) /**< Mask the interrupt
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assertion for a
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resolution change, as
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detected from the MSA
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fields for stream 2, 3,
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or 4. */
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#define XDPRX_INTERRUPT_MASK_1_NO_VIDEO_STREAM234_MASK(Stream) \
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(0x00008 << ((Stream - 2) * 6)) /**< Mask the interrupt
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assertion for the
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no-video condition being
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detected after active
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video received for
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stream 2, 3, or 4. */
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#define XDPRX_INTERRUPT_MASK_1_VBLANK_STREAM234_MASK(Stream) \
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(0x00010 << ((Stream - 2) * 6)) /**< Mask the interrupt
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assertion for the start
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of the blanking interval
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for stream 2, 3, or
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4. */
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#define XDPRX_INTERRUPT_MASK_1_VIDEO_STREAM234_MASK(Stream) \
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(0x00020 << ((Stream - 2) * 6)) /**< Mask the interrupt
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assertion for a valid
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video frame being
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detected on the main
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link for stream 2, 3,
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or 4. */
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/* 0x048: INTERRUPT_CAUSE_1 */
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#define XDPRX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) \
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XDPRX_INTERRUPT_CAUSE_1_EXT_PKT_STREAM234_MASK(Stream) /**< Interrupt
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caused by an audio
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extension packet being
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received for stream 2,
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3, or 4. */
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#define XDPRX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) \
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XDPRX_INTERRUPT_CAUSE_1_INFO_PKT_STREAM234_MASK(Stream) /**< Interrupt
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caused by an audio info
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packet being received
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for stream 2, 3, or
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4. */
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#define XDPRX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) \
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XDPRX_INTERRUPT_CAUSE_1_VM_CHANGE_STREAM234_MASK(Stream) /**< Interrupt
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caused by a resolution
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change, as detected from
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the MSA fields for
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stream 2, 3, or 4. */
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#define XDPRX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) \
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XDPRX_INTERRUPT_CAUSE_1_NO_VIDEO_STREAM234_MASK(Stream) /**< Interrupt
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caused by the no-video
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condition being detected
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after active video
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received for stream 2,
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3, or 4. */
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#define XDPRX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) \
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XDPRX_INTERRUPT_CAUSE_1_VBLANK_STREAM234_MASK(Stream) /**< Interrupt
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caused by the start of
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the blanking interval
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for stream 2, 3, or
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4. */
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#define XDPRX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) \
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XDPRX_INTERRUPT_CAUSE_1_VIDEO_STREAM234_MASK(Stream) /**< Interrupt
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caused by a valid video
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frame being detected on
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the main link for
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stream 2, 3, or 4. */
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/* 0x050: HSYNC_WIDTH */
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#define XDPRX_HSYNC_WIDTH_PULSE_WIDTH_MASK \
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0x00FF /**< Specifies the number of
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clock cycles the
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horizontal sync pulse is
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asserted. */
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#define XDPRX_HSYNC_WIDTH_FRONT_PORCH_MASK \
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0xFF00 /**< Defines the number of video
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clock cycles to place
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between the last pixel
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of active data and the
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start of the horizontal
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sync pulse (the front
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porch). */
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#define XDPRX_HSYNC_WIDTH_FRONT_PORCH_SHIFT 8 /**< Shift bits for the front
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porch. */
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/* 0x090: DEVICE_SERVICE_IRQ */
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#define XDPRX_DEVICE_SERVICE_IRQ_NEW_REMOTE_CMD_MASK \
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0x01 /**< Indicates that a new
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command is present in
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the REMOTE_CMD
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register. */
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#define XDPRX_DEVICE_SERVICE_IRQ_SINK_SPECIFIC_IRQ_MASK \
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0x02 /**< Reflects the
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SINK_SPECIFIC_IRQ
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state. */
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#define XDPRX_DEVICE_SERVICE_IRQ_NEW_DOWN_REPLY_MASK \
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0x10 /**< Indicates a new DOWN_REPLY
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buffer message is
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ready. */
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/* 0x09C: OVER_LINK_BW_SET */
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#define XDPRX_OVER_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */
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#define XDPRX_OVER_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */
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#define XDPRX_OVER_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */
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/* 0x0A0: OVER_LANE_COUNT_SET */
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#define XDPRX_OVER_LANE_COUNT_SET_MASK 0x1F /**< The lane count override
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value. */
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#define XDPRX_OVER_LANE_COUNT_SET_1 0x1 /**< Lane count of 1. */
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#define XDPRX_OVER_LANE_COUNT_SET_2 0x2 /**< Lane count of 2. */
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#define XDPRX_OVER_LANE_COUNT_SET_4 0x4 /**< Lane count of 4. */
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#define XDPRX_OVER_LANE_COUNT_SET_TPS3_SUPPORTED_MASK \
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0x20 /**< Capability override for
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training pattern 3. */
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#define XDPRX_OVER_LANE_COUNT_SET_ENHANCED_FRAME_CAP_MASK \
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0x80 /**< Capability override for
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enhanced framing. */
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/* 0x0A4: OVER_TP_SET */
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#define XDPRX_OVER_TP_SET_TP_SELECT_MASK \
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0x0003 /**< Training pattern select
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override. */
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#define XDPRX_OVER_TP_SET_LQP_SET_MASK \
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0x000C /**< Link quality pattern set
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override. */
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#define XDPRX_OVER_TP_SET_LQP_SET_SHIFT 2 /**< Shift bits for link quality
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pattern set override. */
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#define XDPRX_OVER_TP_SET_REC_CLK_OUT_EN_MASK \
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0x0010 /**< Recovered clock output
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enable override. */
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#define XDPRX_OVER_TP_SET_SCRAMBLER_DISABLE_MASK \
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0x0020 /**< Scrambling disable
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override. */
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#define XDPRX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_MASK \
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0x00C0 /**< Symbol error count
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override. */
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#define XDPRX_OVER_TP_SET_SYMBOL_ERROR_COUNT_SEL_SHIFT \
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6 /**< Shift bits for symbol error
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count override. */
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#define XDPRX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_MASK \
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0xFF00 /**< Training AUX read interval
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override. */
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#define XDPRX_OVER_TP_SET_TRAINING_AUX_RD_INTERVAL_SHIFT \
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8 /**< Shift bits for training AUX
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read interval
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override. */
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/* 0x0A8, 0x0AC, 0x0B0, 0x0B4: OVER_TRAINING_LANEX_SET */
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#define XDPRX_OVER_TRAINING_LANEX_SET_VS_SET_MASK \
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0x03 /**< Voltage swing set
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override. */
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#define XDPRX_OVER_TRAINING_LANEX_SET_MAX_VS_MASK \
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0x04 /**< Maximum voltage swing
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override. */
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#define XDPRX_OVER_TRAINING_LANEX_SET_PE_SET_MASK \
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0x18 /**< Pre-emphasis set
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override. */
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#define XDPRX_OVER_TRAINING_LANEX_SET_PE_SET_SHIFT \
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3 /**< Shift bits for pre-emphasis
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set override. */
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#define XDPRX_OVER_TRAINING_LANEX_SET_MAX_PE_MASK \
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0x20 /**< Maximum pre-emphasis
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override. */
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/* 0x0F8 : VERSION_REGISTER */
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#define XDPRX_VERSION_INTER_REV_MASK \
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0x0000000F /**< Internal revision. */
|
||||
#define XDPRX_VERSION_CORE_PATCH_MASK \
|
||||
0x00000030 /**< Core patch details. */
|
||||
#define XDPRX_VERSION_CORE_PATCH_SHIFT \
|
||||
8 /**< Shift bits for core patch
|
||||
details. */
|
||||
#define XDPRX_VERSION_CORE_VER_REV_MASK \
|
||||
0x000000C0 /**< Core version revision. */
|
||||
#define XDPRX_VERSION_CORE_VER_REV_SHIFT \
|
||||
12 /**< Shift bits for core version
|
||||
revision. */
|
||||
#define XDPRX_VERSION_CORE_VER_MNR_MASK \
|
||||
0x00000F00 /**< Core minor version. */
|
||||
#define XDPRX_VERSION_CORE_VER_MNR_SHIFT \
|
||||
16 /**< Shift bits for core minor
|
||||
version. */
|
||||
#define XDPRX_VERSION_CORE_VER_MJR_MASK \
|
||||
0x0000F000 /**< Core major version. */
|
||||
#define XDPRX_VERSION_CORE_VER_MJR_SHIFT \
|
||||
24 /**< Shift bits for core major
|
||||
version. */
|
||||
/* 0x0FC : CORE_ID */
|
||||
#define XDPRX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */
|
||||
#define XDPRX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */
|
||||
#define XDPRX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */
|
||||
#define XDPRX_CORE_ID_DP_REV_MASK \
|
||||
0x000000F0 /**< DisplayPort protocol
|
||||
revision. */
|
||||
#define XDPRX_CORE_ID_DP_REV_SHIFT \
|
||||
8 /**< Shift bits for DisplayPort
|
||||
protocol revision. */
|
||||
#define XDPRX_CORE_ID_DP_MNR_VER_MASK \
|
||||
0x00000F00 /**< DisplayPort protocol minor
|
||||
version. */
|
||||
#define XDPRX_CORE_ID_DP_MNR_VER_SHIFT \
|
||||
16 /**< Shift bits for DisplayPort
|
||||
protocol major
|
||||
version. */
|
||||
#define XDPRX_CORE_ID_DP_MJR_VER_MASK \
|
||||
0x0000F000 /**< DisplayPort protocol major
|
||||
version. */
|
||||
#define XDPRX_CORE_ID_DP_MJR_VER_SHIFT \
|
||||
24 /**< Shift bits for DisplayPort
|
||||
protocol major
|
||||
version. */
|
||||
/* 0x110: USER_FIFO_OVERFLOW */
|
||||
#define XDPRX_USER_FIFO_OVERFLOW_FLAG_STREAMX_MASK(Stream) \
|
||||
(Stream) /**< Indicates that the internal
|
||||
FIFO has detected on
|
||||
overflow condition for
|
||||
the specified stream. */
|
||||
#define XDPRX_USER_FIFO_OVERFLOW_VID_UNPACK_STREAMX_MASK(Stream) \
|
||||
(Stream << 4) /**< Indicates that the video
|
||||
unpack FIFO has
|
||||
overflown for the
|
||||
specified stream. */
|
||||
#define XDPRX_USER_FIFO_OVERFLOW_VID_TIMING_STREAMX_MASK(Stream) \
|
||||
(Stream << 8) /**< Indicates that the video
|
||||
timing FIFO has
|
||||
overflown for the
|
||||
specified stream. */
|
||||
/* 0x114: USER_VSYNC_STATE */
|
||||
#define XDPRX_USER_VSYNC_STATE_STREAMX_MASK(Stream) \
|
||||
(Stream) /**< The state of the vertical
|
||||
sync pulse for the
|
||||
specified stream. */
|
||||
/* 0x200: PHY_CONFIG */
|
||||
#define XDPRX_PHY_CONFIG_PHY_RESET_ENABLE_MASK \
|
||||
0x00000000 /**< Release reset. */
|
||||
#define XDPRX_PHY_CONFIG_GTPLL_RESET_MASK \
|
||||
0x00000001 /**< Hold the GTPLL in reset. */
|
||||
#define XDPRX_PHY_CONFIG_GTRX_RESET_MASK \
|
||||
0x00000002 /**< Hold GTRXRESET in reset. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_PMA_RESET_MASK \
|
||||
0x00000100 /**< Hold RX_PHY_PMA reset. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_PCS_RESET_MASK \
|
||||
0x00000200 /**< Hold RX_PHY_PCS reset. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_BUF_RESET_MASK \
|
||||
0x00000400 /**< Hold RX_PHY_BUF reset. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_DFE_LPM_RESET_MASK \
|
||||
0x00000800 /**< Hold RX_PHY_DFE_LPM
|
||||
reset. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_MASK \
|
||||
0x00001000 /**< Set RX_PHY_POLARITY. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_LOOPBACK_MASK \
|
||||
0x0000E000 /**< Set RX_PHY_LOOPBACK. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_EYESCANRESET_MASK \
|
||||
0x00010000 /**< Set RX_PHY_EYESCANRESET. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_EYESCANTRIGGER_MASK \
|
||||
0x00020000 /**< Set RX_PHY_
|
||||
EYESCANTRIGGER. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_PRBSCNTRESET_MASK \
|
||||
0x00040000 /**< Set RX_PHY_PRBSCNTRESET. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_RXLPMHFHOLD_MASK \
|
||||
0x00080000 /**< Set RX_PHY_RXLPMHFHOLD. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_RXLPMLFHOLD_MASK \
|
||||
0x00100000 /**< Set RX_PHY_RXLPMLFHOLD. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_RXLPMHFOVERDEN_MASK \
|
||||
0x00200000 /**< Set RX_PHY_
|
||||
RXLPMHFOVERDEN. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_CDRHOLD_MASK \
|
||||
0x00400000 /**< Set RX_PHY_CDRHOLD. */
|
||||
#define XDPRX_PHY_CONFIG_RESET_AT_TRAIN_ITER_MASK \
|
||||
0x00800000 /**< Issue reset at every
|
||||
training iteration. */
|
||||
#define XDPRX_PHY_CONFIG_RESET_AT_LINK_RATE_CHANGE_MASK \
|
||||
0x01000000 /**< Issue reset at every link
|
||||
rate change. */
|
||||
#define XDPRX_PHY_CONFIG_RESET_AT_TP1_START_MASK \
|
||||
0x02000000 /**< Issue reset at start of
|
||||
training pattern 1. */
|
||||
#define XDPRX_PHY_CONFIG_EN_CFG_RX_PHY_POLARITY_MASK \
|
||||
0x04000000 /**< Enable the individual lane
|
||||
polarity. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE0_MASK \
|
||||
0x08000000 /**< Configure RX_PHY_POLARITY
|
||||
for lane 0. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE1_MASK \
|
||||
0x10000000 /**< Configure RX_PHY_POLARITY
|
||||
for lane 1. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE2_MASK \
|
||||
0x20000000 /**< Configure RX_PHY_POLARITY
|
||||
for lane 2. */
|
||||
#define XDPRX_PHY_CONFIG_RX_PHY_POLARITY_LANE3_MASK \
|
||||
0x40000000 /**< Configure RX_PHY_POLARITY
|
||||
for lane 3. */
|
||||
#define XDPRX_PHY_CONFIG_GT_ALL_RESET_MASK \
|
||||
0x00000003 /**< Rest GT and PHY. */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* 0x208: PHY_STATUS */
|
||||
#define XDPRX_PHY_STATUS_RESET_LANE_0_1_DONE_MASK \
|
||||
0x00000003 /**< Reset done for lanes
|
||||
0 and 1. */
|
||||
#define XDPRX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \
|
||||
0x0000000C /**< Reset done for lanes
|
||||
2 and 3. */
|
||||
#define XDPRX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT \
|
||||
2 /**< Shift bits for reset done
|
||||
for lanes 2 and 3. */
|
||||
#define XDPRX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK \
|
||||
0x00000010 /**< PLL locked for lanes
|
||||
0 and 1. */
|
||||
#define XDPRX_PHY_STATUS_PLL_LANE2_3_LOCK_MASK \
|
||||
0x00000020 /**< PLL locked for lanes
|
||||
2 and 3. */
|
||||
#define XDPRX_PHY_STATUS_PLL_FABRIC_LOCK_MASK \
|
||||
0x00000040 /**< FPGA fabric clock PLL
|
||||
locked. */
|
||||
#define XDPRX_PHY_STATUS_RX_CLK_LOCK_MASK \
|
||||
0x00000080 /**< Receiver clock locked. */
|
||||
#define XDPRX_PHY_STATUS_PRBSERR_LANE_0_MASK \
|
||||
0x00000100 /**< PRBS error on lane 0. */
|
||||
#define XDPRX_PHY_STATUS_PRBSERR_LANE_1_MASK \
|
||||
0x00000200 /**< PRBS error on lane 1. */
|
||||
#define XDPRX_PHY_STATUS_PRBSERR_LANE_2_MASK \
|
||||
0x00000400 /**< PRBS error on lane 2. */
|
||||
#define XDPRX_PHY_STATUS_PRBSERR_LANE_3_MASK \
|
||||
0x00000800 /**< PRBS error on lane 3. */
|
||||
#define XDPRX_PHY_STATUS_RX_VLOW_LANE_0_MASK \
|
||||
0x00001000 /**< RX voltage low on lane
|
||||
0. */
|
||||
#define XDPRX_PHY_STATUS_RX_VLOW_LANE_1_MASK \
|
||||
0x00002000 /**< RX voltage low on lane
|
||||
1. */
|
||||
#define XDPRX_PHY_STATUS_RX_VLOW_LANE_2_MASK \
|
||||
0x00004000 /**< RX voltage low on lane
|
||||
2. */
|
||||
#define XDPRX_PHY_STATUS_RX_VLOW_LANE_3_MASK \
|
||||
0x00008000 /**< RX voltage low on lane
|
||||
3. */
|
||||
#define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_0_MASK \
|
||||
0x00010000 /**< Lane aligment status for
|
||||
lane 0. */
|
||||
#define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_1_MASK \
|
||||
0x00020000 /**< Lane aligment status for
|
||||
lane 1. */
|
||||
#define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_2_MASK \
|
||||
0x00040000 /**< Lane aligment status for
|
||||
lane 2. */
|
||||
#define XDPRX_PHY_STATUS_LANE_ALIGN_LANE_3_MASK \
|
||||
0x00080000 /**< Lane aligment status for
|
||||
lane 3. */
|
||||
#define XDPRX_PHY_STATUS_SYM_LOCK_LANE_0_MASK \
|
||||
0x00100000 /**< Symbol lock status for
|
||||
lane 0. */
|
||||
#define XDPRX_PHY_STATUS_SYM_LOCK_LANE_1_MASK \
|
||||
0x00200000 /**< Symbol lock status for
|
||||
lane 1. */
|
||||
#define XDPRX_PHY_STATUS_SYM_LOCK_LANE_2_MASK \
|
||||
0x00400000 /**< Symbol lock status for
|
||||
lane 2. */
|
||||
#define XDPRX_PHY_STATUS_SYM_LOCK_LANE_3_MASK \
|
||||
0x00800000 /**< Symbol lock status for
|
||||
lane 3. */
|
||||
#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_MASK \
|
||||
0x03000000 /**< RX buffer status lane 0. */
|
||||
#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_0_SHIFT \
|
||||
24 /**< Shift bits for RX buffer
|
||||
status lane 0. */
|
||||
#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_1_MASK \
|
||||
0x0C000000 /**< RX buffer status lane 1. */
|
||||
#define XDPRX_PHY_STATUS_RX_BUFFER_STATUE_LANE_1_SHIFT \
|
||||
26 /**< Shift bits for RX buffer
|
||||
status lane 1. */
|
||||
#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_MASK \
|
||||
0x30000000 /**< RX buffer status lane 2. */
|
||||
#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_2_SHIFT \
|
||||
28 /**< Shift bits for RX buffer
|
||||
status lane 2. */
|
||||
#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_MASK \
|
||||
0xC0000000 /**< RX buffer status lane 3. */
|
||||
#define XDPRX_PHY_STATUS_RX_BUFFER_STATUS_LANE_3_SHIFT \
|
||||
30 /**< Shift bits for RX buffer
|
||||
status lane 3. */
|
||||
#define XDPRX_PHY_STATUS_LANES_0_1_READY_MASK \
|
||||
0x00000013 /**< Lanes 0 and 1 are ready. */
|
||||
#define XDPRX_PHY_STATUS_ALL_LANES_READY_MASK \
|
||||
0x0000003F /**< All lanes are ready. */
|
||||
/* 0x210: PHY_POWER_DOWN */
|
||||
#define XDPRX_PHY_POWER_DOWN_LANE_0_MASK 0x1 /**< Power down the PHY for lane
|
||||
0. */
|
||||
#define XDPRX_PHY_POWER_DOWN_LANE_1_MASK 0x2 /**< Power down the PHY for lane
|
||||
1. */
|
||||
#define XDPRX_PHY_POWER_DOWN_LANE_2_MASK 0x4 /**< Power down the PHY for lane
|
||||
2. */
|
||||
#define XDPRX_PHY_POWER_DOWN_LANE_3_MASK 0x8 /**< Power down the PHY for lane
|
||||
3. */
|
||||
/* @} */
|
||||
|
||||
/******************* Macros (Inline Functions) Definitions ********************/
|
||||
|
||||
/** @name Register access macro definitions.
|
||||
|
|
@ -497,98 +1118,4 @@
|
|||
#define XDprx_WriteReg(BaseAddress, RegOffset, Data) \
|
||||
XDprx_Out32((BaseAddress) + (RegOffset), (Data))
|
||||
|
||||
/** @name DPTX core masks, shifts, and register values.
|
||||
* @{
|
||||
*/
|
||||
/* 0x014: INTERRUPT_MASK */
|
||||
#define XDPRX_INTERRUPT_MASK_VIDEO_MODE_CHANGE \
|
||||
0x00001 /**< Mask the interrupt
|
||||
assertion for a
|
||||
resolution change, as
|
||||
detected from the MSA
|
||||
fields. */
|
||||
#define XDPRX_INTERRUPT_MASK_POWER_STATE \
|
||||
0x00002 /**< Mask the interrupt
|
||||
assertion for a power
|
||||
state change. */
|
||||
#define XDPRX_INTERRUPT_MASK_NO_VIDEO 0x00004 /**< Mask the interrupt
|
||||
assertion for the
|
||||
no-video condition being
|
||||
detected after active
|
||||
video received. */
|
||||
#define XDPRX_INTERRUPT_MASK_VERTICAL_BLANKING \
|
||||
0x00008 /**< Mask the interrupt
|
||||
assertion for the start
|
||||
of the blanking
|
||||
interval. */
|
||||
#define XDPRX_INTERRUPT_MASK_TRAINING_LOST \
|
||||
0x00010 /**< Mask the interrupt
|
||||
assertion for training
|
||||
loss on active lanes. */
|
||||
#define XDPRX_INTERRUPT_MASK_VIDEO 0x00040 /**< Mask the interrupt
|
||||
assertion for a valid
|
||||
video frame being
|
||||
detected on the main
|
||||
link. Video interrupt is
|
||||
set after a delay of 8
|
||||
video frames following a
|
||||
valid scrambler reset
|
||||
character. */
|
||||
#define XDPRX_INTERRUPT_MASK_INFO_PKT_RXD \
|
||||
0x00100 /**< Mask the interrupt
|
||||
assertion for an audio
|
||||
info packet being
|
||||
received. */
|
||||
#define XDPRX_INTERRUPT_MASK_EXT_PKT_RXD \
|
||||
0x00200 /**< Mask the interrupt
|
||||
assertion for an audio
|
||||
extension packet being
|
||||
received. */
|
||||
#define XDPRX_INTERRUPT_MASK_VCP_ALLOC 0x00400 /**< Mask the interrupt
|
||||
assertion for a virtual
|
||||
channel payload being
|
||||
allocated. */
|
||||
#define XDPRX_INTERRUPT_MASK_VCP_DEALLOC \
|
||||
0x00800 /**< Mask the interrupt
|
||||
assertion for a virtual
|
||||
channel payload being
|
||||
allocated. */
|
||||
#define XDPRX_INTERRUPT_MASK_DOWN_REPLY 0x01000 /**< Mask the interrupt
|
||||
assertion for a
|
||||
downstream reply being
|
||||
ready. */
|
||||
#define XDPRX_INTERRUPT_MASK_DOWN_REQUEST \
|
||||
0x02000 /**< Mask the interrupt
|
||||
assertion for a
|
||||
downstream request being
|
||||
ready. */
|
||||
#define XDPRX_INTERRUPT_MASK_TRAINING_DONE \
|
||||
0x04000 /**< Mask the interrupt
|
||||
assertion for link
|
||||
training completion. */
|
||||
#define XDPRX_INTERRUPT_MASK_BW_CHANGE 0x08000 /**< Mask the interrupt
|
||||
assertion for a change
|
||||
in bandwidth. */
|
||||
#define XDPRX_INTERRUPT_MASK_TP1 0x10000 /**< Mask the interrupt
|
||||
assertion for start of
|
||||
training pattern 1. */
|
||||
#define XDPRX_INTERRUPT_MASK_TP2 0x20000 /**< Mask the interrupt
|
||||
assertion for start of
|
||||
training pattern 2. */
|
||||
#define XDPRX_INTERRUPT_MASK_TP3 0x40000 /**< Mask the interrupt
|
||||
assertion for start of
|
||||
training pattern 3. */
|
||||
#define XDPRX_INTERRUPT_MASK_ALL 0x7FFFF /**< Mask all interrupts. */
|
||||
|
||||
/* 0x09C: XDPRX_OVER_LINK_BW_SET */
|
||||
#define XDPRX_OVER_LINK_BW_SET_162GBPS 0x06 /**< 1.62 Gbps link rate. */
|
||||
#define XDPRX_OVER_LINK_BW_SET_270GBPS 0x0A /**< 2.70 Gbps link rate. */
|
||||
#define XDPRX_OVER_LINK_BW_SET_540GBPS 0x14 /**< 5.40 Gbps link rate. */
|
||||
|
||||
/* 0x0A0: XDPRX_OVER_LANE_COUNT_SET */
|
||||
#define XDPRX_OVER_LANE_COUNT_SET_1 0x01 /**< Lane count of 1. */
|
||||
#define XDPRX_OVER_LANE_COUNT_SET_2 0x02 /**< Lane count of 2. */
|
||||
#define XDPRX_OVER_LANE_COUNT_SET_4 0x04 /**< Lane count of 4. */
|
||||
/* @} */
|
||||
|
||||
#endif /* XDPRX_HW_H_ */
|
||||
|
|
|
|||
|
|
@ -388,7 +388,7 @@
|
|||
#define XDPTX_TX_MST_CONFIG_VCP_UPDATED_MASK \
|
||||
0x00000002 /**< The VC payload has been
|
||||
updated in the sink. */
|
||||
/* 0x0F8 : VERSION_REGISTER */
|
||||
/* 0x0F8: VERSION */
|
||||
#define XDPTX_VERSION_INTER_REV_MASK \
|
||||
0x0000000F /**< Internal revision. */
|
||||
#define XDPTX_VERSION_CORE_PATCH_MASK \
|
||||
|
|
@ -411,7 +411,7 @@
|
|||
#define XDPTX_VERSION_CORE_VER_MJR_SHIFT \
|
||||
24 /**< Shift bits for core major
|
||||
version. */
|
||||
/* 0x0FC : CORE_ID */
|
||||
/* 0x0FC: CORE_ID */
|
||||
#define XDPTX_CORE_ID_TYPE_MASK 0x0000000F /**< Core type. */
|
||||
#define XDPTX_CORE_ID_TYPE_TX 0x0 /**< Core is a transmitter. */
|
||||
#define XDPTX_CORE_ID_TYPE_RX 0x1 /**< Core is a receiver. */
|
||||
|
|
@ -435,7 +435,7 @@
|
|||
24 /**< Shift bits for DisplayPort
|
||||
protocol major
|
||||
version. */
|
||||
/* 0x100 AUX_CMD */
|
||||
/* 0x100: AUX_CMD */
|
||||
#define XDPTX_AUX_CMD_NBYTES_TRANSFER_MASK \
|
||||
0x0000000F /**< Number of bytes to transfer
|
||||
with the current AUX
|
||||
|
|
@ -465,13 +465,12 @@
|
|||
enable (STOP will be
|
||||
sent after command). */
|
||||
/* 0x10C: AUX_CLK_DIVIDER */
|
||||
#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK \
|
||||
0x0000000F /**< Clock divider value. */
|
||||
#define XDPTX_AUX_CLK_DIVIDER_VAL_MASK 0x00FF /**< Clock divider value. */
|
||||
#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_MASK \
|
||||
0x00000F00 /**< AUX (noise) signal width
|
||||
0xFF00 /**< AUX (noise) signal width
|
||||
filter. */
|
||||
#define XDPTX_AUX_CLK_DIVIDER_AUX_SIG_WIDTH_FILT_SHIFT \
|
||||
8 /**< Shift bits for AUX signal
|
||||
8 /**< Shift bits for AUX signal
|
||||
width filter. */
|
||||
/* 0x130: INTERRUPT_SIG_STATE */
|
||||
#define XDPTX_INTERRUPT_SIG_STATE_HPD_STATE_MASK \
|
||||
|
|
@ -630,7 +629,7 @@
|
|||
#define XDPTX_PHY_CONFIG_TX_PHY_PMA_RESET_MASK \
|
||||
0x0000100 /**< Hold TX_PHY_PMA reset. */
|
||||
#define XDPTX_PHY_CONFIG_TX_PHY_PCS_RESET_MASK \
|
||||
0x0000200 /**< HOLD TX_PHY_PCS reset. */
|
||||
0x0000200 /**< Hold TX_PHY_PCS reset. */
|
||||
#define XDPTX_PHY_CONFIG_TX_PHY_POLARITY_MASK \
|
||||
0x0000400 /**< Set TX_PHY_POLARITY. */
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||||
#define XDPTX_PHY_CONFIG_TX_PHY_PRBSFORCEERR_MASK \
|
||||
|
|
@ -664,6 +663,9 @@
|
|||
#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_MASK \
|
||||
0x0000000C /**< Reset done for lanes
|
||||
2 and 3. */
|
||||
#define XDPTX_PHY_STATUS_RESET_LANE_2_3_DONE_SHIFT \
|
||||
2 /**< Shift bits for reset done
|
||||
for lanes 2 and 3. */
|
||||
#define XDPTX_PHY_STATUS_PLL_LANE0_1_LOCK_MASK \
|
||||
0x00000010 /**< PLL locked for lanes
|
||||
0 and 1. */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue