qspips: Modified the Reset and ResetHw API's.
This patch modifies the configuration register writes in Reset and RestHw API and Mask values. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
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4 changed files with 19 additions and 16 deletions
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@ -93,7 +93,7 @@
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* Added RX threshold reset(1) after transfer in polled and
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* interrupt transfers. Made changes to make sure threshold
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* change is done only when no transfer is in progress.
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* 3.1 hk 06/19/14 When writng configuration register, set/reset
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* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
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* required bits leaving reserved bits untouched. CR# 796813.
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*
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* </pre>
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@ -275,8 +275,10 @@ void XQspiPs_Reset(XQspiPs *InstancePtr)
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*/
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ConfigReg = XQspiPs_ReadReg(InstancePtr->Config.BaseAddress,
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XQSPIPS_CR_OFFSET);
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ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
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ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
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XQspiPs_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPS_CR_OFFSET,
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ConfigReg | XQSPIPS_CR_RESET_STATE);
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ConfigReg);
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}
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/*****************************************************************************/
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@ -263,7 +263,7 @@
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* change is done only when no transfer is in progress.
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* Updated linear init API for parallel and stacked modes.
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* CR#737760.
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* 3.1 hk 06/19/14 When writng configuration register, set/reset
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* 3.1 hk 08/13/14 When writing to the configuration register, set/reset
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* required bits leaving reserved bits untouched. CR# 796813.
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*
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* </pre>
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@ -42,7 +42,7 @@
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* Ver Who Date Changes
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* ----- --- -------- -----------------------------------------------
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* 2.03a hk 09/17/13 First release
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* 3.1 hk 06/19/14 When writng configuration register, set/reset
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* 3.1 hk 06/19/14 When writing to the configuration register, set/reset
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* required bits leaving reserved bits untouched. CR# 796813.
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*
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* </pre>
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@ -140,8 +140,9 @@ void XQspiPs_ResetHw(u32 BaseAddress)
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* Write default value to configuration register
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*/
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ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
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XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
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ConfigReg | XQSPIPS_CR_RESET_STATE);
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ConfigReg |= XQSPIPS_CR_RESET_MASK_SET;
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ConfigReg &= ~XQSPIPS_CR_RESET_MASK_CLR;
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XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
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/*
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* De-select linear mode
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@ -167,6 +168,7 @@ void XQspiPs_LinearInit(u32 BaseAddress)
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{
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u32 BaudRateDiv;
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u32 LinearCfg;
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u32 ConfigReg;
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/*
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* Baud rate divisor for dividing by 4. Value of CR bits [5:3]
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@ -178,10 +180,10 @@ void XQspiPs_LinearInit(u32 BaseAddress)
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* Write configuration register with default values, slave selected &
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* pre-scaler value for divide by 4
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*/
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XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET,
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((XQSPIPS_CR_RESET_STATE |
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XQSPIPS_CR_HOLD_B_MASK | BaudRateDiv) &
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(~XQSPIPS_CR_SSCTRL_MASK) ));
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ConfigReg = XQspiPs_ReadReg(BaseAddress, XQSPIPS_CR_OFFSET);
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ConfigReg |= (XQSPIPS_CR_RESET_MASK_SET | BaudRateDiv);
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ConfigReg &= ~(XQSPIPS_CR_RESET_MASK_CLR | XQSPIPS_CR_SSCTRL_MASK);
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XQspiPs_WriteReg(BaseAddress, XQSPIPS_CR_OFFSET, ConfigReg);
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/*
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* Write linear configuration register with default value -
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@ -55,10 +55,9 @@
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* 2.03a hk 08/22/13 Added prototypes of API's for QSPI reset and
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* linear mode initialization for boot. Added related
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* constant definitions.
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* 3.1 hk 06/19/14 Changed definition of XQSPIPS_CR_RESET_STATE to set/reset
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* 3.1 hk 08/13/14 Changed definition of CR reset value masks to set/reset
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* required bits leaving reserved bits untouched. CR# 796813.
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*
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*
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* </pre>
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*
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******************************************************************************/
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@ -137,19 +136,19 @@ extern "C" {
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#define XQSPIPS_CR_REF_CLK_MASK 0x00000100 /**< Ref clk bit - should be 0 */
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/* Deselect the Slave select line and set the transfer size to 32 at reset */
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#define XQSPIPS_CR_RESET_STATE ((XQSPIPS_CR_IFMODE_MASK | \
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#define XQSPIPS_CR_RESET_MASK_SET XQSPIPS_CR_IFMODE_MASK | \
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XQSPIPS_CR_SSCTRL_MASK | \
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XQSPIPS_CR_DATA_SZ_MASK | \
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XQSPIPS_CR_MSTREN_MASK | \
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XQSPIPS_CR_SSFORCE_MASK | \
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XQSPIPS_CR_HOLD_B_MASK) & \
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(~(XQSPIPS_CR_CPOL_MASK | \
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XQSPIPS_CR_HOLD_B_MASK
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#define XQSPIPS_CR_RESET_MASK_CLR XQSPIPS_CR_CPOL_MASK | \
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XQSPIPS_CR_CPHA_MASK | \
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XQSPIPS_CR_PRESC_MASK | \
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XQSPIPS_CR_MANSTRTEN_MASK | \
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XQSPIPS_CR_MANSTRT_MASK | \
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XQSPIPS_CR_ENDIAN_MASK | \
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XQSPIPS_CR_REF_CLK_MASK)))
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XQSPIPS_CR_REF_CLK_MASK
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/* @} */
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