dp: Clean-up.
Lines should not exceed 80 characters in length. The pre-processor only replaces full names, so prefixes cannot be altered using macros (#define XDPTX_ XDP_TX_). Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
parent
2a662e6f48
commit
e81ba1fde6
5 changed files with 68 additions and 62 deletions
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@ -377,7 +377,8 @@ u32 XDp_TxEstablishLink(XDp *InstancePtr)
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/* Verify arguments. */
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid((LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_162GBPS) ||
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Xil_AssertNonvoid((LinkConfig->LinkRate ==
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XDP_TX_LINK_BW_SET_162GBPS) ||
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(LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_270GBPS) ||
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(LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_270GBPS) ||
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(LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_540GBPS));
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(LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_540GBPS));
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Xil_AssertNonvoid((LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_1) ||
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Xil_AssertNonvoid((LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_1) ||
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@ -401,7 +402,7 @@ u32 XDp_TxEstablishLink(XDp *InstancePtr)
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/* Turn off the training pattern and enable scrambler. */
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/* Turn off the training pattern and enable scrambler. */
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Status2 = XDp_TxSetTrainingPattern(InstancePtr,
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Status2 = XDp_TxSetTrainingPattern(InstancePtr,
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XDP_TX_TRAINING_PATTERN_SET_OFF);
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XDP_TX_TRAINING_PATTERN_SET_OFF);
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if ((Status != XST_SUCCESS) || (Status2 != XST_SUCCESS)) {
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if ((Status != XST_SUCCESS) || (Status2 != XST_SUCCESS)) {
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return XST_FAILURE;
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return XST_FAILURE;
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}
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}
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@ -438,8 +439,8 @@ u32 XDp_TxCheckLinkStatus(XDp *InstancePtr, u8 LaneCount)
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid((LaneCount == XDP_TX_LANE_COUNT_SET_1) ||
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Xil_AssertNonvoid((LaneCount == XDP_TX_LANE_COUNT_SET_1) ||
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(LaneCount == XDP_TX_LANE_COUNT_SET_2) ||
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(LaneCount == XDP_TX_LANE_COUNT_SET_2) ||
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(LaneCount == XDP_TX_LANE_COUNT_SET_4));
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(LaneCount == XDP_TX_LANE_COUNT_SET_4));
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if (!XDp_TxIsConnected(InstancePtr)) {
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if (!XDp_TxIsConnected(InstancePtr)) {
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return XST_DEVICE_NOT_FOUND;
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return XST_DEVICE_NOT_FOUND;
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@ -1039,8 +1040,8 @@ u32 XDp_TxSetLaneCount(XDp *InstancePtr, u8 LaneCount)
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
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Xil_AssertNonvoid((LaneCount == XDP_TX_LANE_COUNT_SET_1) ||
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Xil_AssertNonvoid((LaneCount == XDP_TX_LANE_COUNT_SET_1) ||
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(LaneCount == XDP_TX_LANE_COUNT_SET_2) ||
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(LaneCount == XDP_TX_LANE_COUNT_SET_2) ||
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(LaneCount == XDP_TX_LANE_COUNT_SET_4));
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(LaneCount == XDP_TX_LANE_COUNT_SET_4));
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if (!XDp_TxIsConnected(InstancePtr)) {
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if (!XDp_TxIsConnected(InstancePtr)) {
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return XST_DEVICE_NOT_FOUND;
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return XST_DEVICE_NOT_FOUND;
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@ -1110,15 +1111,15 @@ u32 XDp_TxSetLinkRate(XDp *InstancePtr, u8 LinkRate)
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switch (LinkRate) {
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switch (LinkRate) {
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case XDP_TX_LINK_BW_SET_162GBPS:
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case XDP_TX_LINK_BW_SET_162GBPS:
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Status = XDp_TxSetClkSpeed(InstancePtr,
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Status = XDp_TxSetClkSpeed(InstancePtr,
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XDP_TX_PHY_CLOCK_SELECT_162GBPS);
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XDP_TX_PHY_CLOCK_SELECT_162GBPS);
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break;
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break;
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case XDP_TX_LINK_BW_SET_270GBPS:
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case XDP_TX_LINK_BW_SET_270GBPS:
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Status = XDp_TxSetClkSpeed(InstancePtr,
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Status = XDp_TxSetClkSpeed(InstancePtr,
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XDP_TX_PHY_CLOCK_SELECT_270GBPS);
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XDP_TX_PHY_CLOCK_SELECT_270GBPS);
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break;
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break;
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case XDP_TX_LINK_BW_SET_540GBPS:
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case XDP_TX_LINK_BW_SET_540GBPS:
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Status = XDp_TxSetClkSpeed(InstancePtr,
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Status = XDp_TxSetClkSpeed(InstancePtr,
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XDP_TX_PHY_CLOCK_SELECT_540GBPS);
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XDP_TX_PHY_CLOCK_SELECT_540GBPS);
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break;
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break;
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default:
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default:
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break;
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break;
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@ -1269,7 +1270,7 @@ void XDp_TxResetPhy(XDp *InstancePtr, u32 Reset)
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, Reset);
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG, Reset);
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG,
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_TX_PHY_CONFIG,
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XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
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XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
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if (InstancePtr->Config.MaxLaneCount > 2) {
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if (InstancePtr->Config.MaxLaneCount > 2) {
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XDp_WaitPhyReady(InstancePtr,
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XDp_WaitPhyReady(InstancePtr,
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XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK);
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XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK);
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@ -1665,15 +1666,15 @@ static u32 XDp_TxInitialize(XDp *InstancePtr)
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switch (ConfigPtr->MaxLinkRate) {
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switch (ConfigPtr->MaxLinkRate) {
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case XDP_TX_LINK_BW_SET_540GBPS:
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case XDP_TX_LINK_BW_SET_540GBPS:
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XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT,
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XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT,
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XDP_TX_PHY_CLOCK_SELECT_540GBPS);
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XDP_TX_PHY_CLOCK_SELECT_540GBPS);
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break;
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break;
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case XDP_TX_LINK_BW_SET_270GBPS:
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case XDP_TX_LINK_BW_SET_270GBPS:
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XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT,
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XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT,
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XDP_TX_PHY_CLOCK_SELECT_270GBPS);
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XDP_TX_PHY_CLOCK_SELECT_270GBPS);
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break;
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break;
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case XDP_TX_LINK_BW_SET_162GBPS:
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case XDP_TX_LINK_BW_SET_162GBPS:
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XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT,
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XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CLOCK_SELECT,
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XDP_TX_PHY_CLOCK_SELECT_162GBPS);
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XDP_TX_PHY_CLOCK_SELECT_162GBPS);
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break;
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break;
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default:
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default:
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break;
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break;
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@ -1681,16 +1682,16 @@ static u32 XDp_TxInitialize(XDp *InstancePtr)
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/* Bring the PHY (and GTTXRESET) out of reset. */
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/* Bring the PHY (and GTTXRESET) out of reset. */
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XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CONFIG,
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XDp_WriteReg(ConfigPtr->BaseAddr, XDP_TX_PHY_CONFIG,
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XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
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XDP_TX_PHY_CONFIG_PHY_RESET_ENABLE_MASK);
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/* Wait for the PHY to be ready. */
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/* Wait for the PHY to be ready. */
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if (ConfigPtr->MaxLaneCount > 2) {
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if (ConfigPtr->MaxLaneCount > 2) {
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Status = XDp_WaitPhyReady(InstancePtr,
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Status = XDp_WaitPhyReady(InstancePtr,
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XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK);
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XDP_TX_PHY_STATUS_ALL_LANES_READY_MASK);
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}
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}
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else {
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else {
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Status = XDp_WaitPhyReady(InstancePtr,
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Status = XDp_WaitPhyReady(InstancePtr,
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XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK);
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XDP_TX_PHY_STATUS_LANES_0_1_READY_MASK);
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}
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}
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if (Status != XST_SUCCESS) {
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if (Status != XST_SUCCESS) {
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return XST_FAILURE;
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return XST_FAILURE;
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@ -1782,7 +1783,7 @@ static u32 XDp_RxInitialize(XDp *InstancePtr)
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InstancePtr->RxInstance.LinkConfig.LaneCount);
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InstancePtr->RxInstance.LinkConfig.LaneCount);
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/* Set the interrupt masks. */
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/* Set the interrupt masks. */
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK,
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XDp_WriteReg(InstancePtr->Config.BaseAddr, XDP_RX_INTERRUPT_MASK,
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~XDP_RX_INTERRUPT_MASK_ALL_MASK);
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~XDP_RX_INTERRUPT_MASK_ALL_MASK);
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/* Enable the display timing generator. */
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/* Enable the display timing generator. */
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XDp_RxDtgEn(InstancePtr);
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XDp_RxDtgEn(InstancePtr);
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@ -1915,7 +1916,7 @@ static XDp_TxTrainingState XDp_TxTrainingStateClockRecovery(XDp *InstancePtr)
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InstancePtr->TxInstance.LinkConfig.VsLevel = 0;
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InstancePtr->TxInstance.LinkConfig.VsLevel = 0;
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InstancePtr->TxInstance.LinkConfig.PeLevel = 0;
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InstancePtr->TxInstance.LinkConfig.PeLevel = 0;
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Status = XDp_TxSetTrainingPattern(InstancePtr,
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Status = XDp_TxSetTrainingPattern(InstancePtr,
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XDP_TX_TRAINING_PATTERN_SET_TP1);
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XDP_TX_TRAINING_PATTERN_SET_TP1);
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if (Status != XST_SUCCESS) {
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if (Status != XST_SUCCESS) {
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return XDP_TX_TS_FAILURE;
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return XDP_TX_TS_FAILURE;
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}
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}
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@ -2022,11 +2023,11 @@ static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization(
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DpcdRxCapsField[XDP_DPCD_MAX_LANE_COUNT] &
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DpcdRxCapsField[XDP_DPCD_MAX_LANE_COUNT] &
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XDP_DPCD_TPS3_SUPPORT_MASK) {
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XDP_DPCD_TPS3_SUPPORT_MASK) {
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Status = XDp_TxSetTrainingPattern(InstancePtr,
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Status = XDp_TxSetTrainingPattern(InstancePtr,
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XDP_TX_TRAINING_PATTERN_SET_TP3);
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XDP_TX_TRAINING_PATTERN_SET_TP3);
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}
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}
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else {
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else {
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Status = XDp_TxSetTrainingPattern(InstancePtr,
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Status = XDp_TxSetTrainingPattern(InstancePtr,
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XDP_TX_TRAINING_PATTERN_SET_TP2);
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XDP_TX_TRAINING_PATTERN_SET_TP2);
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}
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}
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if (Status != XST_SUCCESS) {
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if (Status != XST_SUCCESS) {
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return XDP_TX_TS_FAILURE;
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return XDP_TX_TS_FAILURE;
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@ -2084,8 +2085,8 @@ static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization(
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* @param InstancePtr is a pointer to the XDp instance.
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* @param InstancePtr is a pointer to the XDp instance.
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*
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*
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* @return The next training state:
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* @return The next training state:
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* - XDP_TX_TS_ADJUST_LANE_COUNT if the minimal data rate is already
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* - XDP_TX_TS_ADJUST_LANE_COUNT if the minimal data rate is
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* in use. Re-attempt training at a reduced lane count.
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* already in use. Re-attempt training at a reduced lane count.
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* - XDP_TX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
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* - XDP_TX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
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*
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*
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* @note None.
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* @note None.
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@ -2153,7 +2154,7 @@ static XDp_TxTrainingState XDp_TxTrainingStateAdjustLaneCount(XDp *InstancePtr)
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switch (LinkConfig->LaneCount) {
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switch (LinkConfig->LaneCount) {
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case XDP_TX_LANE_COUNT_SET_4:
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case XDP_TX_LANE_COUNT_SET_4:
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Status = XDp_TxSetLaneCount(InstancePtr,
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Status = XDp_TxSetLaneCount(InstancePtr,
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XDP_TX_LANE_COUNT_SET_2);
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XDP_TX_LANE_COUNT_SET_2);
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if (Status != XST_SUCCESS) {
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if (Status != XST_SUCCESS) {
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Status = XDP_TX_TS_FAILURE;
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Status = XDP_TX_TS_FAILURE;
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break;
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break;
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@ -2169,7 +2170,7 @@ static XDp_TxTrainingState XDp_TxTrainingStateAdjustLaneCount(XDp *InstancePtr)
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break;
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break;
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case XDP_TX_LANE_COUNT_SET_2:
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case XDP_TX_LANE_COUNT_SET_2:
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Status = XDp_TxSetLaneCount(InstancePtr,
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Status = XDp_TxSetLaneCount(InstancePtr,
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XDP_TX_LANE_COUNT_SET_1);
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XDP_TX_LANE_COUNT_SET_1);
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if (Status != XST_SUCCESS) {
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if (Status != XST_SUCCESS) {
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Status = XDP_TX_TS_FAILURE;
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Status = XDP_TX_TS_FAILURE;
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break;
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break;
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@ -2901,7 +2902,7 @@ static u32 XDp_TxAuxWaitReply(XDp *InstancePtr)
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while (0 < Timeout) {
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while (0 < Timeout) {
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Status = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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Status = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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XDP_TX_INTERRUPT_STATUS);
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XDP_TX_INTERRUPT_STATUS);
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/* Check for a timeout. */
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/* Check for a timeout. */
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if (Status & XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK) {
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if (Status & XDP_TX_INTERRUPT_STATUS_REPLY_TIMEOUT_MASK) {
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@ -867,8 +867,7 @@ u32 XDp_TxMstDisable(XDp *InstancePtr);
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void XDp_TxMstCfgStreamEnable(XDp *InstancePtr, u8 Stream);
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void XDp_TxMstCfgStreamEnable(XDp *InstancePtr, u8 Stream);
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void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream);
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void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream);
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u8 XDp_TxMstStreamIsEnabled(XDp *InstancePtr, u8 Stream);
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u8 XDp_TxMstStreamIsEnabled(XDp *InstancePtr, u8 Stream);
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void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8
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void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8 SinkNum);
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SinkNum);
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void XDp_TxSetStreamSinkRad(XDp *InstancePtr, u8 Stream, u8 LinkCountTotal,
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void XDp_TxSetStreamSinkRad(XDp *InstancePtr, u8 Stream, u8 LinkCountTotal,
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u8 *RelativeAddress);
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u8 *RelativeAddress);
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@ -992,14 +991,9 @@ void XDp_RxSetUserPixelWidth(XDp *InstancePtr, u8 UserPixelWidth);
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#define XDptx_HpdInterruptHandler XDp_InterruptHandler
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#define XDptx_HpdInterruptHandler XDp_InterruptHandler
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#define XDprx_InterruptHandler XDp_InterruptHandler
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#define XDprx_InterruptHandler XDp_InterruptHandler
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#define XDptx_ XDp_Tx
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#define XDptx XDp_Tx
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#define XDprx_ XDp_Rx
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#define XDprx XDp_Rx
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#define XDptx XDp
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#define XDprx XDp
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#define XDPTX_DPCD_ XDP_DPCD_
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#define XDPTX_ XDP_TX_
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#define XDPRX_ XDP_RX_
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#define XDPTX XDP_TX
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#define XDPTX XDP_TX
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#define XDPRX XDP_RX
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#define XDPRX XDP_RX
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@ -546,11 +546,11 @@ static void XDp_TxInterruptHandler(XDp *InstancePtr)
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/* Determine what kind of interrupt occurred.
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/* Determine what kind of interrupt occurred.
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* Note: XDP_TX_INTERRUPT_STATUS is an RC (read-clear) register. */
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* Note: XDP_TX_INTERRUPT_STATUS is an RC (read-clear) register. */
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IntrStatus = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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IntrStatus = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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XDP_TX_INTERRUPT_STATUS);
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XDP_TX_INTERRUPT_STATUS);
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IntrStatus &= ~XDp_ReadReg(InstancePtr->Config.BaseAddr,
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IntrStatus &= ~XDp_ReadReg(InstancePtr->Config.BaseAddr,
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XDP_TX_INTERRUPT_MASK);
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XDP_TX_INTERRUPT_MASK);
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IntrMask = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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IntrMask = XDp_ReadReg(InstancePtr->Config.BaseAddr,
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XDP_TX_INTERRUPT_MASK);
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XDP_TX_INTERRUPT_MASK);
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HpdEventDetected = IntrStatus & XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK;
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HpdEventDetected = IntrStatus & XDP_TX_INTERRUPT_STATUS_HPD_EVENT_MASK;
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HpdPulseDetected = IntrStatus &
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HpdPulseDetected = IntrStatus &
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@ -414,8 +414,9 @@ u8 XDp_TxMstStreamIsEnabled(XDp *InstancePtr, u8 Stream)
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/* Verify arguments. */
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/* Verify arguments. */
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid(InstancePtr != NULL);
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Xil_AssertNonvoid((Stream == XDP_TX_STREAM_ID1) ||
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Xil_AssertNonvoid((Stream == XDP_TX_STREAM_ID1) ||
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(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
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(Stream == XDP_TX_STREAM_ID2) ||
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(Stream == XDP_TX_STREAM_ID4));
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(Stream == XDP_TX_STREAM_ID3) ||
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(Stream == XDP_TX_STREAM_ID4));
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return InstancePtr->TxInstance.
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return InstancePtr->TxInstance.
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MstStreamConfig[Stream - 1].MstStreamEnable;
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MstStreamConfig[Stream - 1].MstStreamEnable;
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@ -439,8 +440,9 @@ void XDp_TxMstCfgStreamEnable(XDp *InstancePtr, u8 Stream)
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/* Verify arguments. */
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/* Verify arguments. */
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid(InstancePtr != NULL);
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Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
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Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
|
|
||||||
InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstStreamEnable = 1;
|
InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstStreamEnable = 1;
|
||||||
}
|
}
|
||||||
|
@ -463,8 +465,9 @@ void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream)
|
||||||
/* Verify arguments. */
|
/* Verify arguments. */
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
|
|
||||||
InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstStreamEnable = 0;
|
InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstStreamEnable = 0;
|
||||||
}
|
}
|
||||||
|
@ -488,8 +491,7 @@ void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream)
|
||||||
* function using the XDp_TxFindAccessibleDpDevices.
|
* function using the XDp_TxFindAccessibleDpDevices.
|
||||||
*
|
*
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8
|
void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8 SinkNum)
|
||||||
SinkNum)
|
|
||||||
{
|
{
|
||||||
u8 Index;
|
u8 Index;
|
||||||
XDp_TxMstStream *MstStream;
|
XDp_TxMstStream *MstStream;
|
||||||
|
@ -498,8 +500,9 @@ void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8
|
||||||
/* Verify arguments. */
|
/* Verify arguments. */
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
|
|
||||||
MstStream = &InstancePtr->TxInstance.MstStreamConfig[Stream - 1];
|
MstStream = &InstancePtr->TxInstance.MstStreamConfig[Stream - 1];
|
||||||
Topology = &InstancePtr->TxInstance.Topology;
|
Topology = &InstancePtr->TxInstance.Topology;
|
||||||
|
@ -539,8 +542,9 @@ void XDp_TxSetStreamSinkRad(XDp *InstancePtr, u8 Stream, u8 LinkCountTotal,
|
||||||
/* Verify arguments. */
|
/* Verify arguments. */
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
Xil_AssertVoid(LinkCountTotal > 0);
|
Xil_AssertVoid(LinkCountTotal > 0);
|
||||||
Xil_AssertVoid(RelativeAddress != NULL);
|
Xil_AssertVoid(RelativeAddress != NULL);
|
||||||
|
|
||||||
|
@ -1639,7 +1643,8 @@ u32 XDp_TxSendSbMsgRemoteIicWrite(XDp *InstancePtr, u8 LinkCountTotal,
|
||||||
|
|
||||||
/* Prepare the sideband message body. */
|
/* Prepare the sideband message body. */
|
||||||
Msg.Body.MsgData[0] = XDP_TX_SBMSG_REMOTE_I2C_WRITE;
|
Msg.Body.MsgData[0] = XDP_TX_SBMSG_REMOTE_I2C_WRITE;
|
||||||
Msg.Body.MsgData[1] = RelativeAddress[Msg.Header.LinkCountTotal - 1] << 4;
|
Msg.Body.MsgData[1] = RelativeAddress[Msg.Header.LinkCountTotal - 1] <<
|
||||||
|
4;
|
||||||
Msg.Body.MsgData[2] = IicDeviceId; /* Write I2C device ID. */
|
Msg.Body.MsgData[2] = IicDeviceId; /* Write I2C device ID. */
|
||||||
Msg.Body.MsgData[3] = BytesToWrite; /* Number of bytes to write. */
|
Msg.Body.MsgData[3] = BytesToWrite; /* Number of bytes to write. */
|
||||||
for (Index = 0; Index < BytesToWrite; Index++) {
|
for (Index = 0; Index < BytesToWrite; Index++) {
|
||||||
|
|
|
@ -349,8 +349,9 @@ void XDp_TxCfgMsaUseEdidPreferredTiming(XDp *InstancePtr, u8 Stream, u8 *Edid)
|
||||||
/* Verify arguments. */
|
/* Verify arguments. */
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
Xil_AssertVoid(Edid != NULL);
|
Xil_AssertVoid(Edid != NULL);
|
||||||
|
|
||||||
MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1];
|
MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1];
|
||||||
|
@ -484,8 +485,9 @@ void XDp_TxCfgMsaUseCustom(XDp *InstancePtr, u8 Stream,
|
||||||
/* Verify arguments. */
|
/* Verify arguments. */
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
Xil_AssertVoid(MsaConfigCustom != NULL);
|
Xil_AssertVoid(MsaConfigCustom != NULL);
|
||||||
|
|
||||||
MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1];
|
MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1];
|
||||||
|
@ -566,8 +568,9 @@ void XDp_TxCfgMsaSetBpc(XDp *InstancePtr, u8 Stream, u8 BitsPerColor)
|
||||||
/* Verify arguments. */
|
/* Verify arguments. */
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
|
Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
|
||||||
(BitsPerColor == 10) || (BitsPerColor == 12) ||
|
(BitsPerColor == 10) || (BitsPerColor == 12) ||
|
||||||
(BitsPerColor == 16));
|
(BitsPerColor == 16));
|
||||||
|
@ -640,8 +643,9 @@ void XDp_TxSetVideoMode(XDp *InstancePtr, u8 Stream)
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
|
|
||||||
XDp_TxClearMsaValues(InstancePtr, Stream);
|
XDp_TxClearMsaValues(InstancePtr, Stream);
|
||||||
XDp_TxSetMsaValues(InstancePtr, Stream);
|
XDp_TxSetMsaValues(InstancePtr, Stream);
|
||||||
|
@ -671,8 +675,9 @@ void XDp_TxClearMsaValues(XDp *InstancePtr, u8 Stream)
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
|
|
||||||
Config = &InstancePtr->Config;
|
Config = &InstancePtr->Config;
|
||||||
|
|
||||||
|
@ -744,8 +749,9 @@ void XDp_TxSetMsaValues(XDp *InstancePtr, u8 Stream)
|
||||||
Xil_AssertVoid(InstancePtr != NULL);
|
Xil_AssertVoid(InstancePtr != NULL);
|
||||||
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
|
||||||
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
|
||||||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
|
(Stream == XDP_TX_STREAM_ID2) ||
|
||||||
(Stream == XDP_TX_STREAM_ID4));
|
(Stream == XDP_TX_STREAM_ID3) ||
|
||||||
|
(Stream == XDP_TX_STREAM_ID4));
|
||||||
|
|
||||||
ConfigPtr = &InstancePtr->Config;
|
ConfigPtr = &InstancePtr->Config;
|
||||||
MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1];
|
MsaConfig = &InstancePtr->TxInstance.MsaConfig[Stream - 1];
|
||||||
|
|
Loading…
Add table
Reference in a new issue