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dp: Clean-up.

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Lines should not exceed 80 characters in length.
The pre-processor only replaces full names, so prefixes cannot be altered using
macros (#define XDPTX_ XDP_TX_).

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
This commit is contained in:
Andrei-Liviu Simion 2015-01-25 21:54:43 -08:00 • committed by Nava kishore Manne
parent 2a662e6f48
commit e81ba1fde6
5 changed files with 68 additions and 62 deletions
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7
XilinxProcessorIPLib/drivers/dp/src/xdp.c
View file

@ -377,7 +377,8 @@ u32 XDp_TxEstablishLink(XDp *InstancePtr)
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid((LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_162GBPS) ||
Xil_AssertNonvoid((LinkConfig->LinkRate ==
XDP_TX_LINK_BW_SET_162GBPS) ||
(LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_270GBPS) ||
(LinkConfig->LinkRate == XDP_TX_LINK_BW_SET_540GBPS));
Xil_AssertNonvoid((LinkConfig->LaneCount == XDP_TX_LANE_COUNT_SET_1) ||
@ -2084,8 +2085,8 @@ static XDp_TxTrainingState XDp_TxTrainingStateChannelEqualization(
* @param InstancePtr is a pointer to the XDp instance.
*
* @return The next training state:
* - XDP_TX_TS_ADJUST_LANE_COUNT if the minimal data rate is already
* in use. Re-attempt training at a reduced lane count.
* - XDP_TX_TS_ADJUST_LANE_COUNT if the minimal data rate is
* already in use. Re-attempt training at a reduced lane count.
* - XDP_TX_TS_CLOCK_RECOVERY otherwise. Re-attempt training.
*
* @note None.

12
XilinxProcessorIPLib/drivers/dp/src/xdp.h
View file

@ -867,8 +867,7 @@ u32 XDp_TxMstDisable(XDp *InstancePtr);
void XDp_TxMstCfgStreamEnable(XDp *InstancePtr, u8 Stream);
void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream);
u8 XDp_TxMstStreamIsEnabled(XDp *InstancePtr, u8 Stream);
void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8
SinkNum);
void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8 SinkNum);
void XDp_TxSetStreamSinkRad(XDp *InstancePtr, u8 Stream, u8 LinkCountTotal,
u8 *RelativeAddress);
@ -992,14 +991,9 @@ void XDp_RxSetUserPixelWidth(XDp *InstancePtr, u8 UserPixelWidth);
#define XDptx_HpdInterruptHandler XDp_InterruptHandler
#define XDprx_InterruptHandler XDp_InterruptHandler
#define XDptx_ XDp_Tx
#define XDprx_ XDp_Rx
#define XDptx XDp
#define XDprx XDp
#define XDptx XDp_Tx
#define XDprx XDp_Rx
#define XDPTX_DPCD_ XDP_DPCD_
#define XDPTX_ XDP_TX_
#define XDPRX_ XDP_RX_
#define XDPTX XDP_TX
#define XDPRX XDP_RX

21
XilinxProcessorIPLib/drivers/dp/src/xdp_mst.c
View file

@ -414,7 +414,8 @@ u8 XDp_TxMstStreamIsEnabled(XDp *InstancePtr, u8 Stream)
/* Verify arguments. */
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
return InstancePtr->TxInstance.
@ -439,7 +440,8 @@ void XDp_TxMstCfgStreamEnable(XDp *InstancePtr, u8 Stream)
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstStreamEnable = 1;
@ -463,7 +465,8 @@ void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream)
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
InstancePtr->TxInstance.MstStreamConfig[Stream - 1].MstStreamEnable = 0;
@ -488,8 +491,7 @@ void XDp_TxMstCfgStreamDisable(XDp *InstancePtr, u8 Stream)
* function using the XDp_TxFindAccessibleDpDevices.
*
*******************************************************************************/
void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8
SinkNum)
void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8 SinkNum)
{
u8 Index;
XDp_TxMstStream *MstStream;
@ -498,7 +500,8 @@ void XDp_TxSetStreamSelectFromSinkList(XDp *InstancePtr, u8 Stream, u8
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
MstStream = &InstancePtr->TxInstance.MstStreamConfig[Stream - 1];
@ -539,7 +542,8 @@ void XDp_TxSetStreamSinkRad(XDp *InstancePtr, u8 Stream, u8 LinkCountTotal,
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
Xil_AssertVoid(LinkCountTotal > 0);
Xil_AssertVoid(RelativeAddress != NULL);
@ -1639,7 +1643,8 @@ u32 XDp_TxSendSbMsgRemoteIicWrite(XDp *InstancePtr, u8 LinkCountTotal,
/* Prepare the sideband message body. */
Msg.Body.MsgData[0] = XDP_TX_SBMSG_REMOTE_I2C_WRITE;
Msg.Body.MsgData[1] = RelativeAddress[Msg.Header.LinkCountTotal - 1] << 4;
Msg.Body.MsgData[1] = RelativeAddress[Msg.Header.LinkCountTotal - 1] <<
4;
Msg.Body.MsgData[2] = IicDeviceId; /* Write I2C device ID. */
Msg.Body.MsgData[3] = BytesToWrite; /* Number of bytes to write. */
for (Index = 0; Index < BytesToWrite; Index++) {

18
XilinxProcessorIPLib/drivers/dp/src/xdp_spm.c
View file

@ -349,7 +349,8 @@ void XDp_TxCfgMsaUseEdidPreferredTiming(XDp *InstancePtr, u8 Stream, u8 *Edid)
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
Xil_AssertVoid(Edid != NULL);
@ -484,7 +485,8 @@ void XDp_TxCfgMsaUseCustom(XDp *InstancePtr, u8 Stream,
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
Xil_AssertVoid(MsaConfigCustom != NULL);
@ -566,7 +568,8 @@ void XDp_TxCfgMsaSetBpc(XDp *InstancePtr, u8 Stream, u8 BitsPerColor)
/* Verify arguments. */
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
Xil_AssertVoid((BitsPerColor == 6) || (BitsPerColor == 8) ||
(BitsPerColor == 10) || (BitsPerColor == 12) ||
@ -640,7 +643,8 @@ void XDp_TxSetVideoMode(XDp *InstancePtr, u8 Stream)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
XDp_TxClearMsaValues(InstancePtr, Stream);
@ -671,7 +675,8 @@ void XDp_TxClearMsaValues(XDp *InstancePtr, u8 Stream)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
Config = &InstancePtr->Config;
@ -744,7 +749,8 @@ void XDp_TxSetMsaValues(XDp *InstancePtr, u8 Stream)
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid((Stream == XDP_TX_STREAM_ID1) ||
(Stream == XDP_TX_STREAM_ID2) || (Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID2) ||
(Stream == XDP_TX_STREAM_ID3) ||
(Stream == XDP_TX_STREAM_ID4));
ConfigPtr = &InstancePtr->Config;