nandpsu: Remove QEMU specific workarounds

Now the QEMU nand model supports extended parameter page
information. So, removing the QEMU specific hacks from the
driver.

Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Acked-by: Sai Pavan Boddu <saipava@xilinx.com>
This commit is contained in:
Punnaiah Choudary Kalluri 2015-08-18 15:17:51 +05:30 committed by Nava kishore Manne
parent 8eaf69e7fc
commit ee8bf3f411

View file

@ -138,7 +138,6 @@ const static XNandPsu_EccMatrix EccMatrix[] = {
};
/**************************** Type Definitions *******************************/
static u8 isQemuPlatform = 0U;
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Function Prototypes ******************************/
@ -241,17 +240,6 @@ s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
InstancePtr->DmaMode = XNANDPSU_MDMA;
InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
/*
* Temporary hack for disabling the ecc on qemu as currently there
* is no support in the utility for writing images with ecc enabled.
*/
#define CSU_VER_REG 0xFFCA0044U
#define CSU_VER_PLATFORM_MASK 0xF000U
#define CSU_VER_PLATFORM_QEMU_VAL 0x3000U
if ((*(u32 *)CSU_VER_REG & CSU_VER_PLATFORM_MASK) ==
CSU_VER_PLATFORM_QEMU_VAL) {
isQemuPlatform = 1U;
}
/* Initialize the NAND flash targets */
Status = XNandPsu_FlashInit(InstancePtr);
if (Status != XST_SUCCESS) {
@ -269,11 +257,6 @@ s32 XNandPsu_CfgInitialize(XNandPsu *InstancePtr, XNandPsu_Config *ConfigPtr,
InstancePtr->EccMode = XNANDPSU_HWECC;
}
if (isQemuPlatform != 0U) {
InstancePtr->EccMode = XNANDPSU_NONE;
goto Out;
}
/* Initialize Ecc Error flip counters */
InstancePtr->Ecc_Stat_PerPage_flips = 0U;
InstancePtr->Ecc_Stats_total_flips = 0U;
@ -402,10 +385,7 @@ static s32 XNandPsu_FlashInit(XNandPsu *InstancePtr)
InstancePtr->Features.OnDie = 0U;
}
}
if (isQemuPlatform != 0U) {
InstancePtr->Geometry.NumTargets++;
break;
}
if ((InstancePtr->Geometry.NumBitsECC == 0xFFU) &&
(InstancePtr->Features.ExtPrmPage != 0U)) {
/* ONFI 3.1 section 5.7.1.6 & 5.7.1.7 */