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dp: rx: Added interrupt registers.

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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
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Andrei-Liviu Simion 2015-01-15 11:05:21 -08:00 • committed by Nava kishore Manne
parent 252735630d
commit fe56ba6ef0
1 changed files with 22 additions and 0 deletions
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22
XilinxProcessorIPLib/drivers/dp/src/xdprx_hw.h
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@ -106,6 +106,28 @@
recent AUX request. */
/* @} */
/** @name DPRX core registers: Interrupt registers.
* @{
*/
#define XDPRX_INTERRUPT_CAUSE 0x040 /**< Indicates the cause of
pending host interrupts
for stream 1, training,
payload allocation, and
for the AUX channel. */
#define XDPRX_INTERRUPT_MASK_1 0x044 /**< Masks the specified
interrupt sources. */
#define XDPRX_INTERRUPT_CAUSE_1 0x048 /**< Indicates the cause of a
pending host interrupts
for streams 2, 3, 4. */
#define XDPRX_HSYNC_WIDTH 0x050 /**< Controls the timing of the
active-high horizontal
sync pulse generated
by the display timing
generator (DTG). */
#define XDPRX_FAST_I2C_DIVIDER 0x060 /**< Fast I2C mode clock divider
value. */
/* @} */
/******************* Macros (Inline Functions) Definitions ********************/
/** @name Register access macro definitions.