Commit graph

10 commits

Author SHA1 Message Date
VNSL Durga
158f2cec4f xilskey: Modified example of efuseps
As RSA enable and PPK revoke bits are having each 2 bits
in secure control register XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits
API also returns status of 2 bits so added BOTH_BITS_SET in place
of TRUE.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-20 17:40:39 +05:30
VNSL Durga
5e98df225c Xilskey: Modified efuse example
Added new lines in example prints.
Modified CRC calculation API name and
provided backward compatability.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:56:09 +05:30
VNSL Durga
2af5aa5b71 xilskey: Added BBRAM Ps example
To program Bbram PS example is provided this example
doesnot require any input.h file it doesnot contain any control
bits to be programmed.
It has only one feature is to program AES key into BBRAM.
User can edit the macro XSK_ZYNQMP_BBRAMPS_AES_KEY with the key
to be programmed.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:45 +05:30
VNSL Durga
507e33c593 Xilskey: Added Example for Zynq MP efusePs
To program efuse PS of Zynq MP user has to edit input.h file
in input.h file default all will be in FALSE sate which ever has to be
programmed need to be changed to TRUE.
In example after programming cache will be reloaded and keys will be
read from cache. If user wants read API can be changed to read from
efuse memory.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 18:55:36 +05:30
VNSL Durga
601ba781fb xilskey: Added DFT control bits programming
DFT JTAG disable and DFT mode disable control bits
programming and reading from status register are added
to efuse example and also input macros in xilskey_input.h
file.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-10-12 10:46:13 +05:30
VNSL Durga
cfeca6de75 xilskey: Updated copyright year information
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Acked-by: Nava kishore Manne <nava.manne@xilinx.com>
2015-09-01 16:25:10 +05:30
VNSL Durga
7ca1fb1844 xilskey: Modified example and input.h files
Example has been modified to support both Zynq PL eFuse and
Ultrascale eFuse. Added GPIO pins and channels to access
Master Jtag through GPIO and RSA key hash, AES's CRC value
input macros are also added.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:05:52 +05:30
VNSL Durga
e2ccad3c90 xilskey: Modified xilskey_efuse_example
Modified macro name of efuse PS XSK_EFUSEPL_RSA_KEY_HASH_STRING_SIZE
to XSK_EFUSEPS_RSA_KEY_HASH_STRING_SIZE.
Added missing goto.

Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
2015-08-05 21:04:35 +05:30
Nava kishore Manne
398cbdc152 lib:sw_services:standalone drivers license changes
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
2015-05-15 14:48:25 +05:30
Venkata Naga Sai Krishna Kolapalli
22b5585a09 xilskey_v2_1 : created new v2.1 version for xilskey.
This patch deprecates the old v2.0 version and created
new v2.1 version for xilskey library.

Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
2015-04-03 18:22:21 +05:30