As RSA enable and PPK revoke bits are having each 2 bits
in secure control register XilSKey_ZynqMp_EfusePs_ReadSecCtrlBits
API also returns status of 2 bits so added BOTH_BITS_SET in place
of TRUE.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Added new lines in example prints.
Modified CRC calculation API name and
provided backward compatability.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
To program Bbram PS example is provided this example
doesnot require any input.h file it doesnot contain any control
bits to be programmed.
It has only one feature is to program AES key into BBRAM.
User can edit the macro XSK_ZYNQMP_BBRAMPS_AES_KEY with the key
to be programmed.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
To program efuse PS of Zynq MP user has to edit input.h file
in input.h file default all will be in FALSE sate which ever has to be
programmed need to be changed to TRUE.
In example after programming cache will be reloaded and keys will be
read from cache. If user wants read API can be changed to read from
efuse memory.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
DFT JTAG disable and DFT mode disable control bits
programming and reading from status register are added
to efuse example and also input macros in xilskey_input.h
file.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Example has been modified to support both Zynq PL eFuse and
Ultrascale eFuse. Added GPIO pins and channels to access
Master Jtag through GPIO and RSA key hash, AES's CRC value
input macros are also added.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch deprecates the old v2.0 version and created
new v2.1 version for xilskey library.
Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
