Andrei-Liviu Simion
e0d0e0c1e7
dp: rx: Added core masks, shifts, and register values.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:57 +05:30
Andrei-Liviu Simion
835c8acbab
dp: rx: Added modification history.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:56 +05:30
Andrei-Liviu Simion
36aa085a0e
dp: rx: Added register values to override the lane count.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:36 +05:30
Andrei-Liviu Simion
aa7172ded9
dp: rx: Added register values for overriding the link rate.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:35 +05:30
Andrei-Liviu Simion
6ba1a4e305
dp: rx: Added interrupt masks.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:31 +05:30
Andrei-Liviu Simion
b59cb36747
dp: rx: Added vendor specific DPCD registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:25 +05:30
Andrei-Liviu Simion
8933949ee9
dp: rx: Added MST sideband messaging registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:24 +05:30
Andrei-Liviu Simion
1cb3119c90
dp: rx: Added MST MSA offsets for streams 2, 3, and 4.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:23 +05:30
Andrei-Liviu Simion
6157f90f4d
dp: rx: Added MSA registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:22 +05:30
Andrei-Liviu Simion
88d0e95839
dp: rx: Added DPCD configuration space registers.
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These are read-only values that represent the corresponding fields of the RX's
DPCD as seen by the TX.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:21 +05:30
Andrei-Liviu Simion
e6f4d82a4f
dp: rx: Added audio registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:21 +05:30
Andrei-Liviu Simion
c61b1b58d5
dp: rx: Added PHY configuration and status registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:19 +05:30
Andrei-Liviu Simion
f4b1a740fc
dp: rx: Added user video status registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:19 +05:30
Andrei-Liviu Simion
ea0c4f5d2b
dp: rx: Added core and protocol version registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:18 +05:30
Andrei-Liviu Simion
c054b6714c
dp: rx: Added DPCD fields.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:17 +05:30
Andrei-Liviu Simion
fe56ba6ef0
dp: rx: Added interrupt registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:16 +05:30
Andrei-Liviu Simion
252735630d
dp: rx: Added AUX channel status registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:15 +05:30
Andrei-Liviu Simion
342c11f3e5
dp: rx: Added receiver core configuration registers.
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Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:14 +05:30
Andrei-Liviu Simion
9817415d75
dp: rx: Added low-level core reads and writes.
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Created xdprx_hw.h.
Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:33:13 +05:30
