This patch modifies the mld file to chnage the version
from 5.4 to 5.3
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Removing NULL checking asserts for the data buffers where 0x00 is a possible
location. This will resolve the assert failures in xilsecure.
Signed-off-by: Bhavik Ameta <bameta@xilinx.com>
Acked-by: Srikanth Vemula <svemula@xilinx.com>
This patch modifies the SPIPS examples to support on
ZynqMP. In Zynq we are selecting hardware using chip
select 0 where as 1 in ZynqMP and also we will use
two different interrupt id's in two platforms.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add polled and interrupt examples to test
QSPIPSU flash interface.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add QSPIPSU flash interface support
in ZynqMP.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add support for spips peripheral
for ZynqMP in tcl file.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch add qspipsu peripheral support in
tcl file.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch removes clock related PM API ids defined in pm_defs.h
under sw_services and reassigns ids in serial order.
Signed-off-by: Rohit Fule <rohitf@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
Example has been modified to support both Zynq PL eFuse and
Ultrascale eFuse. Added GPIO pins and channels to access
Master Jtag through GPIO and RSA key hash, AES's CRC value
input macros are also added.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
As GpioPs and Timers are different for Ultrascale
all the calls related to Gpio and timers are saperated
by ifdefinitions.
Added new jtag function to access efuse of Ultrascale.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
To add ultrascale's efuse functionality added GPIO pins
and GPIO channels to access master JTAG, Fpga_Flag to tell
the FPGA series, AES CRC check flag and AES CRC value, RSA key
hash to program and RSA key hash read back and control and
secure parameters in PL instance and modified IR length
macro ZYNQ_TAP_IR_LENGTH to TAP_IR_LENGTH as IR length is same for both
Zynq and Ultrasale.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Removed redundant code by adding common API for clock
calculations.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modified tcl for adding macro in xparameters.h based on the
processor.As support is being added for Ultrascale and hence
supported processors are a9 and microblaze too, removed
supported peripherals option in mld.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch use --create option for armcc compiler
instead of rc option.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
When building xilsecure with '-rR' as arguments to make causes this error:
Compiling Xilsecure Library
make[1]: *** No rule to make target 'xsecure_sha.o', needed by 'libxilsecure.a'. Stop.
Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs' failed
make: *** [psu_cortexa53_0/libsrc/xilsecure_v1_0/src/make.libs] Error 2
Fixing this by adding a pattern rules matching the required object files.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Bhavik Ameta <bameta@xilinx.com>
When building xilffs with '-rR' as arguments to make causes this error:
Compiling XilFFs Library
gmake[2]: *** No rule to make target 'ff.o', needed by 'libxilffs.a'. Stop.
Makefile:27: recipe for target 'psu_cortexa53_0/libsrc/xilffs_v3_1/src/make.libs' failed
gmake[1]: *** [psu_cortexa53_0/libsrc/xilffs_v3_1/src/make.libs] Error 2
Fixing this by adding a pattern rules matching the required object files.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch modifies the file size as 8KB to test on emulation
platform. Since 8MB in emulation platform taking long time,
reduced file size to 8KB.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
Modify makefile to check for IAR compiler to use --create and
remove individual checks for all other compilers.
Signed-off-by: Harini Katakam <harinik@xilinx.com>
Reviewed-by: Anirudha Sarangi <anirudh@xilinx.com>
This patch does card detection check before disk
status call, since BaseAddress and card detect
variables will be assigned in disk_status API.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
Reviewed-by: Harini Katakam <harinik@xilinx.com>
This patch removes Change Bus Speed, Clock Freq, SelectCard
API's in glue layer since driver is taking care of those
things.
Signed-off-by: Srinivas Goud <sgoud@xilinx.com>
This patch modifies .mld and .tcl files to provide the
Read_Only option to the user. By default this option
is false.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch removes compilation errors in xilffs library.
This errors are coming when we configure ReadOnly, use
StringFunctions and use LFN options. This patch also does
configuring _FS_READONLY macro based on the option given
by the user.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch removes compilation errors by enabling the
IntelStmFlashInitialize function for STM flash family
on DC1.
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
This patch modifies the check for whether bank crossover
in flash read functions for parallel case. This will fix
the bug where wrap around occurs to the top of flash when
reading very bottom..
Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com>
