High speed/wide bus operations involve data transfers. Hence these buffers should be aligned and flushed/invalidated where required. Signed-off-by: Harini Katakam <harinik@xilinx.com>
Make changes to enable use of data cache. Signed-off-by: Harini Katakam <harinik@xilinx.com> Acked-by: Anirudha Sarangi <anirudh@xilinx.com>
Added initial support Xilinx Embedded Software. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
