68 lines
5.1 KiB
HTML
Executable file
68 lines
5.1 KiB
HTML
Executable file
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<div id="projectname">qspipsu
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<div id="projectbrief">Xilinx SDK Drivers API Documentation</div>
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<li class="current"><a href="index.html"><span>Overview</span></a></li>
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<li><a href="annotated.html"><span>Data Structures</span></a></li>
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<li><a href="globals.html"><span>APIs</span></a></li>
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<div class="title">qspipsu Documentation</div> </div>
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<div class="contents">
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<div class="textblock"><p>This is the header file for the implementation of QSPIPSU driver.Generic QSPI interface allows for communication to any QSPI slave device. GQSPI contains a GENFIFO into which the bus transfers required are to be pushed with appropriate configuration. The controller provides TX and RX FIFO's and a DMA to be used for RX transfers. The controller executes each GENFIFO entry noting the configuration and places data on the bus as required</p>
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<p>The different options in GENFIFO are as follows: IMM_DATA : Can be one byte of data to be transmitted, number of clocks or number of bytes in transfer. DATA_XFER : Indicates that data/clocks need to be transmitted or received. EXPONENT : e when 2^e bytes are involved in transfer. SPI_MODE : SPI/Dual SPI/Quad SPI CS : Lower or Upper CS or Both Bus : Lower or Upper Bus or Both TX : When selected, controller transmits data in IMM or fetches number of bytes mentioned form TX FIFO. If not selected, dummies are pumped. RX : When selected, controller receives and fills the RX FIFO/allows RX DMA of requested number of bytes. If not selected, RX data is discarded. Stripe : Byte stripe over lower and upper bus or not. Poll : Polls response to match for to a set value (used along with POLL_CFG registers) and then proceeds to next GENFIFO entry. This feature is not currently used in the driver.</p>
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<p>GENFIFO has manual and auto start options. All DMA requests need a 4-byte aligned destination address buffer and size of transfer should also be a multiple of 4. This driver supports DMA RX and IO RX.</p>
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<p>Initialization: This driver uses the GQSPI controller with RX DMA. It supports both interrupt and polled transfers. Manual start of GENFIFO is used. <a class="el" href="group__qspipsu__v1__0.html#ga78067f00df477a415138cf035d5c3c1c" title="Initializes a specific XQspiPsu instance such that the driver is ready to use. ">XQspiPsu_CfgInitialize()</a> initializes the instance variables. Additional setting can be done using SetOptions/ClearOptions functions and SelectSlave function.</p>
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<p>Transfer: Polled or Interrupt transfers can be done. The transfer function needs the message(s) to be transmitted in the form of an array of type <a class="el" href="struct_x_qspi_psu___msg.html" title="This typedef contains configuration information for a flash message. ">XQspiPsu_Msg</a>. This is supposed to contain the byte count and any TX/RX buffers as required. Flags can be used indicate further information such as whether the message should be striped. The transfer functions form and write GENFIFO entries, check the status of the transfer and report back to the application when done.</p>
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<pre>
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MODIFICATION HISTORY:</pre><pre>Ver Who Date Changes
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----- --- -------- -----------------------------------------------.
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1.0 hk 08/21/14 First release
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sk 03/13/15 Added IO mode support.
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hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
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Clear and disbale DMA interrupts/status in abort.
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Use DMA DONE bit instead of BUSY as recommended.
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sk 04/24/15 Modified the code according to MISRAC-2012.
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sk 06/17/15 Removed NULL checks for Rx/Tx buffers. As
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writing/reading from 0x0 location is permitted.</pre><pre></pre> </div></div><!-- contents -->
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