stv0g/embeddedsw
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity
embeddedsw/XilinxProcessorIPLib/drivers/video_common
History
Andrei-Liviu Simion 0194e3fc17 video_common: Fixed pixel clock calculation for interlaced modes. 
In interlaced mode, the vertical total lines for frames 0 and 1 may not
necessarily be equal (off by 1). The pixel clock calculation needs to take this
into account by taking their average.

Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com>
2015-04-26 10:34:48 +05:30
..
data video_common: Added Makefile and updated MDD for compilation. 2015-04-26 10:31:57 +05:30
doc/html/api video_common: Added Doxygen documentation. 2015-04-26 10:34:27 +05:30
examples video_common: edid: Added function headers for commenting. 2015-04-26 10:34:20 +05:30
src video_common: Fixed pixel clock calculation for interlaced modes. 2015-04-26 10:34:48 +05:30