58b9762523
This patch modified source code with Misra c guidline Signed-off-by: Om Mishra <omprakas@xilinx.com>
257 lines
9.8 KiB
C
Executable file
257 lines
9.8 KiB
C
Executable file
/******************************************************************************
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*
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* Copyright (C) 2010 - 2014 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xgpiops.h
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*
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* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
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* Controller.
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*
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* The GPIO Controller supports the following features:
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* - 4 banks
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* - Masked writes (There are no masked reads)
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* - Bypass mode
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* - Configurable Interrupts (Level/Edge)
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*
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* This driver is intended to be RTOS and processor independent. Any needs for
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* dynamic memory management, threads or thread mutual exclusion, virtual
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* memory, or cache control must be satisfied by the layer above this driver.
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* This driver supports all the features listed above, if applicable.
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*
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* <b>Driver Description</b>
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*
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* The device driver enables higher layer software (e.g., an application) to
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* communicate to the GPIO.
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*
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* <b>Interrupts</b>
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*
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* The driver provides interrupt management functions and an interrupt handler.
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* Users of this driver need to provide callback functions. An interrupt handler
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* example is available with the driver.
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*
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* <b>Threads</b>
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*
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* This driver is not thread safe. Any needs for threads or thread mutual
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* exclusion must be satisfied by the layer above this driver.
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*
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* <b>Asserts</b>
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*
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* Asserts are used within all Xilinx drivers to enforce constraints on argument
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* values. Asserts can be turned off on a system-wide basis by defining, at
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* compile time, the NDEBUG identifier. By default, asserts are turned on and it
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* is recommended that users leave asserts on during development.
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*
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* <b>Building the driver</b>
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*
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* The XGpioPs driver is composed of several source files. This allows the user
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* to build and link only those parts of the driver that are necessary.
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* <br><br>
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.00a sv 01/15/10 First Release
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* 1.01a sv 04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
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* XGpioPs_GetMode, XGpioPs_GetModePin as they are not
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* relevant to Zynq device.The interrupts are disabled
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* for output pins on all banks during initialization.
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* 1.02a hk 08/22/13 Added low level reset API
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* 2.1 hk 04/29/14 Use Input data register DATA_RO for read. CR# 771667.
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* 2.2 sk 10/13/14 Used Pin number in Bank instead of pin number
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* passed to APIs. CR# 822636
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*
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* </pre>
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*
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******************************************************************************/
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#ifndef XGPIOPS_H /* prevent circular inclusions */
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#define XGPIOPS_H /* by using protection macros */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/***************************** Include Files *********************************/
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#include "xstatus.h"
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#include "xgpiops_hw.h"
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/************************** Constant Definitions *****************************/
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/** @name Interrupt types
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* @{
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* The following constants define the interrupt types that can be set for each
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* GPIO pin.
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*/
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#define XGPIOPS_IRQ_TYPE_EDGE_RISING 0x00U /**< Interrupt on Rising edge */
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#define XGPIOPS_IRQ_TYPE_EDGE_FALLING 0x01U /**< Interrupt Falling edge */
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#define XGPIOPS_IRQ_TYPE_EDGE_BOTH 0x02U /**< Interrupt on both edges */
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#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH 0x03U /**< Interrupt on high level */
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#define XGPIOPS_IRQ_TYPE_LEVEL_LOW 0x04U /**< Interrupt on low level */
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/*@}*/
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#define XGPIOPS_BANK0 0x00U /**< GPIO Bank 0 */
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#define XGPIOPS_BANK1 0x01U /**< GPIO Bank 1 */
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#define XGPIOPS_BANK2 0x02U /**< GPIO Bank 2 */
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#define XGPIOPS_BANK3 0x03U /**< GPIO Bank 3 */
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#define XGPIOPS_MAX_BANKS 0x04U /**< Max banks in a GPIO device */
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#define XGPIOPS_BANK_MAX_PINS (u32)32 /**< Max pins in a GPIO bank */
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#define XGPIOPS_DEVICE_MAX_PIN_NUM (u32)118 /*< Max pins in the GPIO device
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* 0 - 31, Bank 0
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* 32 - 53, Bank 1
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* 54 - 85, Bank 2
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* 86 - 117, Bank 3
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*/
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/**************************** Type Definitions *******************************/
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/****************************************************************************/
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/**
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* This handler data type allows the user to define a callback function to
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* handle the interrupts for the GPIO device. The application using this
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* driver is expected to define a handler of this type, to support interrupt
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* driven mode. The handler executes in an interrupt context such that minimal
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* processing should be performed.
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*
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* @param CallBackRef is a callback reference passed in by the upper layer
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* when setting the callback functions for a GPIO bank. It is
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* passed back to the upper layer when the callback is invoked. Its
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* type is not important to the driver component, so it is a void
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* pointer.
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* @param Bank is the bank for which the interrupt status has changed.
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* @param Status is the Interrupt status of the GPIO bank.
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*
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*****************************************************************************/
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typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
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/**
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* This typedef contains configuration information for a device.
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*/
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typedef struct {
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u16 DeviceId; /**< Unique ID of device */
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u32 BaseAddr; /**< Register base address */
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} XGpioPs_Config;
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/**
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* The XGpioPs driver instance data. The user is required to allocate a
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* variable of this type for the GPIO device in the system. A pointer
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* to a variable of this type is then passed to the driver API functions.
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*/
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typedef struct {
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XGpioPs_Config GpioConfig; /**< Device configuration */
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u32 IsReady; /**< Device is initialized and ready */
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XGpioPs_Handler Handler; /**< Status handlers for all banks */
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void *CallBackRef; /**< Callback ref for bank handlers */
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} XGpioPs;
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Function Prototypes ******************************/
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/*
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* Functions in xgpiops.c
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*/
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s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
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u32 EffectiveAddr);
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/*
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* Bank APIs in xgpiops.c
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*/
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u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
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void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
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void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
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u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
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void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
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u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
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void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank);
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/*
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* Pin APIs in xgpiops.c
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*/
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u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
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void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
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void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
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u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
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void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
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u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
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/*
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* Diagnostic functions in xgpiops_selftest.c
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*/
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s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
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/*
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* Functions in xgpiops_intr.c
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*/
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/*
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* Bank APIs in xgpiops_intr.c
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*/
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void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
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void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
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u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
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u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
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void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
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void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
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u32 IntrPolarity, u32 IntrOnAny);
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void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
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u32 *IntrPolarity, u32 *IntrOnAny);
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void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
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XGpioPs_Handler FuncPointer);
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void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
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/*
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* Pin APIs in xgpiops_intr.c
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*/
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void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
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u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
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void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
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void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
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u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
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u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
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void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
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/*
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* Functions in xgpiops_sinit.c
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*/
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XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
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#ifdef __cplusplus
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}
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#endif
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#endif /* end of protection macro */
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