382 lines
11 KiB
C
382 lines
11 KiB
C
/******************************************************************************
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* Copyright (C) 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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******************************************************************************/
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#include "xpfw_interrupts.h"
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#include "xpfw_events.h"
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#include "xpfw_core.h"
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#include "xil_exception.h"
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/**
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* InterruptRegister holds the state of the IRQ Enable Register
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*
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* @note IRQ_ENABLE register is write-only, So its state is stored here
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*/
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static u32 InterruptRegsiter;
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/**
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* This list of IDs enables re-ordering of Events for GPI1 as per user's priority
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*/
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static u32 Gpi1EventIdList[] = {
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XPFW_EV_APB_AIB_ERROR,
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XPFW_EV_AXI_AIB_ERROR,
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XPFW_EV_ERROR_2,
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XPFW_EV_ERROR_1,
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XPFW_EV_ACPU_3_DBG_PWRUP,
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XPFW_EV_ACPU_2_DBG_PWRUP,
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XPFW_EV_ACPU_1_DBG_PWRUP,
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XPFW_EV_ACPU_0_DBG_PWRUP,
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XPFW_EV_FPD_WAKE_GIC_PROXY,
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XPFW_EV_MIO_WAKE_5,
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XPFW_EV_MIO_WAKE_4,
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XPFW_EV_MIO_WAKE_3,
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XPFW_EV_MIO_WAKE_2,
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XPFW_EV_MIO_WAKE_1,
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XPFW_EV_MIO_WAKE_0,
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XPFW_EV_DAP_RPU_WAKE,
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XPFW_EV_DAP_FPD_WAKE,
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XPFW_EV_USB_1_WAKE,
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XPFW_EV_USB_0_WAKE,
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XPFW_EV_R5_1_WAKE,
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XPFW_EV_R5_0_WAKE,
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XPFW_EV_ACPU_3_WAKE,
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XPFW_EV_ACPU_2_WAKE,
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XPFW_EV_ACPU_1_WAKE,
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XPFW_EV_ACPU_0_WAKE
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};
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static u32 Gpi2EventIdList[] = {
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XPFW_EV_VCC_INT_FP_DISCONNECT,
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XPFW_EV_VCC_INT_DISCONNECT,
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XPFW_EV_VCC_AUX_DISCONNECT,
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XPFW_EV_DBG_ACPU3_RST_REQ,
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XPFW_EV_DBG_ACPU2_RST_REQ,
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XPFW_EV_DBG_ACPU1_RST_REQ,
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XPFW_EV_DBG_ACPU0_RST_REQ,
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XPFW_EV_CP_ACPU3_RST_REQ,
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XPFW_EV_CP_ACPU2_RST_REQ,
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XPFW_EV_CP_ACPU1_RST_REQ,
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XPFW_EV_CP_ACPU0_RST_REQ,
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XPFW_EV_DBG_RCPU1_RST_REQ,
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XPFW_EV_DBG_RCPU0_RST_REQ,
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XPFW_EV_R5_1_SLEEP,
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XPFW_EV_R5_0_SLEEP,
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XPFW_EV_ACPU_3_SLEEP,
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XPFW_EV_ACPU_2_SLEEP,
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XPFW_EV_ACPU_1_SLEEP,
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XPFW_EV_ACPU_0_SLEEP
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};
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static u32 Gpi3EventIdList[] = {
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XPFW_EV_PL_GPI_31,
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XPFW_EV_PL_GPI_30,
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XPFW_EV_PL_GPI_29,
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XPFW_EV_PL_GPI_28,
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XPFW_EV_PL_GPI_27,
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XPFW_EV_PL_GPI_26,
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XPFW_EV_PL_GPI_25,
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XPFW_EV_PL_GPI_24,
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XPFW_EV_PL_GPI_23,
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XPFW_EV_PL_GPI_22,
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XPFW_EV_PL_GPI_21,
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XPFW_EV_PL_GPI_20,
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XPFW_EV_PL_GPI_19,
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XPFW_EV_PL_GPI_18,
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XPFW_EV_PL_GPI_17,
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XPFW_EV_PL_GPI_16,
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XPFW_EV_PL_GPI_15,
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XPFW_EV_PL_GPI_14,
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XPFW_EV_PL_GPI_13,
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XPFW_EV_PL_GPI_12,
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XPFW_EV_PL_GPI_11,
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XPFW_EV_PL_GPI_10,
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XPFW_EV_PL_GPI_9,
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XPFW_EV_PL_GPI_8,
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XPFW_EV_PL_GPI_7,
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XPFW_EV_PL_GPI_6,
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XPFW_EV_PL_GPI_5,
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XPFW_EV_PL_GPI_4,
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XPFW_EV_PL_GPI_3,
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XPFW_EV_PL_GPI_2,
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XPFW_EV_PL_GPI_1,
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XPFW_EV_PL_GPI_0,
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};
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static void XPfw_NullHandler(void)
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{
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/**
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* This should never be called.
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* TODO: Set PMUFW Error register
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*/
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fw_printf("Error: NullHandler Triggered!\r\n");
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}
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static void XPfw_InterruptPwrUpHandler(void)
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{
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XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_REQ_PWRUP);
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if (XST_SUCCESS != Status) {
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fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
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XPFW_EV_REQ_PWRUP);
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}
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}
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static void XPfw_InterruptPwrDnHandler(void)
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{
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XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_REQ_PWRDN);
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if (XST_SUCCESS != Status) {
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fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
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XPFW_EV_REQ_PWRDN);
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}
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}
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static void XPfw_InterruptSecLockHandler(void)
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{
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XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_CSU_SEC_LOCK);
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if (XST_SUCCESS != Status) {
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fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
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XPFW_EV_CSU_SEC_LOCK);
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}
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}
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static void XPfw_InterruptGpi0Handler(void)
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{
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XStatus Status = XPfw_CoreDispatchEvent(XPFW_EV_MB_FAULT);
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if (XST_SUCCESS != Status) {
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fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
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XPFW_EV_MB_FAULT);
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}
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}
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static void XPfw_InterruptGpi1Handler(void)
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{
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u32 Index;
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for (Index = 0U; Index < ARRAYSIZE(Gpi1EventIdList); Index++) {
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u32 RegMask = XPfw_EventGetRegMask(Gpi1EventIdList[Index]);
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u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI1);
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if ((GpiRegVal & RegMask) == RegMask) {
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/* Dispatch the event to Registered Modules */
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XStatus Status = XPfw_CoreDispatchEvent(Gpi1EventIdList[Index]);
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if (XST_SUCCESS != Status) {
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fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
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Gpi1EventIdList[Index]);
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}
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}
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}
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}
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static void XPfw_InterruptGpi2Handler(void)
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{
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u32 Index;
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for (Index = 0U; Index < ARRAYSIZE(Gpi2EventIdList); Index++) {
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u32 RegMask = XPfw_EventGetRegMask(Gpi2EventIdList[Index]);
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u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI2);
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if ((GpiRegVal & RegMask) == RegMask) {
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/* Dispatch the event to Registered Modules */
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XStatus Status = XPfw_CoreDispatchEvent(Gpi2EventIdList[Index]);
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if (XST_SUCCESS != Status) {
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fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
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Gpi2EventIdList[Index]);
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}
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}
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}
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}
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static void XPfw_InterruptGpi3Handler(void)
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{
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u32 Index;
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for (Index = 0U; Index < ARRAYSIZE(Gpi3EventIdList); Index++) {
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u32 RegMask = XPfw_EventGetRegMask(Gpi3EventIdList[Index]);
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u32 GpiRegVal = XPfw_Read32(PMU_IOMODULE_GPI3);
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if ((GpiRegVal & RegMask) == RegMask) {
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/* Dispatch the event to Registered Modules */
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XStatus Status = XPfw_CoreDispatchEvent(Gpi3EventIdList[Index]);
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if (XST_SUCCESS != Status) {
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fw_printf("Warning: Failed to dispatch Event ID: %d\r\n",
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Gpi3EventIdList[Index]);
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}
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}
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}
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}
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/* TODO: For all the Interrupt Handlers-> Report Error */
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static void XPfw_InterruptRtcAlaramHandler(void)
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{
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(void)XPfw_CoreDispatchEvent(XPFW_EV_RTC_ALARM);
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}
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static void XPfw_InterruptRtcSecondsmHandler(void)
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{
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(void)XPfw_CoreDispatchEvent(XPFW_EV_RTC_SECONDS);
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}
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static void XPfw_Pit1Handler(void)
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{
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(void)XPfw_CoreTickHandler();
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}
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static void XPfw_Ipi0Handler(void)
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{
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XStatus Status = XPfw_CoreDispatchIpi(0U);
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/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
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if (XST_SUCCESS != Status) {
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u32 Mask = XPfw_Read32(IPI_PMU_0_ISR);
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fw_printf("Error: Unhandled IPI received\r\n");
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XPfw_Write32(IPI_PMU_0_ISR, Mask);
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}
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}
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static void XPfw_Ipi1Handler(void)
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{
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XStatus Status = XPfw_CoreDispatchIpi(1U);
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/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
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if (XST_SUCCESS != Status) {
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u32 Mask = XPfw_Read32(IPI_PMU_1_ISR);
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fw_printf("Error: Unhandled IPI received\r\n");
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XPfw_Write32(IPI_PMU_1_ISR, Mask);
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}
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}
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static void XPfw_Ipi2Handler(void)
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{
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XStatus Status = XPfw_CoreDispatchIpi(2U);
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/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
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if(XST_SUCCESS != Status){
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u32 Mask = XPfw_Read32(IPI_PMU_2_ISR);
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fw_printf("Error: Unhandled IPI received\r\n");
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XPfw_Write32(IPI_PMU_2_ISR, Mask);
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}
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}
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static void XPfw_Ipi3Handler(void)
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{
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XStatus Status = XPfw_CoreDispatchIpi(3U);
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/* If no Mod has registered for IPI, Ack it to prevent re-triggering */
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if(XST_SUCCESS != Status){
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u32 Mask = XPfw_Read32(IPI_PMU_3_ISR);
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fw_printf("Error: Unhandled IPI received\r\n");
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XPfw_Write32(IPI_PMU_3_ISR, Mask);
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}
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}
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static struct HandlerTable g_TopLevelInterruptTable[] = {
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{PMU_IOMODULE_IRQ_PENDING_RTC_ALARM_MASK, XPfw_InterruptRtcAlaramHandler},
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{PMU_IOMODULE_IRQ_PENDING_RTC_EVERY_SECOND_MASK, XPfw_InterruptRtcSecondsmHandler},
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{PMU_IOMODULE_IRQ_PENDING_CORRECTABLE_ECC_MASK, XPfw_NullHandler},
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{PMU_IOMODULE_IRQ_PENDING_INV_ADDR_MASK, XPfw_NullHandler},
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{PMU_IOMODULE_IRQ_PENDING_IPI3_MASK, XPfw_Ipi3Handler},
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{PMU_IOMODULE_IRQ_PENDING_IPI2_MASK, XPfw_Ipi2Handler},
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{PMU_IOMODULE_IRQ_PENDING_IPI1_MASK, XPfw_Ipi1Handler},
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{PMU_IOMODULE_IRQ_PENDING_IPI0_MASK, XPfw_Ipi0Handler},
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{PMU_IOMODULE_IRQ_PENDING_PWR_UP_REQ_MASK, XPfw_InterruptPwrUpHandler},
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{PMU_IOMODULE_IRQ_PENDING_PWR_DN_REQ_MASK, XPfw_InterruptPwrDnHandler},
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{PMU_IOMODULE_IRQ_PENDING_ISO_REQ_MASK, XPfw_NullHandler},
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{PMU_IOMODULE_IRQ_PENDING_SW_RST_REQ_MASK, XPfw_NullHandler},
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{PMU_IOMODULE_IRQ_PENDING_HW_RST_REQ_MASK, XPfw_NullHandler},
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{PMU_IOMODULE_IRQ_PENDING_GPI3_MASK, XPfw_InterruptGpi3Handler},
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{PMU_IOMODULE_IRQ_PENDING_GPI2_MASK, XPfw_InterruptGpi2Handler},
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{PMU_IOMODULE_IRQ_PENDING_GPI1_MASK, XPfw_InterruptGpi1Handler},
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{PMU_IOMODULE_IRQ_PENDING_GPI0_MASK, XPfw_InterruptGpi0Handler},
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{PMU_IOMODULE_IRQ_PENDING_PIT3_MASK, XPfw_NullHandler},
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{PMU_IOMODULE_IRQ_PENDING_PIT2_MASK, XPfw_NullHandler},
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{PMU_IOMODULE_IRQ_PENDING_PIT1_MASK, XPfw_Pit1Handler},
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{PMU_IOMODULE_IRQ_PENDING_PIT0_MASK, XPfw_NullHandler},
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{PMU_IOMODULE_IRQ_PENDING_CSU_PMU_SEC_LOCK_MASK, XPfw_InterruptSecLockHandler}
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};
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void XPfw_InterruptInit(void)
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{
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XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, 0U);
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Xil_ExceptionDisable();
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XPfw_Write32(PMU_IOMODULE_IRQ_ACK, 0xffffffffU);
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InterruptRegsiter = 0U;
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}
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void XPfw_InterruptStart(void)
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{
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XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter);
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Xil_ExceptionEnable();
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}
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void XPfw_InterruptHandler(void)
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{
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u32 l_IrqReg;
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u32 l_index;
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if (XST_SUCCESS == XPfw_CoreIsReady()) {
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/* Latch the IRQ_PENDING register into a local variable */
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l_IrqReg = XPfw_Read32(PMU_IOMODULE_IRQ_PENDING);
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/* Loop through the Handler Table and handle the trigger interrupts */
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for (l_index = 0U; l_index < ARRAYSIZE(g_TopLevelInterruptTable);
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l_index++) {
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if ((l_IrqReg & g_TopLevelInterruptTable[l_index].Mask)
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== g_TopLevelInterruptTable[l_index].Mask) {
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/* Call the Handler */
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g_TopLevelInterruptTable[l_index].Handler();
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/* ACK the Interrupt */
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XPfw_Write32(PMU_IOMODULE_IRQ_ACK,
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g_TopLevelInterruptTable[l_index].Mask);
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}
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}
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} else {
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/* We shouldnt be here before Init, but we are.. So disable the Interrupts */
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/* Init will enable only the required interrupts */
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XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, 0U);
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XPfw_Write32(PMU_IOMODULE_IRQ_ACK, 0xffffffffU);
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}
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}
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void XPfw_InterruptDisable(u32 Mask)
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{
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InterruptRegsiter = InterruptRegsiter & (~Mask);
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XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter);
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}
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void XPfw_InterruptEnable(u32 Mask)
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{
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InterruptRegsiter = InterruptRegsiter | Mask;
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XPfw_Write32(PMU_IOMODULE_IRQ_ENABLE, InterruptRegsiter);
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}
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