3b7b32fe0e
PHY ready check is now done immediately before initiating link training. In pass-through designs where the TX reference clock is derived from the input RX clock, having no RX clock would have resulted the TX initialization failing due to PHY ready time out. This patch allows TX and RX to both be initialized in any order. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> Acked-by: Shadul Shaikh <shaduls@xilinx.com> |
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