Sarat Chand Savitala 2f7303ed76 sw_apps:zynqmp_fsbl: Load address configuration in DDR for PL ... Changed the location of temporary ddr address definition. This address is for storing PL bitstream temporarily. User can change this address till support is provided in bootgen (for load address configuration for PL). Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com> Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>		2015-07-17 20:20:58 +05:30
..
freertos_hello_world	lib:sw_apps:get_cells is changed to ::hsi::get_cells	2015-07-13 17:38:07 +05:30
lwip_echo_server	lib:sw_apps:standalone drivers license changes	2015-05-16 14:37:24 +05:30
openamp_echo_test	lib:sw_apps:get_cells is changed to ::hsi::get_cells	2015-07-13 17:38:07 +05:30
openamp_matrix_multiply	lib:sw_apps:get_cells is changed to ::hsi::get_cells	2015-07-13 17:38:07 +05:30
openamp_rpc_demo	lib:sw_apps:get_cells is changed to ::hsi::get_cells	2015-07-13 17:38:07 +05:30
rsa_auth_app	lib:sw_apps:standalone drivers license changes	2015-05-16 14:37:24 +05:30
xilkernel_thread_demo	lib:sw_apps:standalone drivers license changes	2015-05-16 14:37:24 +05:30
zynq_fsbl	Syncing ESW zynq_fsbl with HEAD zynq_fsbl	2015-07-09 18:56:17 +05:30
zynqmp_fsbl	sw_apps:zynqmp_fsbl: Load address configuration in DDR for PL	2015-07-17 20:20:58 +05:30
zynqmp_pmufw	lib:sw_apps:get_cells is changed to ::hsi::get_cells	2015-07-13 17:38:07 +05:30