Xilinx Embedded Software (embeddedsw) Development
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Mirela Simonovic 13e22f9eb0 PMUFW: PM: pm_master: Added default requirements, set upon entering active state
-Added default requirements field in PmRequirements structure
-Added notification of master when primary processor switches from
 forced powerdown to active state. Master has to make sure that all
 default requirements gets set before primary processor enters active
 state.
-In PmMasterNotify, changed behavior when wake event is received:
 if primary processor is in sleep state, everything works as before,
 if primary processor is in forced powerdown, default requirements
 are requested and configured
-In PmRequirementReleaseAll added a check is master using slave and
 if yes, usage flag and requirements are cleared
-Added PmRequirementRequestDefault function called before primary
 processor switches from forced powerdown to active. Function
 automatically requests all default requirements which are later
 configured by PmRequirementUpdateScheduled
-In PmRequirementUpdateScheduled when swapping requirements added
 a check whether master has default requirements. If yes, default
 reqs are saved as next reqs instead of current. Default requirements
 have priority over current requirement. Example: RPU0 keeps boot code
 in one TCM bank and when booted, during the runtime, it keeps that
 bank in retention. For this bank RPU0 should have default requirements
 = on state, and when it boots up it can request retention. If default
 requirements wouldn't exist, it would have to request for boot bank to
 switch from retention to on before calling self suspend, just to get
 on state in scheduled reqs

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Jyotheeswar Reddy Mutthareddyvari <jyothee@xilinx.com>
2015-07-31 16:55:16 +05:30
doc doc: update pdf for standalone bsp 2015-05-22 11:35:21 +05:30
lib PMUFW: PM: pm_master: Added default requirements, set upon entering active state 2015-07-31 16:55:16 +05:30
mcap/linux mcap: linux: Fix race condition while programming bitfiles 2015-07-31 16:54:57 +05:30
ThirdParty/sw_services Update Tcl files to support MultiBd and Packaged Bd Designs 2015-07-31 16:55:01 +05:30
XilinxProcessorIPLib/drivers Update Tcl files to support MultiBd and Packaged Bd Designs 2015-07-31 16:55:01 +05:30
license.txt license: Add license.txt file 2015-07-31 16:54:47 +05:30
README.txt mcap: Add MCAP Linux Library 2015-07-31 16:54:48 +05:30

embeddedsw.git - repo for standalone software

All software is version less and divided into three directories
	- lib
		contains bsp, zynq fsbl and software services like xilisf
	- license.txt
		contains information about the various licenses and copyrights
	- XilinxProcessorIPLib
		contains all drivers
	- ThirdParty
		software from third party like light weight IP stack
	- mcap
		software for using MCAP interface on Ultra Scale boards to
		program 2nd level bitstream

Every driver/lib/apps/services has these sub-directories

1. data		- contains tcl, mdd, testapp tcl or header files used in SDK
2. doc		- documentation of source code in form of pdf or html
3. examples	- illustrating different use cases of driver
4. src		- driver interface code implementing functionality of IP


<repo>
|-XilinxProcessorIPLib
|	|- drivers
|		|- uartps
|			|- data
|			|- src
|			|- doc
|			|- examples
|
|-lib
|	|- bsp
|		|- standalone
|			|- data
|			|- src
|				|- cortexa9
|				|- microblaze
|				|- common
|				|- profile
|			|- doc
|		|- xilkernel
|			|- data
|			|- doc
|			|- src
|	|- sw_apps
|		|- zynq_fsbl [described below]
|	|- sw_services
|		|- xilffs
|		|- xilskey
|		|- xilmfs
|		|- xilrsa
|		|- xilflash
|		|- xilisf
|
|	Note - All these are libraries and utilize drivers
|
|-ThirdParty
|	|- sw_services
|        	|- lwip140
|
|-mcap
|	|-linux


Building FSBL from git:

FSBL has 3 directories.
	1. data - It contains files for SDK
	2. src  - It contains the FSBK source files
	3. misc - It contains miscelanious files required to
		  compile FSBL for zc702, zc706, zed and
		  microzed boards.
		  It also contains the ps7_init_gpl.[c/h] with gpl
		  header in respective board directories.


How to compile FSBL:
	1.Go to the Fsbl src directory "lib/sw_apps/zynq_fsbl/src/"
	2. make "BOARD=<>" "CC=<>"
		a. Values for BOARD  are zc702, zc706, zed, microzed
		b. Value for CC is arm-xilinx-eabi-gcc. Default value is also same.
	3.Give "make" to compile the fsbl with BSP. By default it is
	  built for zc702 board with arm-xilinx-eabi-gcc compiler
	4.Below are the examples for compiling for different options
		a. To generate Fsbl for zc706 board
			i.make "BOARD=zc706"
		b.To generate Fsbl for zc702 board with debug enable
		  and RSA support
			i.make "BOARD=zc702" "CFLAGS=-DFSBL_DEBUG_INFO -DRSA_SUPPORT"
		c.To generate Fsbl for zc706 board and compile with arm-xilinx-eabi-gcc
		  with MMC support
			i.make "BOARD=zc706" "CC=arm-xilinx-eabi-gcc" "CFLAGS=-DMMC_SUPPORT"