Xilinx Embedded Software (embeddedsw) Development

Harini Katakam 2b3a7c5e4c qspipsu: Switch to I/O mode before clearing RX FIFO ... There is a bug wherein the DMA listening to RX empty status goes busy if RX FIFO clear bit is set in the FIFO control register, even if there is no transfer request. So switch to I/O mode always to clear RX FIFO and restore the mode in the end. Signed-off-by: Harini Katakam <harinik@xilinx.com>		2015-03-19 13:55:46 +05:30
doc	Change Log for 2015.1	2015-03-01 09:56:03 +05:30
lib	sw_apps: modified openamp rpc demo application	2015-03-19 10:34:19 +05:30
ThirdParty/sw_services/xilopenamp	sw_services: openamp: removed platform specific APIs from library Signed-off-by: Kinjal Pravinbhai Patel <patelki@xilinx.com>	2015-03-19 10:34:18 +05:30
XilinxProcessorIPLib/drivers	qspipsu: Switch to I/O mode before clearing RX FIFO	2015-03-19 13:55:46 +05:30