qspipsu: Switch to I/O mode before clearing RX FIFO
There is a bug wherein the DMA listening to RX empty status goes busy if RX FIFO clear bit is set in the FIFO control register, even if there is no transfer request. So switch to I/O mode always to clear RX FIFO and restore the mode in the end. Signed-off-by: Harini Katakam <harinik@xilinx.com>
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2 changed files with 33 additions and 5 deletions
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@ -44,6 +44,7 @@
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* ----- --- -------- -----------------------------------------------
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* 1.0 hk 08/21/14 First release
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* sk 03/13/15 Added IO mode support.
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* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
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*
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* </pre>
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*
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@ -244,6 +245,7 @@ void XQspiPsu_Reset(XQspiPsu *InstancePtr)
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void XQspiPsu_Abort(XQspiPsu *InstancePtr)
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{
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u32 ConfigReg;
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/* Clear and disable interrupts */
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_ISR_OFFSET,
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@ -253,11 +255,36 @@ void XQspiPsu_Abort(XQspiPsu *InstancePtr)
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XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
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/* Clear FIFO */
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_FIFO_CTRL_OFFSET,
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XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK |
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XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK |
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XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK);
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if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_ISR_OFFSET) & XQSPIPSU_ISR_RXEMPTY_MASK)) {
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_FIFO_CTRL_OFFSET,
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XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK |
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XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK);
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}
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/*
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* Switch to IO mode to Clear RX FIFO. This is becuase of DMA behaviour
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* where it waits on RX empty and goes busy assuming there is data
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* to be transfered even if there is no request.
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*/
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if ((IntrStatus & XQSPIPSU_ISR_RXEMPTY_MASK) != 0) {
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ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_CFG_OFFSET);
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ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_CFG_OFFSET, ConfigReg);
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_FIFO_CTRL_OFFSET,
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XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK);
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if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
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ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
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XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
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XQSPIPSU_CFG_OFFSET, ConfigReg);
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}
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}
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/* Disable QSPIPSU */
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XQspiPsu_Disable(InstancePtr);
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@ -86,6 +86,7 @@
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* ----- --- -------- -----------------------------------------------.
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* 1.0 hk 08/21/14 First release
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* sk 03/13/15 Added IO mode support.
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* hk 03/18/15 Switch to I/O mode before clearing RX FIFO.
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*
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* </pre>
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*
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