Sarat Chand Savitala 2f7303ed76 sw_apps:zynqmp_fsbl: Load address configuration in DDR for PL ... Changed the location of temporary ddr address definition. This address is for storing PL bitstream temporarily. User can change this address till support is provided in bootgen (for load address configuration for PL). Signed-off-by: Sarat Chand Savitala <saratcha@xilinx.com> Acked-by: Krishna Chaitanya Patakamuri <kpataka@xilinx.com>		2015-07-17 20:20:58 +05:30
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bsp	bsp: a53: changed the makefile to take compiler name from cpu tcl	2015-07-14 10:51:59 +05:30
sw_apps	sw_apps:zynqmp_fsbl: Load address configuration in DDR for PL	2015-07-17 20:20:58 +05:30
sw_services	xilskey: Changed supported peripheral name to ps7_cortexa9.	2015-07-09 19:47:17 +05:30