3f6f63b07e
This patch unifies standalone for both Zynq and ZynqMP platforms. Also follows misrac guidelines. Signed-off-by: Venkata Naga Sai Krishna Kolapalli <venkatan@xilinx.com>
375 lines
9.6 KiB
C
375 lines
9.6 KiB
C
/******************************************************************************
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*
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* Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved.
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*
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* This file contains confidential and proprietary information of Xilinx, Inc.
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* and is protected under U.S. and international copyright and other
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* intellectual property laws.
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*
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* DISCLAIMER
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* This disclaimer is not a license and does not grant any rights to the
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* materials distributed herewith. Except as otherwise provided in a valid
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* license issued to you by Xilinx, and to the maximum extent permitted by
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* applicable law:
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* (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND
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* XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED,
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* OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY,
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* NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE
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* and
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* (2) Xilinx shall not be liable (whether in contract or tort, including
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* negligence, or under any other theory of liability) for any loss or damage of
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* any kind or nature related to, arising under or in connection with these
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* materials, including for any direct, or any indirect, special, incidental,
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* or consequential loss or damage (including loss of data, profits, goodwill,
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* or any type of loss or damage suffered as a result of any action brought
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* by a third party) even if such damage or loss was reasonably foreseeable
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* or Xilinx had been advised of the possibility of the same.
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*
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* CRITICAL APPLICATIONS
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* Xilinx products are not designed or intended to be fail-safe, or for use in
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* any application requiring fail-safe performance, such as life-support or
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* safety devices or systems, Class III medical devices, nuclear facilities,
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* applications related to the deployment of airbags, or any other applications
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* that could lead to death, personal injury, or severe property or environmental
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* damage (individually and collectively, "Critical Applications").
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* Customer assumes the sole risk and liability of any use of Xilinx products in
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* Critical Applications, subject only to applicable laws and regulations
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* governing limitations on product liability.
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*
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* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE
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* AT ALL TIMES.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xil_testcache.c
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*
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* Contains utility functions to test cache.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a hbm 07/28/09 Initial release
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* 4.1 asa 05/09/14 Ensured that the address uses for cache test is aligned
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* cache line.
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* </pre>
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*
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* @note
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*
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* This file contain functions that all operate on HAL.
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*
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******************************************************************************/
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#ifdef __ARM__
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#include "xil_cache.h"
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#include "xil_testcache.h"
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#include "xil_types.h"
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#include "xpseudo_asm.h"
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#ifdef __aarch64__
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#include "xreg_cortexa53.h"
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#else
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#include "xreg_cortexr5.h"
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#endif
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extern void xil_printf(const char8 *ctrl1, ...);
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#define DATA_LENGTH 128
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#ifdef __aarch64__
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static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
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#else
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static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
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#endif
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/**
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* Perform DCache range related API test such as Xil_DCacheFlushRange and
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* Xil_DCacheInvalidateRange. This test function writes a constant value
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* to the Data array, flushes the range, writes a new value, then invalidates
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* the corresponding range.
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*
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* @return
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*
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* - 0 is returned for a pass
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* - -1 is returned for a failure
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*/
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s32 Xil_TestDCacheRange(void)
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{
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s32 Index;
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s32 Status = 0;
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u32 CtrlReg;
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INTPTR Value;
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xil_printf("-- Cache Range Test --\n\r");
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A00505;
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xil_printf(" initialize Data done:\r\n");
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Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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xil_printf(" flush range done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0xA0A00505) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Flush worked\r\n");
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}
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else {
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xil_printf("Error: flush dcache range not working\r\n");
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}
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A0C505;
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Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = Index + 3;
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Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
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xil_printf(" invalidate dcache range done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0xA0A0A05;
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0xA0A0A05) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Invalidate worked\r\n");
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}
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else {
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xil_printf("Error: Invalidate dcache range not working\r\n");
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}
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xil_printf("-- Cache Range Test Complete --\r\n");
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return Status;
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}
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/**
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* Perform DCache all related API test such as Xil_DCacheFlush and
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* Xil_DCacheInvalidate. This test function writes a constant value
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* to the Data array, flushes the DCache, writes a new value, then invalidates
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* the DCache.
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*
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* @return
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* - 0 is returned for a pass
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* - -1 is returned for a failure
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*/
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s32 Xil_TestDCacheAll(void)
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{
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s32 Index;
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s32 Status;
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INTPTR Value;
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u32 CtrlReg;
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xil_printf("-- Cache All Test --\n\r");
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x50500A0A;
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xil_printf(" initialize Data done:\r\n");
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Xil_DCacheFlush();
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xil_printf(" flush all done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0x50500A0A) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Flush all worked\r\n");
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}
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else {
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xil_printf("Error: Flush dcache all not working\r\n");
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}
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x505FFA0A;
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Xil_DCacheFlush();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = Index + 3;
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Xil_DCacheInvalidate();
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xil_printf(" invalidate all done\r\n");
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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for (Index = 0; Index < DATA_LENGTH; Index++)
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Data[Index] = 0x50CFA0A;
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dsb();
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#ifdef __aarch64__
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CtrlReg = mfcp(SCTLR_EL3);
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CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
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mtcp(SCTLR_EL3,CtrlReg);
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#else
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CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
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CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
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mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
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#endif
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dsb();
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Status = 0;
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for (Index = 0; Index < DATA_LENGTH; Index++) {
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Value = Data[Index];
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if (Value != 0x50CFA0A) {
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Status = -1;
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xil_printf("Data[%d] = %x\r\n", Index, Value);
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break;
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}
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}
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if (!Status) {
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xil_printf(" Invalidate all worked\r\n");
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}
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else {
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xil_printf("Error: Invalidate dcache all not working\r\n");
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}
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xil_printf("-- DCache all Test Complete --\n\r");
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return Status;
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}
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/**
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* Perform Xil_ICacheInvalidateRange() on a few function pointers.
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*
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* @return
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*
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* - 0 is returned for a pass
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* The function will hang if it fails.
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*/
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s32 Xil_TestICacheRange(void)
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{
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
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Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
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xil_printf("-- Invalidate icache range done --\r\n");
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return 0;
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}
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/**
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* Perform Xil_ICacheInvalidate().
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*
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* @return
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*
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* - 0 is returned for a pass
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* The function will hang if it fails.
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*/
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s32 Xil_TestICacheAll(void)
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{
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Xil_ICacheInvalidate();
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xil_printf("-- Invalidate icache all done --\r\n");
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return 0;
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}
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#endif
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